Reinforcement Learning based Illumination Controller (RLIC)  v1.0
MIMXRT1021.h
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1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1021CAF4A
4 ** MIMXRT1021CAG4A
5 ** MIMXRT1021DAF5A
6 ** MIMXRT1021DAG5A
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: IMXRT1020RM Rev.1, 12/2018 | IMXRT1020SRM Rev.3
15 ** Version: rev. 1.1, 2019-04-29
16 ** Build: b201123
17 **
18 ** Abstract:
19 ** CMSIS Peripheral Access Layer for MIMXRT1021
20 **
21 ** Copyright 1997-2016 Freescale Semiconductor, Inc.
22 ** Copyright 2016-2020 NXP
23 ** All rights reserved.
24 **
25 ** SPDX-License-Identifier: BSD-3-Clause
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 0.1 (2017-11-06)
32 ** Initial version.
33 ** - rev. 1.0 (2018-11-27)
34 ** Update header files to align with IMXRT1020RM Rev.1.
35 ** - rev. 1.1 (2019-04-29)
36 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
37 **
38 ** ###################################################################
39 */
40 
50 #ifndef _MIMXRT1021_H_
51 #define _MIMXRT1021_H_
55 #define MCU_MEM_MAP_VERSION 0x0100U
57 #define MCU_MEM_MAP_VERSION_MINOR 0x0001U
58 
59 
60 /* ----------------------------------------------------------------------------
61  -- Interrupt vector numbers
62  ---------------------------------------------------------------------------- */
63 
70 #define NUMBER_OF_INT_VECTORS 158
72 typedef enum IRQn {
73  /* Auxiliary constants */
74  NotAvail_IRQn = -128,
76  /* Core interrupts */
77  NonMaskableInt_IRQn = -14,
78  HardFault_IRQn = -13,
79  MemoryManagement_IRQn = -12,
80  BusFault_IRQn = -11,
81  UsageFault_IRQn = -10,
82  SVCall_IRQn = -5,
83  DebugMonitor_IRQn = -4,
84  PendSV_IRQn = -2,
85  SysTick_IRQn = -1,
87  /* Device specific interrupts */
88  DMA0_DMA16_IRQn = 0,
89  DMA1_DMA17_IRQn = 1,
90  DMA2_DMA18_IRQn = 2,
91  DMA3_DMA19_IRQn = 3,
92  DMA4_DMA20_IRQn = 4,
93  DMA5_DMA21_IRQn = 5,
94  DMA6_DMA22_IRQn = 6,
95  DMA7_DMA23_IRQn = 7,
96  DMA8_DMA24_IRQn = 8,
97  DMA9_DMA25_IRQn = 9,
98  DMA10_DMA26_IRQn = 10,
99  DMA11_DMA27_IRQn = 11,
100  DMA12_DMA28_IRQn = 12,
101  DMA13_DMA29_IRQn = 13,
102  DMA14_DMA30_IRQn = 14,
103  DMA15_DMA31_IRQn = 15,
104  DMA_ERROR_IRQn = 16,
105  CTI0_ERROR_IRQn = 17,
106  CTI1_ERROR_IRQn = 18,
107  CORE_IRQn = 19,
108  LPUART1_IRQn = 20,
109  LPUART2_IRQn = 21,
110  LPUART3_IRQn = 22,
111  LPUART4_IRQn = 23,
112  LPUART5_IRQn = 24,
113  LPUART6_IRQn = 25,
114  LPUART7_IRQn = 26,
115  LPUART8_IRQn = 27,
116  LPI2C1_IRQn = 28,
117  LPI2C2_IRQn = 29,
118  LPI2C3_IRQn = 30,
119  LPI2C4_IRQn = 31,
120  LPSPI1_IRQn = 32,
121  LPSPI2_IRQn = 33,
122  LPSPI3_IRQn = 34,
123  LPSPI4_IRQn = 35,
124  CAN1_IRQn = 36,
125  CAN2_IRQn = 37,
126  FLEXRAM_IRQn = 38,
127  KPP_IRQn = 39,
128  Reserved56_IRQn = 40,
129  GPR_IRQ_IRQn = 41,
130  Reserved58_IRQn = 42,
131  Reserved59_IRQn = 43,
132  Reserved60_IRQn = 44,
133  WDOG2_IRQn = 45,
134  SNVS_HP_WRAPPER_IRQn = 46,
135  SNVS_HP_WRAPPER_TZ_IRQn = 47,
136  SNVS_LP_HP_WRAPPER_IRQn = 48,
137  CSU_IRQn = 49,
138  DCP_IRQn = 50,
139  DCP_VMI_IRQn = 51,
140  Reserved68_IRQn = 52,
141  TRNG_IRQn = 53,
142  Reserved70_IRQn = 54,
143  BEE_IRQn = 55,
144  SAI1_IRQn = 56,
145  SAI2_IRQn = 57,
146  SAI3_RX_IRQn = 58,
147  SAI3_TX_IRQn = 59,
148  SPDIF_IRQn = 60,
149  PMU_IRQn = 61,
150  Reserved78_IRQn = 62,
151  TEMP_LOW_HIGH_IRQn = 63,
152  TEMP_PANIC_IRQn = 64,
153  USB_PHY_IRQn = 65,
154  Reserved82_IRQn = 66,
155  ADC1_IRQn = 67,
156  ADC2_IRQn = 68,
157  DCDC_IRQn = 69,
158  Reserved86_IRQn = 70,
159  Reserved87_IRQn = 71,
160  GPIO1_INT0_IRQn = 72,
161  GPIO1_INT1_IRQn = 73,
162  GPIO1_INT2_IRQn = 74,
163  GPIO1_INT3_IRQn = 75,
164  GPIO1_INT4_IRQn = 76,
165  GPIO1_INT5_IRQn = 77,
166  GPIO1_INT6_IRQn = 78,
167  GPIO1_INT7_IRQn = 79,
168  GPIO1_Combined_0_15_IRQn = 80,
169  GPIO1_Combined_16_31_IRQn = 81,
170  GPIO2_Combined_0_15_IRQn = 82,
171  GPIO2_Combined_16_31_IRQn = 83,
172  GPIO3_Combined_0_15_IRQn = 84,
173  GPIO3_Combined_16_31_IRQn = 85,
174  Reserved102_IRQn = 86,
175  Reserved103_IRQn = 87,
176  GPIO5_Combined_0_15_IRQn = 88,
177  GPIO5_Combined_16_31_IRQn = 89,
178  FLEXIO1_IRQn = 90,
179  Reserved107_IRQn = 91,
180  WDOG1_IRQn = 92,
181  RTWDOG_IRQn = 93,
182  EWM_IRQn = 94,
183  CCM_1_IRQn = 95,
184  CCM_2_IRQn = 96,
185  GPC_IRQn = 97,
186  SRC_IRQn = 98,
187  Reserved115_IRQn = 99,
188  GPT1_IRQn = 100,
189  GPT2_IRQn = 101,
190  PWM1_0_IRQn = 102,
191  PWM1_1_IRQn = 103,
192  PWM1_2_IRQn = 104,
193  PWM1_3_IRQn = 105,
194  PWM1_FAULT_IRQn = 106,
195  Reserved123_IRQn = 107,
196  FLEXSPI_IRQn = 108,
197  SEMC_IRQn = 109,
198  USDHC1_IRQn = 110,
199  USDHC2_IRQn = 111,
200  Reserved128_IRQn = 112,
201  USB_OTG1_IRQn = 113,
202  ENET_IRQn = 114,
203  ENET_1588_Timer_IRQn = 115,
204  XBAR1_IRQ_0_1_IRQn = 116,
205  XBAR1_IRQ_2_3_IRQn = 117,
206  ADC_ETC_IRQ0_IRQn = 118,
207  ADC_ETC_IRQ1_IRQn = 119,
208  ADC_ETC_IRQ2_IRQn = 120,
209  ADC_ETC_ERROR_IRQ_IRQn = 121,
210  PIT_IRQn = 122,
211  ACMP1_IRQn = 123,
212  ACMP2_IRQn = 124,
213  ACMP3_IRQn = 125,
214  ACMP4_IRQn = 126,
215  Reserved143_IRQn = 127,
216  Reserved144_IRQn = 128,
217  ENC1_IRQn = 129,
218  ENC2_IRQn = 130,
219  Reserved147_IRQn = 131,
220  Reserved148_IRQn = 132,
221  TMR1_IRQn = 133,
222  TMR2_IRQn = 134,
223  Reserved151_IRQn = 135,
224  Reserved152_IRQn = 136,
225  PWM2_0_IRQn = 137,
226  PWM2_1_IRQn = 138,
227  PWM2_2_IRQn = 139,
228  PWM2_3_IRQn = 140,
229  PWM2_FAULT_IRQn = 141
230 } IRQn_Type;
231  /* end of group Interrupt_vector_numbers */
235 
236 
237 /* ----------------------------------------------------------------------------
238  -- Cortex M7 Core Configuration
239  ---------------------------------------------------------------------------- */
240 
246 #define __MPU_PRESENT 1
247 #define __ICACHE_PRESENT 1
248 #define __DCACHE_PRESENT 1
249 #define __DTCM_PRESENT 1
250 #define __NVIC_PRIO_BITS 4
251 #define __Vendor_SysTickConfig 0
252 #define __FPU_PRESENT 1
254 #include "core_cm7.h" /* Core Peripheral Access Layer */
255 #include "system_MIMXRT1021.h" /* Device specific configuration file */
256  /* end of group Cortex_Core_Configuration */
260 
261 
262 /* ----------------------------------------------------------------------------
263  -- Mapping Information
264  ---------------------------------------------------------------------------- */
265 
277 /*******************************************************************************
278  * Definitions
279  ******************************************************************************/
280 
288 typedef enum _dma_request_source
289 {
290  kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U,
291  kDmaRequestMuxFlexIO1Request4Request5 = 1|0x100U,
292  kDmaRequestMuxLPUART1Tx = 2|0x100U,
293  kDmaRequestMuxLPUART1Rx = 3|0x100U,
294  kDmaRequestMuxLPUART3Tx = 4|0x100U,
295  kDmaRequestMuxLPUART3Rx = 5|0x100U,
296  kDmaRequestMuxLPUART5Tx = 6|0x100U,
297  kDmaRequestMuxLPUART5Rx = 7|0x100U,
298  kDmaRequestMuxLPUART7Tx = 8|0x100U,
299  kDmaRequestMuxLPUART7Rx = 9|0x100U,
300  kDmaRequestMuxLPSPI1Rx = 13|0x100U,
301  kDmaRequestMuxLPSPI1Tx = 14|0x100U,
302  kDmaRequestMuxLPSPI3Rx = 15|0x100U,
303  kDmaRequestMuxLPSPI3Tx = 16|0x100U,
304  kDmaRequestMuxLPI2C1 = 17|0x100U,
305  kDmaRequestMuxLPI2C3 = 18|0x100U,
306  kDmaRequestMuxSai1Rx = 19|0x100U,
307  kDmaRequestMuxSai1Tx = 20|0x100U,
308  kDmaRequestMuxSai2Rx = 21|0x100U,
309  kDmaRequestMuxSai2Tx = 22|0x100U,
310  kDmaRequestMuxADC_ETC = 23|0x100U,
311  kDmaRequestMuxADC1 = 24|0x100U,
312  kDmaRequestMuxACMP1 = 25|0x100U,
313  kDmaRequestMuxACMP3 = 26|0x100U,
314  kDmaRequestMuxFlexSPIRx = 28|0x100U,
315  kDmaRequestMuxFlexSPITx = 29|0x100U,
316  kDmaRequestMuxXBAR1Request0 = 30|0x100U,
317  kDmaRequestMuxXBAR1Request1 = 31|0x100U,
318  kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U,
319  kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U,
320  kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U,
321  kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U,
322  kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U,
323  kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U,
324  kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U,
325  kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U,
326  kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U,
327  kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,
328  kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U,
329  kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U,
330  kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U,
331  kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U,
332  kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U,
333  kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U,
334  kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U,
335  kDmaRequestMuxFlexIO1Request6Request7 = 65|0x100U,
336  kDmaRequestMuxLPUART2Tx = 66|0x100U,
337  kDmaRequestMuxLPUART2Rx = 67|0x100U,
338  kDmaRequestMuxLPUART4Tx = 68|0x100U,
339  kDmaRequestMuxLPUART4Rx = 69|0x100U,
340  kDmaRequestMuxLPUART6Tx = 70|0x100U,
341  kDmaRequestMuxLPUART6Rx = 71|0x100U,
342  kDmaRequestMuxLPUART8Tx = 72|0x100U,
343  kDmaRequestMuxLPUART8Rx = 73|0x100U,
344  kDmaRequestMuxLPSPI2Rx = 77|0x100U,
345  kDmaRequestMuxLPSPI2Tx = 78|0x100U,
346  kDmaRequestMuxLPSPI4Rx = 79|0x100U,
347  kDmaRequestMuxLPSPI4Tx = 80|0x100U,
348  kDmaRequestMuxLPI2C2 = 81|0x100U,
349  kDmaRequestMuxLPI2C4 = 82|0x100U,
350  kDmaRequestMuxSai3Rx = 83|0x100U,
351  kDmaRequestMuxSai3Tx = 84|0x100U,
352  kDmaRequestMuxSpdifRx = 85|0x100U,
353  kDmaRequestMuxSpdifTx = 86|0x100U,
354  kDmaRequestMuxADC2 = 88|0x100U,
355  kDmaRequestMuxACMP2 = 89|0x100U,
356  kDmaRequestMuxACMP4 = 90|0x100U,
357  kDmaRequestMuxEnetTimer0 = 92|0x100U,
358  kDmaRequestMuxEnetTimer1 = 93|0x100U,
359  kDmaRequestMuxXBAR1Request2 = 94|0x100U,
360  kDmaRequestMuxXBAR1Request3 = 95|0x100U,
361  kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U,
362  kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U,
363  kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U,
364  kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U,
365  kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U,
366  kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U,
367  kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U,
368  kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U,
369  kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U,
370  kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U,
371  kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,
372  kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U,
373  kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U,
374  kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U,
375  kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U,
376  kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U,
377 } dma_request_source_t;
378 
379 /* @} */
380 
385 /*******************************************************************************
386  * Definitions
387 *******************************************************************************/
388 
394 typedef enum _iomuxc_sw_mux_ctl_pad
395 {
396  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U,
397  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U,
398  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U,
399  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U,
400  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U,
401  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U,
402  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U,
403  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U,
404  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U,
405  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U,
406  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U,
407  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U,
408  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U,
409  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U,
410  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U,
411  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U,
412  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U,
413  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U,
414  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U,
415  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U,
416  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U,
417  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U,
418  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U,
419  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U,
420  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U,
421  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U,
422  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U,
423  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U,
424  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U,
425  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U,
426  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U,
427  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U,
428  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U,
429  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U,
430  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U,
431  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U,
432  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U,
433  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U,
434  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U,
435  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U,
436  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U,
437  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U,
438  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U,
439  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U,
440  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U,
441  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U,
442  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U,
443  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U,
444  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U,
445  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U,
446  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U,
447  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U,
448  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U,
449  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U,
450  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U,
451  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U,
452  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U,
453  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U,
454  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U,
455  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U,
456  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U,
457  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U,
458  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U,
459  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U,
460  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U,
461  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U,
462  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U,
463  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U,
464  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U,
465  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U,
466  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U,
467  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U,
468  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U,
469  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U,
470  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 74U,
471  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 75U,
472  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 76U,
473  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 77U,
474  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 78U,
475  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 79U,
476  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_06 = 80U,
477  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 81U,
478  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 82U,
479  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 83U,
480  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 84U,
481  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 85U,
482  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 86U,
483  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 87U,
484  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 88U,
485  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 89U,
486  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 90U,
487  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 91U,
488  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 92U,
489 } iomuxc_sw_mux_ctl_pad_t;
490 
491 /* @} */
492 
497 /*******************************************************************************
498  * Definitions
499 *******************************************************************************/
500 
506 typedef enum _iomuxc_sw_pad_ctl_pad
507 {
508  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U,
509  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U,
510  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U,
511  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U,
512  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U,
513  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U,
514  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U,
515  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U,
516  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U,
517  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U,
518  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U,
519  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U,
520  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U,
521  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U,
522  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U,
523  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U,
524  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U,
525  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U,
526  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U,
527  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U,
528  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U,
529  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U,
530  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U,
531  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U,
532  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U,
533  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U,
534  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U,
535  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U,
536  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U,
537  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U,
538  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U,
539  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U,
540  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U,
541  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U,
542  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U,
543  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U,
544  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U,
545  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U,
546  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U,
547  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U,
548  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U,
549  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U,
550  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U,
551  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U,
552  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U,
553  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U,
554  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U,
555  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U,
556  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U,
557  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U,
558  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U,
559  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U,
560  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U,
561  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U,
562  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U,
563  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U,
564  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U,
565  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U,
566  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U,
567  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U,
568  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U,
569  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U,
570  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U,
571  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U,
572  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U,
573  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U,
574  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U,
575  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U,
576  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U,
577  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U,
578  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U,
579  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U,
580  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U,
581  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U,
582  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 74U,
583  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 75U,
584  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 76U,
585  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 77U,
586  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 78U,
587  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 79U,
588  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_06 = 80U,
589  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 81U,
590  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 82U,
591  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 83U,
592  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 84U,
593  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 85U,
594  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 86U,
595  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 87U,
596  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 88U,
597  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 89U,
598  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 90U,
599  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 91U,
600  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 92U,
601 } iomuxc_sw_pad_ctl_pad_t;
602 
603 /* @} */
604 
610 typedef enum _iomuxc_select_input
611 {
612  kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U,
613  kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 1U,
614  kIOMUXC_ENET_RMII_SELECT_INPUT = 2U,
615  kIOMUXC_ENET_MDIO_SELECT_INPUT = 3U,
616  kIOMUXC_ENET_RX_DATA0_SELECT_INPUT = 4U,
617  kIOMUXC_ENET_RX_DATA1_SELECT_INPUT = 5U,
618  kIOMUXC_ENET_RX_EN_SELECT_INPUT = 6U,
619  kIOMUXC_ENET_RX_ERR_SELECT_INPUT = 7U,
620  kIOMUXC_ENET_TX_CLK_SELECT_INPUT = 8U,
621  kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 9U,
622  kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 10U,
623  kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 11U,
624  kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 12U,
625  kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 13U,
626  kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 14U,
627  kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 15U,
628  kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 16U,
629  kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 17U,
630  kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 18U,
631  kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 19U,
632  kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 20U,
633  kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 21U,
634  kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 22U,
635  kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 23U,
636  kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 24U,
637  kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 25U,
638  kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 26U,
639  kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT = 27U,
640  kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT = 28U,
641  kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT = 29U,
642  kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT = 30U,
643  kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT = 31U,
644  kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 32U,
645  kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 33U,
646  kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 34U,
647  kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 35U,
648  kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 36U,
649  kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 37U,
650  kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 38U,
651  kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 39U,
652  kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 40U,
653  kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 41U,
654  kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 42U,
655  kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 43U,
656  kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 44U,
657  kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 45U,
658  kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 46U,
659  kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 47U,
660  kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 48U,
661  kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 49U,
662  kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 50U,
663  kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 51U,
664  kIOMUXC_LPUART2_CTS_B_SELECT_INPUT = 52U,
665  kIOMUXC_LPUART2_RX_SELECT_INPUT = 53U,
666  kIOMUXC_LPUART2_TX_SELECT_INPUT = 54U,
667  kIOMUXC_LPUART3_RX_SELECT_INPUT = 55U,
668  kIOMUXC_LPUART3_TX_SELECT_INPUT = 56U,
669  kIOMUXC_LPUART4_CTS_B_SELECT_INPUT = 57U,
670  kIOMUXC_LPUART4_RX_SELECT_INPUT = 58U,
671  kIOMUXC_LPUART4_TX_SELECT_INPUT = 59U,
672  kIOMUXC_LPUART5_RX_SELECT_INPUT = 60U,
673  kIOMUXC_LPUART5_TX_SELECT_INPUT = 61U,
674  kIOMUXC_LPUART6_RX_SELECT_INPUT = 62U,
675  kIOMUXC_LPUART6_TX_SELECT_INPUT = 63U,
676  kIOMUXC_LPUART7_RX_SELECT_INPUT = 64U,
677  kIOMUXC_LPUART7_TX_SELECT_INPUT = 65U,
678  kIOMUXC_LPUART8_RX_SELECT_INPUT = 66U,
679  kIOMUXC_LPUART8_TX_SELECT_INPUT = 67U,
680  kIOMUXC_NMI_SELECT_INPUT = 68U,
681  kIOMUXC_QTIMER1_TIMER0_INPUT_SELECT_INPUT = 69U,
682  kIOMUXC_QTIMER1_TIMER1_INPUT_SELECT_INPUT = 70U,
683  kIOMUXC_QTIMER1_TIMER2_INPUT_SELECT_INPUT = 71U,
684  kIOMUXC_QTIMER1_TIMER3_INPUT_SELECT_INPUT = 72U,
685  kIOMUXC_QTIMER2_TIMER0_INPUT_SELECT_INPUT = 73U,
686  kIOMUXC_QTIMER2_TIMER1_INPUT_SELECT_INPUT = 74U,
687  kIOMUXC_QTIMER2_TIMER2_INPUT_SELECT_INPUT = 75U,
688  kIOMUXC_QTIMER2_TIMER3_INPUT_SELECT_INPUT = 76U,
689  kIOMUXC_SAI1_MCLK_SELECT_INPUT = 77U,
690  kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 78U,
691  kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 79U,
692  kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 80U,
693  kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 81U,
694  kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 82U,
695  kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 83U,
696  kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 84U,
697  kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 85U,
698  kIOMUXC_SAI2_MCLK_SELECT_INPUT = 86U,
699  kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 87U,
700  kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 88U,
701  kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 89U,
702  kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 90U,
703  kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 91U,
704  kIOMUXC_SAI3_MCLK_SELECT_INPUT = 92U,
705  kIOMUXC_SAI3_RX_BCLK_SELECT_INPUT = 93U,
706  kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT = 94U,
707  kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT = 95U,
708  kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT = 96U,
709  kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT = 97U,
710  kIOMUXC_SEMC_READY_SELECT_INPUT = 98U,
711  kIOMUXC_SPDIF_IN_SELECT_INPUT = 99U,
712  kIOMUXC_USB_OTG_OC_SELECT_INPUT = 100U,
713  kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 101U,
714  kIOMUXC_USDHC1_WP_SELECT_INPUT = 102U,
715  kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 103U,
716  kIOMUXC_USDHC2_WP_SELECT_INPUT = 104U,
717  kIOMUXC_XBAR1_IN14_SELECT_INPUT = 105U,
718  kIOMUXC_XBAR1_IN15_SELECT_INPUT = 106U,
719  kIOMUXC_XBAR1_IN16_SELECT_INPUT = 107U,
720  kIOMUXC_XBAR1_IN17_SELECT_INPUT = 108U,
721  kIOMUXC_XBAR1_IN10_SELECT_INPUT = 109U,
722  kIOMUXC_XBAR1_IN12_SELECT_INPUT = 110U,
723  kIOMUXC_XBAR1_IN13_SELECT_INPUT = 111U,
724  kIOMUXC_XBAR1_IN18_SELECT_INPUT = 112U,
725  kIOMUXC_XBAR1_IN19_SELECT_INPUT = 113U,
726 } iomuxc_select_input_t;
727 
728 typedef enum _xbar_input_signal
729 {
730  kXBARA1_InputLogicLow = 0|0x100U,
731  kXBARA1_InputLogicHigh = 1|0x100U,
732  kXBARA1_InputRESERVED2 = 2|0x100U,
733  kXBARA1_InputRESERVED3 = 3|0x100U,
734  kXBARA1_InputIomuxXbarInout04 = 4|0x100U,
735  kXBARA1_InputIomuxXbarInout05 = 5|0x100U,
736  kXBARA1_InputIomuxXbarInout06 = 6|0x100U,
737  kXBARA1_InputIomuxXbarInout07 = 7|0x100U,
738  kXBARA1_InputIomuxXbarInout08 = 8|0x100U,
739  kXBARA1_InputIomuxXbarInout09 = 9|0x100U,
740  kXBARA1_InputIomuxXbarInout10 = 10|0x100U,
741  kXBARA1_InputIomuxXbarInout11 = 11|0x100U,
742  kXBARA1_InputIomuxXbarInout12 = 12|0x100U,
743  kXBARA1_InputIomuxXbarInout13 = 13|0x100U,
744  kXBARA1_InputIomuxXbarInout14 = 14|0x100U,
745  kXBARA1_InputIomuxXbarInout15 = 15|0x100U,
746  kXBARA1_InputIomuxXbarInout16 = 16|0x100U,
747  kXBARA1_InputIomuxXbarInout17 = 17|0x100U,
748  kXBARA1_InputIomuxXbarInout18 = 18|0x100U,
749  kXBARA1_InputIomuxXbarInout19 = 19|0x100U,
750  kXBARA1_InputRESERVED20 = 20|0x100U,
751  kXBARA1_InputRESERVED21 = 21|0x100U,
752  kXBARA1_InputRESERVED22 = 22|0x100U,
753  kXBARA1_InputRESERVED23 = 23|0x100U,
754  kXBARA1_InputRESERVED24 = 24|0x100U,
755  kXBARA1_InputRESERVED25 = 25|0x100U,
756  kXBARA1_InputAcmp1Out = 26|0x100U,
757  kXBARA1_InputAcmp2Out = 27|0x100U,
758  kXBARA1_InputAcmp3Out = 28|0x100U,
759  kXBARA1_InputAcmp4Out = 29|0x100U,
760  kXBARA1_InputRESERVED30 = 30|0x100U,
761  kXBARA1_InputRESERVED31 = 31|0x100U,
762  kXBARA1_InputQtimer1Tmr0 = 32|0x100U,
763  kXBARA1_InputQtimer1Tmr1 = 33|0x100U,
764  kXBARA1_InputQtimer1Tmr2 = 34|0x100U,
765  kXBARA1_InputQtimer1Tmr3 = 35|0x100U,
766  kXBARA1_InputQtimer2Tmr0 = 36|0x100U,
767  kXBARA1_InputQtimer2Tmr1 = 37|0x100U,
768  kXBARA1_InputQtimer2Tmr2 = 38|0x100U,
769  kXBARA1_InputQtimer2Tmr3 = 39|0x100U,
770  kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U,
771  kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U,
772  kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U,
773  kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U,
774  kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U,
775  kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U,
776  kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U,
777  kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U,
778  kXBARA1_InputRESERVED48 = 48|0x100U,
779  kXBARA1_InputRESERVED49 = 49|0x100U,
780  kXBARA1_InputRESERVED50 = 50|0x100U,
781  kXBARA1_InputRESERVED51 = 51|0x100U,
782  kXBARA1_InputRESERVED52 = 52|0x100U,
783  kXBARA1_InputRESERVED53 = 53|0x100U,
784  kXBARA1_InputRESERVED54 = 54|0x100U,
785  kXBARA1_InputRESERVED55 = 55|0x100U,
786  kXBARA1_InputPitTrigger0 = 56|0x100U,
787  kXBARA1_InputPitTrigger1 = 57|0x100U,
788  kXBARA1_InputPitTrigger2 = 58|0x100U,
789  kXBARA1_InputPitTrigger3 = 59|0x100U,
790  kXBARA1_InputEnc1PosMatch = 60|0x100U,
791  kXBARA1_InputEnc2PosMatch = 61|0x100U,
792  kXBARA1_InputRESERVED62 = 62|0x100U,
793  kXBARA1_InputRESERVED63 = 63|0x100U,
794  kXBARA1_InputDmaDone0 = 64|0x100U,
795  kXBARA1_InputDmaDone1 = 65|0x100U,
796  kXBARA1_InputDmaDone2 = 66|0x100U,
797  kXBARA1_InputDmaDone3 = 67|0x100U,
798  kXBARA1_InputDmaDone4 = 68|0x100U,
799  kXBARA1_InputDmaDone5 = 69|0x100U,
800  kXBARA1_InputDmaDone6 = 70|0x100U,
801  kXBARA1_InputDmaDone7 = 71|0x100U,
802  kXBARA1_InputAoi1Out0 = 72|0x100U,
803  kXBARA1_InputAoi1Out1 = 73|0x100U,
804  kXBARA1_InputAoi1Out2 = 74|0x100U,
805  kXBARA1_InputAoi1Out3 = 75|0x100U,
806  kXBARA1_InputRESERVED76 = 76|0x100U,
807  kXBARA1_InputRESERVED77 = 77|0x100U,
808  kXBARA1_InputRESERVED78 = 78|0x100U,
809  kXBARA1_InputRESERVED79 = 79|0x100U,
810  kXBARA1_InputAdcEtc0Coco0 = 80|0x100U,
811  kXBARA1_InputAdcEtc0Coco1 = 81|0x100U,
812  kXBARA1_InputAdcEtc0Coco2 = 82|0x100U,
813  kXBARA1_InputAdcEtc0Coco3 = 83|0x100U,
814  kXBARA1_InputAdcEtc1Coco0 = 84|0x100U,
815  kXBARA1_InputAdcEtc1Coco1 = 85|0x100U,
816  kXBARA1_InputAdcEtc1Coco2 = 86|0x100U,
817  kXBARA1_InputAdcEtc1Coco3 = 87|0x100U,
818  kXBARB2_InputLogicLow = 0|0x200U,
819  kXBARB2_InputLogicHigh = 1|0x200U,
820  kXBARB2_InputRESERVED2 = 2|0x200U,
821  kXBARB2_InputRESERVED3 = 3|0x200U,
822  kXBARB2_InputRESERVED4 = 4|0x200U,
823  kXBARB2_InputRESERVED5 = 5|0x200U,
824  kXBARB2_InputAcmp1Out = 6|0x200U,
825  kXBARB2_InputAcmp2Out = 7|0x200U,
826  kXBARB2_InputAcmp3Out = 8|0x200U,
827  kXBARB2_InputAcmp4Out = 9|0x200U,
828  kXBARB2_InputRESERVED10 = 10|0x200U,
829  kXBARB2_InputRESERVED11 = 11|0x200U,
830  kXBARB2_InputQtimer1Tmr0 = 12|0x200U,
831  kXBARB2_InputQtimer1Tmr1 = 13|0x200U,
832  kXBARB2_InputQtimer1Tmr2 = 14|0x200U,
833  kXBARB2_InputQtimer1Tmr3 = 15|0x200U,
834  kXBARB2_InputQtimer2Tmr0 = 16|0x200U,
835  kXBARB2_InputQtimer2Tmr1 = 17|0x200U,
836  kXBARB2_InputQtimer2Tmr2 = 18|0x200U,
837  kXBARB2_InputQtimer2Tmr3 = 19|0x200U,
838  kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U,
839  kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U,
840  kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U,
841  kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U,
842  kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U,
843  kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U,
844  kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U,
845  kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U,
846  kXBARB2_InputRESERVED28 = 28|0x200U,
847  kXBARB2_InputRESERVED29 = 29|0x200U,
848  kXBARB2_InputRESERVED30 = 30|0x200U,
849  kXBARB2_InputRESERVED31 = 31|0x200U,
850  kXBARB2_InputRESERVED32 = 32|0x200U,
851  kXBARB2_InputRESERVED33 = 33|0x200U,
852  kXBARB2_InputRESERVED34 = 34|0x200U,
853  kXBARB2_InputRESERVED35 = 35|0x200U,
854  kXBARB2_InputPitTrigger0 = 36|0x200U,
855  kXBARB2_InputPitTrigger1 = 37|0x200U,
856  kXBARB2_InputAdcEtc0Coco0 = 38|0x200U,
857  kXBARB2_InputAdcEtc0Coco1 = 39|0x200U,
858  kXBARB2_InputAdcEtc0Coco2 = 40|0x200U,
859  kXBARB2_InputAdcEtc0Coco3 = 41|0x200U,
860  kXBARB2_InputAdcEtc1Coco0 = 42|0x200U,
861  kXBARB2_InputAdcEtc1Coco1 = 43|0x200U,
862  kXBARB2_InputAdcEtc1Coco2 = 44|0x200U,
863  kXBARB2_InputAdcEtc1Coco3 = 45|0x200U,
864  kXBARB2_InputEnc1PosMatch = 46|0x200U,
865  kXBARB2_InputEnc2PosMatch = 47|0x200U,
866  kXBARB2_InputRESERVED48 = 48|0x200U,
867  kXBARB2_InputRESERVED49 = 49|0x200U,
868  kXBARB2_InputDmaDone0 = 50|0x200U,
869  kXBARB2_InputDmaDone1 = 51|0x200U,
870  kXBARB2_InputDmaDone2 = 52|0x200U,
871  kXBARB2_InputDmaDone3 = 53|0x200U,
872  kXBARB2_InputDmaDone4 = 54|0x200U,
873  kXBARB2_InputDmaDone5 = 55|0x200U,
874  kXBARB2_InputDmaDone6 = 56|0x200U,
875  kXBARB2_InputDmaDone7 = 57|0x200U,
876 } xbar_input_signal_t;
877 
878 typedef enum _xbar_output_signal
879 {
880  kXBARA1_OutputDmaChMuxReq30 = 0|0x100U,
881  kXBARA1_OutputDmaChMuxReq31 = 1|0x100U,
882  kXBARA1_OutputDmaChMuxReq94 = 2|0x100U,
883  kXBARA1_OutputDmaChMuxReq95 = 3|0x100U,
884  kXBARA1_OutputIomuxXbarInout04 = 4|0x100U,
885  kXBARA1_OutputIomuxXbarInout05 = 5|0x100U,
886  kXBARA1_OutputIomuxXbarInout06 = 6|0x100U,
887  kXBARA1_OutputIomuxXbarInout07 = 7|0x100U,
888  kXBARA1_OutputIomuxXbarInout08 = 8|0x100U,
889  kXBARA1_OutputIomuxXbarInout09 = 9|0x100U,
890  kXBARA1_OutputIomuxXbarInout10 = 10|0x100U,
891  kXBARA1_OutputIomuxXbarInout11 = 11|0x100U,
892  kXBARA1_OutputIomuxXbarInout12 = 12|0x100U,
893  kXBARA1_OutputIomuxXbarInout13 = 13|0x100U,
894  kXBARA1_OutputIomuxXbarInout14 = 14|0x100U,
895  kXBARA1_OutputIomuxXbarInout15 = 15|0x100U,
896  kXBARA1_OutputIomuxXbarInout16 = 16|0x100U,
897  kXBARA1_OutputIomuxXbarInout17 = 17|0x100U,
898  kXBARA1_OutputIomuxXbarInout18 = 18|0x100U,
899  kXBARA1_OutputIomuxXbarInout19 = 19|0x100U,
900  kXBARA1_OutputAcmp1Sample = 20|0x100U,
901  kXBARA1_OutputAcmp2Sample = 21|0x100U,
902  kXBARA1_OutputAcmp3Sample = 22|0x100U,
903  kXBARA1_OutputAcmp4Sample = 23|0x100U,
904  kXBARA1_OutputRESERVED24 = 24|0x100U,
905  kXBARA1_OutputRESERVED25 = 25|0x100U,
906  kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U,
907  kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U,
908  kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U,
909  kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U,
910  kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U,
911  kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U,
912  kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U,
913  kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U,
914  kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U,
915  kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U,
916  kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U,
917  kXBARA1_OutputFlexpwm12Fault2 = 37|0x100U,
918  kXBARA1_OutputFlexpwm12Fault3 = 38|0x100U,
919  kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U,
920  kXBARA1_OutputFlexpwm2Exta0 = 40|0x100U,
921  kXBARA1_OutputFlexpwm2Exta1 = 41|0x100U,
922  kXBARA1_OutputFlexpwm2Exta2 = 42|0x100U,
923  kXBARA1_OutputFlexpwm2Exta3 = 43|0x100U,
924  kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U,
925  kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U,
926  kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U,
927  kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U,
928  kXBARA1_OutputFlexpwm2ExtClk = 48|0x100U,
929  kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U,
930  kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U,
931  kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U,
932  kXBARA1_OutputRESERVED52 = 52|0x100U,
933  kXBARA1_OutputRESERVED53 = 53|0x100U,
934  kXBARA1_OutputRESERVED54 = 54|0x100U,
935  kXBARA1_OutputRESERVED55 = 55|0x100U,
936  kXBARA1_OutputRESERVED56 = 56|0x100U,
937  kXBARA1_OutputRESERVED57 = 57|0x100U,
938  kXBARA1_OutputRESERVED58 = 58|0x100U,
939  kXBARA1_OutputRESERVED59 = 59|0x100U,
940  kXBARA1_OutputRESERVED60 = 60|0x100U,
941  kXBARA1_OutputRESERVED61 = 61|0x100U,
942  kXBARA1_OutputRESERVED62 = 62|0x100U,
943  kXBARA1_OutputRESERVED63 = 63|0x100U,
944  kXBARA1_OutputRESERVED64 = 64|0x100U,
945  kXBARA1_OutputRESERVED65 = 65|0x100U,
946  kXBARA1_OutputEnc1PhaseAInput = 66|0x100U,
947  kXBARA1_OutputEnc1PhaseBInput = 67|0x100U,
948  kXBARA1_OutputEnc1Index = 68|0x100U,
949  kXBARA1_OutputEnc1Home = 69|0x100U,
950  kXBARA1_OutputEnc1Trigger = 70|0x100U,
951  kXBARA1_OutputEnc2PhaseAInput = 71|0x100U,
952  kXBARA1_OutputEnc2PhaseBInput = 72|0x100U,
953  kXBARA1_OutputEnc2Index = 73|0x100U,
954  kXBARA1_OutputEnc2Home = 74|0x100U,
955  kXBARA1_OutputEnc2Trigger = 75|0x100U,
956  kXBARA1_OutputRESERVED76 = 76|0x100U,
957  kXBARA1_OutputRESERVED77 = 77|0x100U,
958  kXBARA1_OutputRESERVED78 = 78|0x100U,
959  kXBARA1_OutputRESERVED79 = 79|0x100U,
960  kXBARA1_OutputRESERVED80 = 80|0x100U,
961  kXBARA1_OutputRESERVED81 = 81|0x100U,
962  kXBARA1_OutputRESERVED82 = 82|0x100U,
963  kXBARA1_OutputRESERVED83 = 83|0x100U,
964  kXBARA1_OutputRESERVED84 = 84|0x100U,
965  kXBARA1_OutputRESERVED85 = 85|0x100U,
966  kXBARA1_OutputQtimer1Tmr0 = 86|0x100U,
967  kXBARA1_OutputQtimer1Tmr1 = 87|0x100U,
968  kXBARA1_OutputQtimer1Tmr2 = 88|0x100U,
969  kXBARA1_OutputQtimer1Tmr3 = 89|0x100U,
970  kXBARA1_OutputQtimer2Tmr0 = 90|0x100U,
971  kXBARA1_OutputQtimer2Tmr1 = 91|0x100U,
972  kXBARA1_OutputQtimer2Tmr2 = 92|0x100U,
973  kXBARA1_OutputQtimer2Tmr3 = 93|0x100U,
974  kXBARA1_OutputRESERVED94 = 94|0x100U,
975  kXBARA1_OutputRESERVED95 = 95|0x100U,
976  kXBARA1_OutputRESERVED96 = 96|0x100U,
977  kXBARA1_OutputRESERVED97 = 97|0x100U,
978  kXBARA1_OutputRESERVED98 = 98|0x100U,
979  kXBARA1_OutputRESERVED99 = 99|0x100U,
980  kXBARA1_OutputRESERVED100 = 100|0x100U,
981  kXBARA1_OutputRESERVED101 = 101|0x100U,
982  kXBARA1_OutputEwmEwmIn = 102|0x100U,
983  kXBARA1_OutputAdcEtcTrig00 = 103|0x100U,
984  kXBARA1_OutputAdcEtcTrig01 = 104|0x100U,
985  kXBARA1_OutputAdcEtcTrig02 = 105|0x100U,
986  kXBARA1_OutputAdcEtcTrig03 = 106|0x100U,
987  kXBARA1_OutputAdcEtcTrig10 = 107|0x100U,
988  kXBARA1_OutputAdcEtcTrig11 = 108|0x100U,
989  kXBARA1_OutputAdcEtcTrig12 = 109|0x100U,
990  kXBARA1_OutputAdcEtcTrig13 = 110|0x100U,
991  kXBARA1_OutputLpi2c1TrgInput = 111|0x100U,
992  kXBARA1_OutputLpi2c2TrgInput = 112|0x100U,
993  kXBARA1_OutputLpi2c3TrgInput = 113|0x100U,
994  kXBARA1_OutputLpi2c4TrgInput = 114|0x100U,
995  kXBARA1_OutputLpspi1TrgInput = 115|0x100U,
996  kXBARA1_OutputLpspi2TrgInput = 116|0x100U,
997  kXBARA1_OutputLpspi3TrgInput = 117|0x100U,
998  kXBARA1_OutputLpspi4TrgInput = 118|0x100U,
999  kXBARA1_OutputLpuart1TrgInput = 119|0x100U,
1000  kXBARA1_OutputLpuart2TrgInput = 120|0x100U,
1001  kXBARA1_OutputLpuart3TrgInput = 121|0x100U,
1002  kXBARA1_OutputLpuart4TrgInput = 122|0x100U,
1003  kXBARA1_OutputLpuart5TrgInput = 123|0x100U,
1004  kXBARA1_OutputLpuart6TrgInput = 124|0x100U,
1005  kXBARA1_OutputLpuart7TrgInput = 125|0x100U,
1006  kXBARA1_OutputLpuart8TrgInput = 126|0x100U,
1007  kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U,
1008  kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U,
1009  kXBARA1_OutputRESERVED129 = 129|0x100U,
1010  kXBARA1_OutputRESERVED130 = 130|0x100U,
1011  kXBARA1_OutputRESERVED131 = 131|0x100U,
1012  kXBARB2_OutputAoi1In00 = 0|0x200U,
1013  kXBARB2_OutputAoi1In01 = 1|0x200U,
1014  kXBARB2_OutputAoi1In02 = 2|0x200U,
1015  kXBARB2_OutputAoi1In03 = 3|0x200U,
1016  kXBARB2_OutputAoi1In04 = 4|0x200U,
1017  kXBARB2_OutputAoi1In05 = 5|0x200U,
1018  kXBARB2_OutputAoi1In06 = 6|0x200U,
1019  kXBARB2_OutputAoi1In07 = 7|0x200U,
1020  kXBARB2_OutputAoi1In08 = 8|0x200U,
1021  kXBARB2_OutputAoi1In09 = 9|0x200U,
1022  kXBARB2_OutputAoi1In10 = 10|0x200U,
1023  kXBARB2_OutputAoi1In11 = 11|0x200U,
1024  kXBARB2_OutputAoi1In12 = 12|0x200U,
1025  kXBARB2_OutputAoi1In13 = 13|0x200U,
1026  kXBARB2_OutputAoi1In14 = 14|0x200U,
1027  kXBARB2_OutputAoi1In15 = 15|0x200U,
1028 } xbar_output_signal_t;
1029 
1030  /* end of group Mapping_Information */
1034 
1035 
1036 /* ----------------------------------------------------------------------------
1037  -- Device Peripheral Access Layer
1038  ---------------------------------------------------------------------------- */
1039 
1046 /*
1047 ** Start of section using anonymous unions
1048 */
1049 
1050 #if defined(__ARMCC_VERSION)
1051  #if (__ARMCC_VERSION >= 6010050)
1052  #pragma clang diagnostic push
1053  #else
1054  #pragma push
1055  #pragma anon_unions
1056  #endif
1057 #elif defined(__CWCC__)
1058  #pragma push
1059  #pragma cpp_extensions on
1060 #elif defined(__GNUC__)
1061  /* anonymous unions are enabled by default */
1062 #elif defined(__IAR_SYSTEMS_ICC__)
1063  #pragma language=extended
1064 #else
1065  #error Not supported compiler type
1066 #endif
1067 
1068 /* ----------------------------------------------------------------------------
1069  -- ADC Peripheral Access Layer
1070  ---------------------------------------------------------------------------- */
1071 
1078 typedef struct {
1079  __IO uint32_t HC[8];
1080  __I uint32_t HS;
1081  __I uint32_t R[8];
1082  __IO uint32_t CFG;
1083  __IO uint32_t GC;
1084  __IO uint32_t GS;
1085  __IO uint32_t CV;
1086  __IO uint32_t OFS;
1087  __IO uint32_t CAL;
1088 } ADC_Type;
1089 
1090 /* ----------------------------------------------------------------------------
1091  -- ADC Register Masks
1092  ---------------------------------------------------------------------------- */
1093 
1101 #define ADC_HC_ADCH_MASK (0x1FU)
1102 #define ADC_HC_ADCH_SHIFT (0U)
1111 #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1112 #define ADC_HC_AIEN_MASK (0x80U)
1113 #define ADC_HC_AIEN_SHIFT (7U)
1118 #define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1121 /* The count of ADC_HC */
1122 #define ADC_HC_COUNT (8U)
1123 
1126 #define ADC_HS_COCO0_MASK (0x1U)
1127 #define ADC_HS_COCO0_SHIFT (0U)
1130 #define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1131 #define ADC_HS_COCO1_MASK (0x2U)
1132 #define ADC_HS_COCO1_SHIFT (1U)
1135 #define ADC_HS_COCO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO1_SHIFT)) & ADC_HS_COCO1_MASK)
1136 #define ADC_HS_COCO2_MASK (0x4U)
1137 #define ADC_HS_COCO2_SHIFT (2U)
1138 #define ADC_HS_COCO2(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO2_SHIFT)) & ADC_HS_COCO2_MASK)
1139 #define ADC_HS_COCO3_MASK (0x8U)
1140 #define ADC_HS_COCO3_SHIFT (3U)
1141 #define ADC_HS_COCO3(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO3_SHIFT)) & ADC_HS_COCO3_MASK)
1142 #define ADC_HS_COCO4_MASK (0x10U)
1143 #define ADC_HS_COCO4_SHIFT (4U)
1144 #define ADC_HS_COCO4(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO4_SHIFT)) & ADC_HS_COCO4_MASK)
1145 #define ADC_HS_COCO5_MASK (0x20U)
1146 #define ADC_HS_COCO5_SHIFT (5U)
1147 #define ADC_HS_COCO5(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO5_SHIFT)) & ADC_HS_COCO5_MASK)
1148 #define ADC_HS_COCO6_MASK (0x40U)
1149 #define ADC_HS_COCO6_SHIFT (6U)
1150 #define ADC_HS_COCO6(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO6_SHIFT)) & ADC_HS_COCO6_MASK)
1151 #define ADC_HS_COCO7_MASK (0x80U)
1152 #define ADC_HS_COCO7_SHIFT (7U)
1153 #define ADC_HS_COCO7(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO7_SHIFT)) & ADC_HS_COCO7_MASK)
1158 #define ADC_R_CDATA_MASK (0xFFFU)
1159 #define ADC_R_CDATA_SHIFT (0U)
1162 #define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1165 /* The count of ADC_R */
1166 #define ADC_R_COUNT (8U)
1167 
1170 #define ADC_CFG_ADICLK_MASK (0x3U)
1171 #define ADC_CFG_ADICLK_SHIFT (0U)
1178 #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1179 #define ADC_CFG_MODE_MASK (0xCU)
1180 #define ADC_CFG_MODE_SHIFT (2U)
1187 #define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1188 #define ADC_CFG_ADLSMP_MASK (0x10U)
1189 #define ADC_CFG_ADLSMP_SHIFT (4U)
1194 #define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1195 #define ADC_CFG_ADIV_MASK (0x60U)
1196 #define ADC_CFG_ADIV_SHIFT (5U)
1203 #define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1204 #define ADC_CFG_ADLPC_MASK (0x80U)
1205 #define ADC_CFG_ADLPC_SHIFT (7U)
1210 #define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1211 #define ADC_CFG_ADSTS_MASK (0x300U)
1212 #define ADC_CFG_ADSTS_SHIFT (8U)
1219 #define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1220 #define ADC_CFG_ADHSC_MASK (0x400U)
1221 #define ADC_CFG_ADHSC_SHIFT (10U)
1226 #define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1227 #define ADC_CFG_REFSEL_MASK (0x1800U)
1228 #define ADC_CFG_REFSEL_SHIFT (11U)
1235 #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1236 #define ADC_CFG_ADTRG_MASK (0x2000U)
1237 #define ADC_CFG_ADTRG_SHIFT (13U)
1242 #define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1243 #define ADC_CFG_AVGS_MASK (0xC000U)
1244 #define ADC_CFG_AVGS_SHIFT (14U)
1251 #define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1252 #define ADC_CFG_OVWREN_MASK (0x10000U)
1253 #define ADC_CFG_OVWREN_SHIFT (16U)
1258 #define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1263 #define ADC_GC_ADACKEN_MASK (0x1U)
1264 #define ADC_GC_ADACKEN_SHIFT (0U)
1269 #define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1270 #define ADC_GC_DMAEN_MASK (0x2U)
1271 #define ADC_GC_DMAEN_SHIFT (1U)
1276 #define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1277 #define ADC_GC_ACREN_MASK (0x4U)
1278 #define ADC_GC_ACREN_SHIFT (2U)
1283 #define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1284 #define ADC_GC_ACFGT_MASK (0x8U)
1285 #define ADC_GC_ACFGT_SHIFT (3U)
1292 #define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1293 #define ADC_GC_ACFE_MASK (0x10U)
1294 #define ADC_GC_ACFE_SHIFT (4U)
1299 #define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1300 #define ADC_GC_AVGE_MASK (0x20U)
1301 #define ADC_GC_AVGE_SHIFT (5U)
1306 #define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1307 #define ADC_GC_ADCO_MASK (0x40U)
1308 #define ADC_GC_ADCO_SHIFT (6U)
1313 #define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1314 #define ADC_GC_CAL_MASK (0x80U)
1315 #define ADC_GC_CAL_SHIFT (7U)
1318 #define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1323 #define ADC_GS_ADACT_MASK (0x1U)
1324 #define ADC_GS_ADACT_SHIFT (0U)
1329 #define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1330 #define ADC_GS_CALF_MASK (0x2U)
1331 #define ADC_GS_CALF_SHIFT (1U)
1336 #define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1337 #define ADC_GS_AWKST_MASK (0x4U)
1338 #define ADC_GS_AWKST_SHIFT (2U)
1343 #define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1348 #define ADC_CV_CV1_MASK (0xFFFU)
1349 #define ADC_CV_CV1_SHIFT (0U)
1352 #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1353 #define ADC_CV_CV2_MASK (0xFFF0000U)
1354 #define ADC_CV_CV2_SHIFT (16U)
1357 #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1362 #define ADC_OFS_OFS_MASK (0xFFFU)
1363 #define ADC_OFS_OFS_SHIFT (0U)
1366 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1367 #define ADC_OFS_SIGN_MASK (0x1000U)
1368 #define ADC_OFS_SIGN_SHIFT (12U)
1373 #define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1378 #define ADC_CAL_CAL_CODE_MASK (0xFU)
1379 #define ADC_CAL_CAL_CODE_SHIFT (0U)
1382 #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) /* end of group ADC_Register_Masks */
1389 
1390 
1391 /* ADC - Peripheral instance base addresses */
1393 #define ADC1_BASE (0x400C4000u)
1395 #define ADC1 ((ADC_Type *)ADC1_BASE)
1397 #define ADC2_BASE (0x400C8000u)
1399 #define ADC2 ((ADC_Type *)ADC2_BASE)
1401 #define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
1403 #define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
1405 #define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1406  /* end of group ADC_Peripheral_Access_Layer */
1410 
1411 
1412 /* ----------------------------------------------------------------------------
1413  -- ADC_ETC Peripheral Access Layer
1414  ---------------------------------------------------------------------------- */
1415 
1422 typedef struct {
1423  __IO uint32_t CTRL;
1424  __IO uint32_t DONE0_1_IRQ;
1425  __IO uint32_t DONE2_ERR_IRQ;
1426  __IO uint32_t DMA_CTRL;
1427  struct { /* offset: 0x10, array step: 0x28 */
1428  __IO uint32_t TRIGn_CTRL;
1429  __IO uint32_t TRIGn_COUNTER;
1430  __IO uint32_t TRIGn_CHAIN_1_0;
1431  __IO uint32_t TRIGn_CHAIN_3_2;
1432  __IO uint32_t TRIGn_CHAIN_5_4;
1433  __IO uint32_t TRIGn_CHAIN_7_6;
1434  __I uint32_t TRIGn_RESULT_1_0;
1435  __I uint32_t TRIGn_RESULT_3_2;
1436  __I uint32_t TRIGn_RESULT_5_4;
1437  __I uint32_t TRIGn_RESULT_7_6;
1438  } TRIG[8];
1439 } ADC_ETC_Type;
1440 
1441 /* ----------------------------------------------------------------------------
1442  -- ADC_ETC Register Masks
1443  ---------------------------------------------------------------------------- */
1444 
1452 #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1453 #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1454 #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1455 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1456 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1457 #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1458 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1459 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1460 #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1461 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1462 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1463 #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1464 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1465 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1466 #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1467 #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1468 #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1469 #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1470 #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1471 #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1472 #define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1473 #define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1474 #define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1475 #define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1476 #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1477 #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1478 #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1483 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1484 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1485 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1486 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1487 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1488 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1489 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1490 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1491 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1492 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1493 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1494 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1495 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1496 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1497 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1498 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1499 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1500 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1501 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1502 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1503 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1504 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1505 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1506 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1507 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1508 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1509 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1510 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1511 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1512 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1513 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1514 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1515 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1516 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1517 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1518 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1519 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1520 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1521 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1522 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1523 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1524 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1525 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1526 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1527 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1528 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1529 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1530 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1535 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1536 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1537 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
1538 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1539 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1540 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1541 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1542 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1543 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1544 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1545 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1546 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1547 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1548 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1549 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1550 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1551 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1552 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1553 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1554 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1555 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1556 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1557 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1558 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1559 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1560 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1561 #define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1562 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1563 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1564 #define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1565 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1566 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1567 #define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1568 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1569 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1570 #define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1571 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1572 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1573 #define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1574 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1575 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1576 #define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1577 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1578 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1579 #define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1580 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1581 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1582 #define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1587 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1588 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1589 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1590 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1591 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1592 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1593 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1594 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1595 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1596 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1597 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1598 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1599 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1600 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1601 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1602 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1603 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1604 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1605 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1606 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1607 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1608 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1609 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1610 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1611 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1612 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1613 #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1614 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1615 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1616 #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1617 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1618 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1619 #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1620 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1621 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1622 #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1623 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1624 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1625 #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1626 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1627 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1628 #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1629 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1630 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1631 #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1632 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1633 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1634 #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1639 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1640 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1641 #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1642 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1643 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1644 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1645 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1646 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1647 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1648 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1649 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1650 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1651 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1652 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1653 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1656 /* The count of ADC_ETC_TRIGn_CTRL */
1657 #define ADC_ETC_TRIGn_CTRL_COUNT (8U)
1658 
1661 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1662 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1663 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1664 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1665 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1666 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1669 /* The count of ADC_ETC_TRIGn_COUNTER */
1670 #define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
1671 
1674 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
1675 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
1676 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
1677 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
1678 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
1679 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
1680 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
1681 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
1682 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
1683 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
1684 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
1685 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
1686 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
1687 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
1688 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
1689 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
1690 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
1691 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
1692 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
1693 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
1694 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
1695 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
1696 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
1697 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
1700 /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
1701 #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
1702 
1705 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
1706 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
1707 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
1708 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
1709 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
1710 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
1711 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
1712 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
1713 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
1714 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
1715 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
1716 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
1717 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
1718 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
1719 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
1720 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
1721 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
1722 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
1723 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
1724 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
1725 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
1726 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
1727 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
1728 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
1731 /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
1732 #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
1733 
1736 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
1737 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
1738 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
1739 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
1740 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
1741 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
1742 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
1743 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
1744 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
1745 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
1746 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
1747 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
1748 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
1749 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
1750 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
1751 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
1752 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
1753 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
1754 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
1755 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
1756 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
1757 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
1758 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
1759 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
1762 /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
1763 #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
1764 
1767 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
1768 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
1769 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
1770 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
1771 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
1772 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
1773 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
1774 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
1775 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
1776 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
1777 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
1778 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
1779 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
1780 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
1781 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
1782 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
1783 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
1784 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
1785 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
1786 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
1787 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
1788 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
1789 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
1790 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
1793 /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
1794 #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
1795 
1798 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
1799 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
1800 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
1801 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
1802 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
1803 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
1806 /* The count of ADC_ETC_TRIGn_RESULT_1_0 */
1807 #define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
1808 
1811 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
1812 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
1813 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
1814 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
1815 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
1816 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
1819 /* The count of ADC_ETC_TRIGn_RESULT_3_2 */
1820 #define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
1821 
1824 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
1825 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
1826 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
1827 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
1828 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
1829 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
1832 /* The count of ADC_ETC_TRIGn_RESULT_5_4 */
1833 #define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
1834 
1837 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
1838 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
1839 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
1840 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
1841 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
1842 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
1845 /* The count of ADC_ETC_TRIGn_RESULT_7_6 */
1846 #define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
1847 
1848  /* end of group ADC_ETC_Register_Masks */
1852 
1853 
1854 /* ADC_ETC - Peripheral instance base addresses */
1856 #define ADC_ETC_BASE (0x403B0000u)
1858 #define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
1860 #define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
1862 #define ADC_ETC_BASE_PTRS { ADC_ETC }
1864 #define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
1865 #define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
1866  /* end of group ADC_ETC_Peripheral_Access_Layer */
1870 
1871 
1872 /* ----------------------------------------------------------------------------
1873  -- AIPSTZ Peripheral Access Layer
1874  ---------------------------------------------------------------------------- */
1875 
1882 typedef struct {
1883  __IO uint32_t MPR;
1884  uint8_t RESERVED_0[60];
1885  __IO uint32_t OPACR;
1886  __IO uint32_t OPACR1;
1887  __IO uint32_t OPACR2;
1888  __IO uint32_t OPACR3;
1889  __IO uint32_t OPACR4;
1890 } AIPSTZ_Type;
1891 
1892 /* ----------------------------------------------------------------------------
1893  -- AIPSTZ Register Masks
1894  ---------------------------------------------------------------------------- */
1895 
1903 #define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
1904 #define AIPSTZ_MPR_MPROT3_SHIFT (16U)
1914 #define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
1915 #define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
1916 #define AIPSTZ_MPR_MPROT2_SHIFT (20U)
1926 #define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
1927 #define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
1928 #define AIPSTZ_MPR_MPROT1_SHIFT (24U)
1938 #define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
1939 #define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
1940 #define AIPSTZ_MPR_MPROT0_SHIFT (28U)
1950 #define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
1955 #define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
1956 #define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
1971 #define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
1972 #define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
1973 #define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
1988 #define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
1989 #define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
1990 #define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
2005 #define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2006 #define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
2007 #define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
2022 #define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2023 #define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
2024 #define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
2039 #define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2040 #define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
2041 #define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
2056 #define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2057 #define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
2058 #define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
2073 #define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
2074 #define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
2075 #define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
2090 #define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
2095 #define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
2096 #define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
2111 #define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
2112 #define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
2113 #define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
2128 #define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
2129 #define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
2130 #define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
2145 #define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
2146 #define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
2147 #define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
2162 #define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
2163 #define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
2164 #define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
2179 #define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
2180 #define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
2181 #define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
2196 #define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
2197 #define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
2198 #define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
2213 #define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
2214 #define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
2215 #define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
2230 #define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
2235 #define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
2236 #define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
2251 #define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
2252 #define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
2253 #define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
2268 #define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
2269 #define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
2270 #define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
2285 #define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
2286 #define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
2287 #define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
2302 #define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
2303 #define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
2304 #define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
2319 #define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
2320 #define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
2321 #define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
2336 #define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
2337 #define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
2338 #define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
2353 #define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
2354 #define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
2355 #define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
2370 #define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
2375 #define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
2376 #define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
2391 #define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
2392 #define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
2393 #define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
2408 #define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
2409 #define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
2410 #define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
2425 #define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
2426 #define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
2427 #define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
2442 #define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
2443 #define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
2444 #define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
2459 #define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
2460 #define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
2461 #define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
2476 #define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2477 #define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2478 #define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2493 #define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2494 #define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2495 #define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2510 #define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2515 #define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2516 #define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2531 #define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2532 #define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2533 #define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2548 #define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) /* end of group AIPSTZ_Register_Masks */
2555 
2556 
2557 /* AIPSTZ - Peripheral instance base addresses */
2559 #define AIPSTZ1_BASE (0x4007C000u)
2561 #define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2563 #define AIPSTZ2_BASE (0x4017C000u)
2565 #define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2567 #define AIPSTZ3_BASE (0x4027C000u)
2569 #define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
2571 #define AIPSTZ4_BASE (0x4037C000u)
2573 #define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
2575 #define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
2577 #define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
2578  /* end of group AIPSTZ_Peripheral_Access_Layer */
2582 
2583 
2584 /* ----------------------------------------------------------------------------
2585  -- AOI Peripheral Access Layer
2586  ---------------------------------------------------------------------------- */
2587 
2594 typedef struct {
2595  struct { /* offset: 0x0, array step: 0x4 */
2596  __IO uint16_t BFCRT01;
2597  __IO uint16_t BFCRT23;
2598  } BFCRT[4];
2599 } AOI_Type;
2600 
2601 /* ----------------------------------------------------------------------------
2602  -- AOI Register Masks
2603  ---------------------------------------------------------------------------- */
2604 
2612 #define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2613 #define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2620 #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2621 #define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2622 #define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2629 #define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2630 #define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2631 #define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2638 #define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2639 #define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2640 #define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2647 #define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2648 #define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2649 #define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2656 #define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2657 #define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2658 #define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2665 #define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
2666 #define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
2667 #define AOI_BFCRT01_PT0_BC_SHIFT (12U)
2674 #define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
2675 #define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
2676 #define AOI_BFCRT01_PT0_AC_SHIFT (14U)
2683 #define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
2686 /* The count of AOI_BFCRT01 */
2687 #define AOI_BFCRT01_COUNT (4U)
2688 
2691 #define AOI_BFCRT23_PT3_DC_MASK (0x3U)
2692 #define AOI_BFCRT23_PT3_DC_SHIFT (0U)
2699 #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
2700 #define AOI_BFCRT23_PT3_CC_MASK (0xCU)
2701 #define AOI_BFCRT23_PT3_CC_SHIFT (2U)
2708 #define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
2709 #define AOI_BFCRT23_PT3_BC_MASK (0x30U)
2710 #define AOI_BFCRT23_PT3_BC_SHIFT (4U)
2717 #define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
2718 #define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
2719 #define AOI_BFCRT23_PT3_AC_SHIFT (6U)
2726 #define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
2727 #define AOI_BFCRT23_PT2_DC_MASK (0x300U)
2728 #define AOI_BFCRT23_PT2_DC_SHIFT (8U)
2735 #define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
2736 #define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
2737 #define AOI_BFCRT23_PT2_CC_SHIFT (10U)
2744 #define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
2745 #define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
2746 #define AOI_BFCRT23_PT2_BC_SHIFT (12U)
2753 #define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
2754 #define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
2755 #define AOI_BFCRT23_PT2_AC_SHIFT (14U)
2762 #define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
2765 /* The count of AOI_BFCRT23 */
2766 #define AOI_BFCRT23_COUNT (4U)
2767 
2768  /* end of group AOI_Register_Masks */
2772 
2773 
2774 /* AOI - Peripheral instance base addresses */
2776 #define AOI_BASE (0x403B4000u)
2778 #define AOI ((AOI_Type *)AOI_BASE)
2780 #define AOI_BASE_ADDRS { AOI_BASE }
2782 #define AOI_BASE_PTRS { AOI }
2783  /* end of group AOI_Peripheral_Access_Layer */
2787 
2788 
2789 /* ----------------------------------------------------------------------------
2790  -- BEE Peripheral Access Layer
2791  ---------------------------------------------------------------------------- */
2792 
2799 typedef struct {
2800  __IO uint32_t CTRL;
2801  __IO uint32_t ADDR_OFFSET0;
2802  __IO uint32_t ADDR_OFFSET1;
2803  __O uint32_t AES_KEY0_W0;
2804  __O uint32_t AES_KEY0_W1;
2805  __O uint32_t AES_KEY0_W2;
2806  __O uint32_t AES_KEY0_W3;
2807  __IO uint32_t STATUS;
2808  __O uint32_t CTR_NONCE0_W0;
2809  __O uint32_t CTR_NONCE0_W1;
2810  __O uint32_t CTR_NONCE0_W2;
2811  __O uint32_t CTR_NONCE0_W3;
2812  __O uint32_t CTR_NONCE1_W0;
2813  __O uint32_t CTR_NONCE1_W1;
2814  __O uint32_t CTR_NONCE1_W2;
2815  __O uint32_t CTR_NONCE1_W3;
2816  __IO uint32_t REGION1_TOP;
2817  __IO uint32_t REGION1_BOT;
2818 } BEE_Type;
2819 
2820 /* ----------------------------------------------------------------------------
2821  -- BEE Register Masks
2822  ---------------------------------------------------------------------------- */
2823 
2831 #define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
2832 #define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
2837 #define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
2838 #define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
2839 #define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
2840 #define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
2841 #define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
2842 #define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
2843 #define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
2844 #define BEE_CTRL_KEY_VALID_MASK (0x10U)
2845 #define BEE_CTRL_KEY_VALID_SHIFT (4U)
2846 #define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
2847 #define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
2848 #define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
2853 #define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
2854 #define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
2855 #define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
2856 #define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
2857 #define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
2858 #define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
2865 #define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
2866 #define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
2867 #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
2868 #define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
2869 #define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
2870 #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
2875 #define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
2876 #define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
2877 #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
2878 #define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
2879 #define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
2880 #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
2885 #define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
2886 #define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
2887 #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
2888 #define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
2889 #define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
2890 #define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
2891 #define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
2892 #define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
2893 #define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
2894 #define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
2895 #define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
2896 #define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
2897 #define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
2898 #define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
2899 #define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
2900 #define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
2901 #define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
2902 #define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
2903 #define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
2904 #define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
2905 #define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
2906 #define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
2907 #define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
2908 #define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
2909 #define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
2910 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
2911 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
2912 #define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
2913 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
2914 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
2915 #define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
2916 #define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
2917 #define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
2918 #define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
2919 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
2920 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
2921 #define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
2922 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
2923 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
2924 #define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
2925 #define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
2926 #define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
2927 #define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
2932 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
2933 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
2934 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
2935 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
2936 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
2937 #define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
2942 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
2943 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
2944 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
2945 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
2946 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
2947 #define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
2952 #define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
2953 #define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
2956 #define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
2961 #define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
2962 #define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
2965 #define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
2970 #define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
2971 #define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
2974 #define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
2979 #define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
2980 #define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
2983 #define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
2988 #define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
2989 #define BEE_STATUS_IRQ_VEC_SHIFT (0U)
2990 #define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
2991 #define BEE_STATUS_BEE_IDLE_MASK (0x100U)
2992 #define BEE_STATUS_BEE_IDLE_SHIFT (8U)
2993 #define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
2998 #define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
2999 #define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
3000 #define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
3005 #define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
3006 #define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
3007 #define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
3012 #define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
3013 #define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
3014 #define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
3019 #define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
3020 #define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
3021 #define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
3026 #define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
3027 #define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
3028 #define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
3033 #define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
3034 #define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
3035 #define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
3040 #define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
3041 #define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
3042 #define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
3047 #define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
3048 #define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
3049 #define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
3054 #define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
3055 #define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
3058 #define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
3063 #define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
3064 #define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
3067 #define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) /* end of group BEE_Register_Masks */
3074 
3075 
3076 /* BEE - Peripheral instance base addresses */
3078 #define BEE_BASE (0x403EC000u)
3080 #define BEE ((BEE_Type *)BEE_BASE)
3082 #define BEE_BASE_ADDRS { BEE_BASE }
3084 #define BEE_BASE_PTRS { BEE }
3085  /* end of group BEE_Peripheral_Access_Layer */
3089 
3090 
3091 /* ----------------------------------------------------------------------------
3092  -- CAN Peripheral Access Layer
3093  ---------------------------------------------------------------------------- */
3094 
3101 typedef struct {
3102  __IO uint32_t MCR;
3103  __IO uint32_t CTRL1;
3104  __IO uint32_t TIMER;
3105  uint8_t RESERVED_0[4];
3106  __IO uint32_t RXMGMASK;
3107  __IO uint32_t RX14MASK;
3108  __IO uint32_t RX15MASK;
3109  __IO uint32_t ECR;
3110  __IO uint32_t ESR1;
3111  __IO uint32_t IMASK2;
3112  __IO uint32_t IMASK1;
3113  __IO uint32_t IFLAG2;
3114  __IO uint32_t IFLAG1;
3115  __IO uint32_t CTRL2;
3116  __I uint32_t ESR2;
3117  uint8_t RESERVED_1[8];
3118  __I uint32_t CRCR;
3119  __IO uint32_t RXFGMASK;
3120  __I uint32_t RXFIR;
3121  uint8_t RESERVED_2[8];
3122  __I uint32_t DBG1;
3123  __I uint32_t DBG2;
3124  uint8_t RESERVED_3[32];
3125  struct { /* offset: 0x80, array step: 0x10 */
3126  __IO uint32_t CS;
3127  __IO uint32_t ID;
3128  __IO uint32_t WORD0;
3129  __IO uint32_t WORD1;
3130  } MB[64];
3131  uint8_t RESERVED_4[1024];
3132  __IO uint32_t RXIMR[64];
3133  uint8_t RESERVED_5[96];
3134  __IO uint32_t GFWR;
3135 } CAN_Type;
3136 
3137 /* ----------------------------------------------------------------------------
3138  -- CAN Register Masks
3139  ---------------------------------------------------------------------------- */
3140 
3148 #define CAN_MCR_MAXMB_MASK (0x7FU)
3149 #define CAN_MCR_MAXMB_SHIFT (0U)
3150 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
3151 #define CAN_MCR_IDAM_MASK (0x300U)
3152 #define CAN_MCR_IDAM_SHIFT (8U)
3159 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
3160 #define CAN_MCR_AEN_MASK (0x1000U)
3161 #define CAN_MCR_AEN_SHIFT (12U)
3166 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
3167 #define CAN_MCR_LPRIOEN_MASK (0x2000U)
3168 #define CAN_MCR_LPRIOEN_SHIFT (13U)
3173 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
3174 #define CAN_MCR_IRMQ_MASK (0x10000U)
3175 #define CAN_MCR_IRMQ_SHIFT (16U)
3180 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
3181 #define CAN_MCR_SRXDIS_MASK (0x20000U)
3182 #define CAN_MCR_SRXDIS_SHIFT (17U)
3187 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
3188 #define CAN_MCR_WAKSRC_MASK (0x80000U)
3189 #define CAN_MCR_WAKSRC_SHIFT (19U)
3194 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
3195 #define CAN_MCR_LPMACK_MASK (0x100000U)
3196 #define CAN_MCR_LPMACK_SHIFT (20U)
3201 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
3202 #define CAN_MCR_WRNEN_MASK (0x200000U)
3203 #define CAN_MCR_WRNEN_SHIFT (21U)
3208 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
3209 #define CAN_MCR_SLFWAK_MASK (0x400000U)
3210 #define CAN_MCR_SLFWAK_SHIFT (22U)
3215 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
3216 #define CAN_MCR_SUPV_MASK (0x800000U)
3217 #define CAN_MCR_SUPV_SHIFT (23U)
3223 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
3224 #define CAN_MCR_FRZACK_MASK (0x1000000U)
3225 #define CAN_MCR_FRZACK_SHIFT (24U)
3230 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
3231 #define CAN_MCR_SOFTRST_MASK (0x2000000U)
3232 #define CAN_MCR_SOFTRST_SHIFT (25U)
3237 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
3238 #define CAN_MCR_WAKMSK_MASK (0x4000000U)
3239 #define CAN_MCR_WAKMSK_SHIFT (26U)
3244 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
3245 #define CAN_MCR_NOTRDY_MASK (0x8000000U)
3246 #define CAN_MCR_NOTRDY_SHIFT (27U)
3251 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
3252 #define CAN_MCR_HALT_MASK (0x10000000U)
3253 #define CAN_MCR_HALT_SHIFT (28U)
3258 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
3259 #define CAN_MCR_RFEN_MASK (0x20000000U)
3260 #define CAN_MCR_RFEN_SHIFT (29U)
3265 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
3266 #define CAN_MCR_FRZ_MASK (0x40000000U)
3267 #define CAN_MCR_FRZ_SHIFT (30U)
3272 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
3273 #define CAN_MCR_MDIS_MASK (0x80000000U)
3274 #define CAN_MCR_MDIS_SHIFT (31U)
3279 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
3284 #define CAN_CTRL1_PROPSEG_MASK (0x7U)
3285 #define CAN_CTRL1_PROPSEG_SHIFT (0U)
3286 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
3287 #define CAN_CTRL1_LOM_MASK (0x8U)
3288 #define CAN_CTRL1_LOM_SHIFT (3U)
3293 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
3294 #define CAN_CTRL1_LBUF_MASK (0x10U)
3295 #define CAN_CTRL1_LBUF_SHIFT (4U)
3300 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
3301 #define CAN_CTRL1_TSYN_MASK (0x20U)
3302 #define CAN_CTRL1_TSYN_SHIFT (5U)
3307 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
3308 #define CAN_CTRL1_BOFFREC_MASK (0x40U)
3309 #define CAN_CTRL1_BOFFREC_SHIFT (6U)
3314 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
3315 #define CAN_CTRL1_SMP_MASK (0x80U)
3316 #define CAN_CTRL1_SMP_SHIFT (7U)
3322 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
3323 #define CAN_CTRL1_RWRNMSK_MASK (0x400U)
3324 #define CAN_CTRL1_RWRNMSK_SHIFT (10U)
3329 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
3330 #define CAN_CTRL1_TWRNMSK_MASK (0x800U)
3331 #define CAN_CTRL1_TWRNMSK_SHIFT (11U)
3336 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
3337 #define CAN_CTRL1_LPB_MASK (0x1000U)
3338 #define CAN_CTRL1_LPB_SHIFT (12U)
3343 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
3344 #define CAN_CTRL1_ERRMSK_MASK (0x4000U)
3345 #define CAN_CTRL1_ERRMSK_SHIFT (14U)
3350 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
3351 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
3352 #define CAN_CTRL1_BOFFMSK_SHIFT (15U)
3357 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
3358 #define CAN_CTRL1_PSEG2_MASK (0x70000U)
3359 #define CAN_CTRL1_PSEG2_SHIFT (16U)
3360 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
3361 #define CAN_CTRL1_PSEG1_MASK (0x380000U)
3362 #define CAN_CTRL1_PSEG1_SHIFT (19U)
3363 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
3364 #define CAN_CTRL1_RJW_MASK (0xC00000U)
3365 #define CAN_CTRL1_RJW_SHIFT (22U)
3366 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
3367 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
3368 #define CAN_CTRL1_PRESDIV_SHIFT (24U)
3369 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
3374 #define CAN_TIMER_TIMER_MASK (0xFFFFU)
3375 #define CAN_TIMER_TIMER_SHIFT (0U)
3376 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
3381 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
3382 #define CAN_RXMGMASK_MG_SHIFT (0U)
3387 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
3392 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
3393 #define CAN_RX14MASK_RX14M_SHIFT (0U)
3398 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
3403 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
3404 #define CAN_RX15MASK_RX15M_SHIFT (0U)
3409 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
3414 #define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
3415 #define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
3416 #define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
3417 #define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
3418 #define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
3419 #define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
3424 #define CAN_ESR1_WAKINT_MASK (0x1U)
3425 #define CAN_ESR1_WAKINT_SHIFT (0U)
3430 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
3431 #define CAN_ESR1_ERRINT_MASK (0x2U)
3432 #define CAN_ESR1_ERRINT_SHIFT (1U)
3437 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
3438 #define CAN_ESR1_BOFFINT_MASK (0x4U)
3439 #define CAN_ESR1_BOFFINT_SHIFT (2U)
3444 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
3445 #define CAN_ESR1_RX_MASK (0x8U)
3446 #define CAN_ESR1_RX_SHIFT (3U)
3451 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
3452 #define CAN_ESR1_FLTCONF_MASK (0x30U)
3453 #define CAN_ESR1_FLTCONF_SHIFT (4U)
3459 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
3460 #define CAN_ESR1_TX_MASK (0x40U)
3461 #define CAN_ESR1_TX_SHIFT (6U)
3466 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
3467 #define CAN_ESR1_IDLE_MASK (0x80U)
3468 #define CAN_ESR1_IDLE_SHIFT (7U)
3473 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
3474 #define CAN_ESR1_RXWRN_MASK (0x100U)
3475 #define CAN_ESR1_RXWRN_SHIFT (8U)
3480 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
3481 #define CAN_ESR1_TXWRN_MASK (0x200U)
3482 #define CAN_ESR1_TXWRN_SHIFT (9U)
3487 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
3488 #define CAN_ESR1_STFERR_MASK (0x400U)
3489 #define CAN_ESR1_STFERR_SHIFT (10U)
3494 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
3495 #define CAN_ESR1_FRMERR_MASK (0x800U)
3496 #define CAN_ESR1_FRMERR_SHIFT (11U)
3501 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
3502 #define CAN_ESR1_CRCERR_MASK (0x1000U)
3503 #define CAN_ESR1_CRCERR_SHIFT (12U)
3508 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
3509 #define CAN_ESR1_ACKERR_MASK (0x2000U)
3510 #define CAN_ESR1_ACKERR_SHIFT (13U)
3515 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
3516 #define CAN_ESR1_BIT0ERR_MASK (0x4000U)
3517 #define CAN_ESR1_BIT0ERR_SHIFT (14U)
3522 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
3523 #define CAN_ESR1_BIT1ERR_MASK (0x8000U)
3524 #define CAN_ESR1_BIT1ERR_SHIFT (15U)
3529 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
3530 #define CAN_ESR1_RWRNINT_MASK (0x10000U)
3531 #define CAN_ESR1_RWRNINT_SHIFT (16U)
3536 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
3537 #define CAN_ESR1_TWRNINT_MASK (0x20000U)
3538 #define CAN_ESR1_TWRNINT_SHIFT (17U)
3543 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
3544 #define CAN_ESR1_SYNCH_MASK (0x40000U)
3545 #define CAN_ESR1_SYNCH_SHIFT (18U)
3550 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
3555 #define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
3556 #define CAN_IMASK2_BUFHM_SHIFT (0U)
3561 #define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
3566 #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
3567 #define CAN_IMASK1_BUFLM_SHIFT (0U)
3572 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
3577 #define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
3578 #define CAN_IFLAG2_BUFHI_SHIFT (0U)
3583 #define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
3588 #define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
3589 #define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
3594 #define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
3595 #define CAN_IFLAG1_BUF5I_MASK (0x20U)
3596 #define CAN_IFLAG1_BUF5I_SHIFT (5U)
3601 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
3602 #define CAN_IFLAG1_BUF6I_MASK (0x40U)
3603 #define CAN_IFLAG1_BUF6I_SHIFT (6U)
3608 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
3609 #define CAN_IFLAG1_BUF7I_MASK (0x80U)
3610 #define CAN_IFLAG1_BUF7I_SHIFT (7U)
3615 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
3616 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
3617 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
3622 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
3627 #define CAN_CTRL2_EACEN_MASK (0x10000U)
3628 #define CAN_CTRL2_EACEN_SHIFT (16U)
3634 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
3635 #define CAN_CTRL2_RRS_MASK (0x20000U)
3636 #define CAN_CTRL2_RRS_SHIFT (17U)
3641 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
3642 #define CAN_CTRL2_MRP_MASK (0x40000U)
3643 #define CAN_CTRL2_MRP_SHIFT (18U)
3648 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
3649 #define CAN_CTRL2_TASD_MASK (0xF80000U)
3650 #define CAN_CTRL2_TASD_SHIFT (19U)
3651 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
3652 #define CAN_CTRL2_RFFN_MASK (0xF000000U)
3653 #define CAN_CTRL2_RFFN_SHIFT (24U)
3654 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
3655 #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
3656 #define CAN_CTRL2_WRMFRZ_SHIFT (28U)
3661 #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
3666 #define CAN_ESR2_IMB_MASK (0x2000U)
3667 #define CAN_ESR2_IMB_SHIFT (13U)
3672 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
3673 #define CAN_ESR2_VPS_MASK (0x4000U)
3674 #define CAN_ESR2_VPS_SHIFT (14U)
3679 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
3680 #define CAN_ESR2_LPTM_MASK (0x7F0000U)
3681 #define CAN_ESR2_LPTM_SHIFT (16U)
3682 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
3687 #define CAN_CRCR_TXCRC_MASK (0x7FFFU)
3688 #define CAN_CRCR_TXCRC_SHIFT (0U)
3689 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
3690 #define CAN_CRCR_MBCRC_MASK (0x7F0000U)
3691 #define CAN_CRCR_MBCRC_SHIFT (16U)
3692 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
3697 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
3698 #define CAN_RXFGMASK_FGM_SHIFT (0U)
3703 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
3708 #define CAN_RXFIR_IDHIT_MASK (0x1FFU)
3709 #define CAN_RXFIR_IDHIT_SHIFT (0U)
3710 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
3715 #define CAN_DBG1_CFSM_MASK (0x3FU)
3716 #define CAN_DBG1_CFSM_SHIFT (0U)
3719 #define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
3720 #define CAN_DBG1_CBN_MASK (0x1F000000U)
3721 #define CAN_DBG1_CBN_SHIFT (24U)
3724 #define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
3729 #define CAN_DBG2_RMP_MASK (0x7FU)
3730 #define CAN_DBG2_RMP_SHIFT (0U)
3733 #define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
3734 #define CAN_DBG2_MPP_MASK (0x80U)
3735 #define CAN_DBG2_MPP_SHIFT (7U)
3740 #define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
3741 #define CAN_DBG2_TAP_MASK (0x7F00U)
3742 #define CAN_DBG2_TAP_SHIFT (8U)
3745 #define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
3746 #define CAN_DBG2_APP_MASK (0x8000U)
3747 #define CAN_DBG2_APP_SHIFT (15U)
3752 #define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
3757 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
3758 #define CAN_CS_TIME_STAMP_SHIFT (0U)
3763 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
3764 #define CAN_CS_DLC_MASK (0xF0000U)
3765 #define CAN_CS_DLC_SHIFT (16U)
3768 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
3769 #define CAN_CS_RTR_MASK (0x100000U)
3770 #define CAN_CS_RTR_SHIFT (20U)
3773 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
3774 #define CAN_CS_IDE_MASK (0x200000U)
3775 #define CAN_CS_IDE_SHIFT (21U)
3778 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
3779 #define CAN_CS_SRR_MASK (0x400000U)
3780 #define CAN_CS_SRR_SHIFT (22U)
3783 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
3784 #define CAN_CS_CODE_MASK (0xF000000U)
3785 #define CAN_CS_CODE_SHIFT (24U)
3788 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
3791 /* The count of CAN_CS */
3792 #define CAN_CS_COUNT (64U)
3793 
3796 #define CAN_ID_EXT_MASK (0x3FFFFU)
3797 #define CAN_ID_EXT_SHIFT (0U)
3800 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
3801 #define CAN_ID_STD_MASK (0x1FFC0000U)
3802 #define CAN_ID_STD_SHIFT (18U)
3805 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
3806 #define CAN_ID_PRIO_MASK (0xE0000000U)
3807 #define CAN_ID_PRIO_SHIFT (29U)
3812 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
3815 /* The count of CAN_ID */
3816 #define CAN_ID_COUNT (64U)
3817 
3820 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
3821 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
3824 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
3825 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
3826 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
3829 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
3830 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
3831 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
3834 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
3835 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
3836 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
3839 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
3842 /* The count of CAN_WORD0 */
3843 #define CAN_WORD0_COUNT (64U)
3844 
3847 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
3848 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
3851 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
3852 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
3853 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
3856 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
3857 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
3858 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
3861 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
3862 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
3863 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
3866 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
3869 /* The count of CAN_WORD1 */
3870 #define CAN_WORD1_COUNT (64U)
3871 
3874 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
3875 #define CAN_RXIMR_MI_SHIFT (0U)
3880 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
3883 /* The count of CAN_RXIMR */
3884 #define CAN_RXIMR_COUNT (64U)
3885 
3888 #define CAN_GFWR_GFWR_MASK (0xFFU)
3889 #define CAN_GFWR_GFWR_SHIFT (0U)
3890 #define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) /* end of group CAN_Register_Masks */
3897 
3898 
3899 /* CAN - Peripheral instance base addresses */
3901 #define CAN1_BASE (0x401D0000u)
3903 #define CAN1 ((CAN_Type *)CAN1_BASE)
3905 #define CAN2_BASE (0x401D4000u)
3907 #define CAN2 ((CAN_Type *)CAN2_BASE)
3909 #define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }
3911 #define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }
3913 #define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3914 #define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3915 #define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3916 #define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3917 #define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3918 #define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3919 /* Backward compatibility */
3920 #define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK
3921 #define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT
3922 #define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)
3923 #define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK
3924 #define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT
3925 #define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)
3926 
3927  /* end of group CAN_Peripheral_Access_Layer */
3931 
3932 
3933 /* ----------------------------------------------------------------------------
3934  -- CCM Peripheral Access Layer
3935  ---------------------------------------------------------------------------- */
3936 
3943 typedef struct {
3944  __IO uint32_t CCR;
3945  uint8_t RESERVED_0[4];
3946  __I uint32_t CSR;
3947  __IO uint32_t CCSR;
3948  __IO uint32_t CACRR;
3949  __IO uint32_t CBCDR;
3950  __IO uint32_t CBCMR;
3951  __IO uint32_t CSCMR1;
3952  __IO uint32_t CSCMR2;
3953  __IO uint32_t CSCDR1;
3954  __IO uint32_t CS1CDR;
3955  __IO uint32_t CS2CDR;
3956  __IO uint32_t CDCDR;
3957  uint8_t RESERVED_1[4];
3958  __IO uint32_t CSCDR2;
3959  uint32_t CSCDR3;
3960  uint8_t RESERVED_2[8];
3961  __I uint32_t CDHIPR;
3962  uint8_t RESERVED_3[8];
3963  __IO uint32_t CLPCR;
3964  __IO uint32_t CISR;
3965  __IO uint32_t CIMR;
3966  __IO uint32_t CCOSR;
3967  __IO uint32_t CGPR;
3968  __IO uint32_t CCGR0;
3969  __IO uint32_t CCGR1;
3970  __IO uint32_t CCGR2;
3971  __IO uint32_t CCGR3;
3972  __IO uint32_t CCGR4;
3973  __IO uint32_t CCGR5;
3974  __IO uint32_t CCGR6;
3975  uint8_t RESERVED_4[4];
3976  __IO uint32_t CMEOR;
3977 } CCM_Type;
3978 
3979 /* ----------------------------------------------------------------------------
3980  -- CCM Register Masks
3981  ---------------------------------------------------------------------------- */
3982 
3990 #define CCM_CCR_OSCNT_MASK (0xFFU)
3991 #define CCM_CCR_OSCNT_SHIFT (0U)
3998 #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
3999 #define CCM_CCR_COSC_EN_MASK (0x1000U)
4000 #define CCM_CCR_COSC_EN_SHIFT (12U)
4005 #define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
4006 #define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
4007 #define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
4013 #define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
4014 #define CCM_CCR_RBC_EN_MASK (0x8000000U)
4015 #define CCM_CCR_RBC_EN_SHIFT (27U)
4020 #define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
4025 #define CCM_CSR_REF_EN_B_MASK (0x1U)
4026 #define CCM_CSR_REF_EN_B_SHIFT (0U)
4031 #define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
4032 #define CCM_CSR_CAMP2_READY_MASK (0x8U)
4033 #define CCM_CSR_CAMP2_READY_SHIFT (3U)
4038 #define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
4039 #define CCM_CSR_COSC_READY_MASK (0x20U)
4040 #define CCM_CSR_COSC_READY_SHIFT (5U)
4045 #define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
4050 #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
4051 #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
4056 #define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
4061 #define CCM_CACRR_ARM_PODF_MASK (0x7U)
4062 #define CCM_CACRR_ARM_PODF_SHIFT (0U)
4073 #define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
4078 #define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
4079 #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
4084 #define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
4085 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
4086 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
4091 #define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
4092 #define CCM_CBCDR_IPG_PODF_MASK (0x300U)
4093 #define CCM_CBCDR_IPG_PODF_SHIFT (8U)
4100 #define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
4101 #define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
4102 #define CCM_CBCDR_AHB_PODF_SHIFT (10U)
4113 #define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
4114 #define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
4115 #define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
4126 #define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
4127 #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
4128 #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
4133 #define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
4134 #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
4135 #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
4146 #define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
4151 #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
4152 #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
4159 #define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
4160 #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
4161 #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
4168 #define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
4169 #define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
4170 #define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
4177 #define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
4178 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
4179 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
4186 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
4187 #define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
4188 #define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
4199 #define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
4204 #define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
4205 #define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
4272 #define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
4273 #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
4274 #define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
4279 #define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
4280 #define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
4281 #define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
4288 #define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
4289 #define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
4290 #define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
4297 #define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
4298 #define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
4299 #define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
4306 #define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
4307 #define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
4308 #define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
4313 #define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
4314 #define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
4315 #define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
4320 #define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
4321 #define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
4322 #define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
4333 #define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
4334 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
4335 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
4342 #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
4347 #define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
4348 #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
4415 #define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
4416 #define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
4417 #define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
4423 #define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
4424 #define CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U)
4425 #define CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U)
4432 #define CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK)
4437 #define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
4438 #define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
4505 #define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
4506 #define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
4507 #define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
4512 #define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
4513 #define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
4514 #define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
4525 #define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
4526 #define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
4527 #define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
4538 #define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
4539 #define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
4540 #define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
4547 #define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
4552 #define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
4553 #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
4621 #define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
4622 #define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
4623 #define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
4634 #define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
4635 #define CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U)
4636 #define CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U)
4647 #define CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK)
4648 #define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
4649 #define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
4717 #define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
4718 #define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
4719 #define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
4730 #define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
4731 #define CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0xE000000U)
4732 #define CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U)
4743 #define CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK)
4748 #define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
4749 #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
4817 #define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
4818 #define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
4819 #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
4830 #define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
4835 #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
4836 #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
4843 #define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
4844 #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
4845 #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
4856 #define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
4857 #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
4858 #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
4869 #define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
4874 #define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
4875 #define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
4880 #define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
4881 #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
4882 #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
4951 #define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
4956 #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
4957 #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
4963 #define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
4964 #define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
4965 #define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
4971 #define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
4972 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
4973 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
4979 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
4980 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
4981 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
4987 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
4988 #define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
4989 #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
4995 #define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
5000 #define CCM_CLPCR_LPM_MASK (0x3U)
5001 #define CCM_CLPCR_LPM_SHIFT (0U)
5008 #define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
5009 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
5010 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
5015 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
5016 #define CCM_CLPCR_SBYOS_MASK (0x40U)
5017 #define CCM_CLPCR_SBYOS_SHIFT (6U)
5026 #define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
5027 #define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
5028 #define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
5033 #define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
5034 #define CCM_CLPCR_VSTBY_MASK (0x100U)
5035 #define CCM_CLPCR_VSTBY_SHIFT (8U)
5040 #define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
5041 #define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
5042 #define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
5049 #define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
5050 #define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
5051 #define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
5056 #define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
5057 #define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
5058 #define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
5059 #define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
5060 #define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
5061 #define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
5062 #define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
5063 #define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
5064 #define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
5069 #define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
5070 #define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
5071 #define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
5076 #define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
5077 #define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
5078 #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
5083 #define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
5088 #define CCM_CISR_LRF_PLL_MASK (0x1U)
5089 #define CCM_CISR_LRF_PLL_SHIFT (0U)
5094 #define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
5095 #define CCM_CISR_COSC_READY_MASK (0x40U)
5096 #define CCM_CISR_COSC_READY_SHIFT (6U)
5101 #define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
5102 #define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
5103 #define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
5108 #define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
5109 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
5110 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
5115 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
5116 #define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
5117 #define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
5122 #define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
5123 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
5124 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
5129 #define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
5130 #define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
5131 #define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
5136 #define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
5141 #define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
5142 #define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
5147 #define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
5148 #define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
5149 #define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
5154 #define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
5155 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
5156 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
5161 #define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
5162 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
5163 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
5168 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
5169 #define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
5170 #define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
5175 #define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
5176 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
5177 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
5182 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
5183 #define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
5184 #define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
5189 #define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
5194 #define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
5195 #define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
5210 #define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
5211 #define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
5212 #define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
5223 #define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
5224 #define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
5225 #define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
5230 #define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
5231 #define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
5232 #define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
5237 #define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
5238 #define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
5239 #define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
5257 #define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
5258 #define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
5259 #define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
5270 #define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
5271 #define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
5272 #define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
5277 #define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
5282 #define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
5283 #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
5288 #define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
5289 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
5290 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
5295 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
5296 #define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
5297 #define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
5303 #define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
5304 #define CCM_CGPR_FPL_MASK (0x10000U)
5305 #define CCM_CGPR_FPL_SHIFT (16U)
5310 #define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
5311 #define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
5312 #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
5318 #define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
5323 #define CCM_CCGR0_CG0_MASK (0x3U)
5324 #define CCM_CCGR0_CG0_SHIFT (0U)
5325 #define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
5326 #define CCM_CCGR0_CG1_MASK (0xCU)
5327 #define CCM_CCGR0_CG1_SHIFT (2U)
5328 #define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
5329 #define CCM_CCGR0_CG2_MASK (0x30U)
5330 #define CCM_CCGR0_CG2_SHIFT (4U)
5331 #define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
5332 #define CCM_CCGR0_CG3_MASK (0xC0U)
5333 #define CCM_CCGR0_CG3_SHIFT (6U)
5334 #define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
5335 #define CCM_CCGR0_CG4_MASK (0x300U)
5336 #define CCM_CCGR0_CG4_SHIFT (8U)
5337 #define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
5338 #define CCM_CCGR0_CG5_MASK (0xC00U)
5339 #define CCM_CCGR0_CG5_SHIFT (10U)
5340 #define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
5341 #define CCM_CCGR0_CG6_MASK (0x3000U)
5342 #define CCM_CCGR0_CG6_SHIFT (12U)
5343 #define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
5344 #define CCM_CCGR0_CG7_MASK (0xC000U)
5345 #define CCM_CCGR0_CG7_SHIFT (14U)
5346 #define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
5347 #define CCM_CCGR0_CG8_MASK (0x30000U)
5348 #define CCM_CCGR0_CG8_SHIFT (16U)
5349 #define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
5350 #define CCM_CCGR0_CG9_MASK (0xC0000U)
5351 #define CCM_CCGR0_CG9_SHIFT (18U)
5352 #define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
5353 #define CCM_CCGR0_CG10_MASK (0x300000U)
5354 #define CCM_CCGR0_CG10_SHIFT (20U)
5355 #define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
5356 #define CCM_CCGR0_CG11_MASK (0xC00000U)
5357 #define CCM_CCGR0_CG11_SHIFT (22U)
5358 #define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
5359 #define CCM_CCGR0_CG12_MASK (0x3000000U)
5360 #define CCM_CCGR0_CG12_SHIFT (24U)
5361 #define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
5362 #define CCM_CCGR0_CG13_MASK (0xC000000U)
5363 #define CCM_CCGR0_CG13_SHIFT (26U)
5364 #define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
5365 #define CCM_CCGR0_CG14_MASK (0x30000000U)
5366 #define CCM_CCGR0_CG14_SHIFT (28U)
5367 #define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
5368 #define CCM_CCGR0_CG15_MASK (0xC0000000U)
5369 #define CCM_CCGR0_CG15_SHIFT (30U)
5370 #define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
5375 #define CCM_CCGR1_CG0_MASK (0x3U)
5376 #define CCM_CCGR1_CG0_SHIFT (0U)
5377 #define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
5378 #define CCM_CCGR1_CG1_MASK (0xCU)
5379 #define CCM_CCGR1_CG1_SHIFT (2U)
5380 #define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
5381 #define CCM_CCGR1_CG2_MASK (0x30U)
5382 #define CCM_CCGR1_CG2_SHIFT (4U)
5383 #define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
5384 #define CCM_CCGR1_CG3_MASK (0xC0U)
5385 #define CCM_CCGR1_CG3_SHIFT (6U)
5386 #define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
5387 #define CCM_CCGR1_CG4_MASK (0x300U)
5388 #define CCM_CCGR1_CG4_SHIFT (8U)
5389 #define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
5390 #define CCM_CCGR1_CG5_MASK (0xC00U)
5391 #define CCM_CCGR1_CG5_SHIFT (10U)
5392 #define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
5393 #define CCM_CCGR1_CG6_MASK (0x3000U)
5394 #define CCM_CCGR1_CG6_SHIFT (12U)
5395 #define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
5396 #define CCM_CCGR1_CG7_MASK (0xC000U)
5397 #define CCM_CCGR1_CG7_SHIFT (14U)
5398 #define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
5399 #define CCM_CCGR1_CG8_MASK (0x30000U)
5400 #define CCM_CCGR1_CG8_SHIFT (16U)
5401 #define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
5402 #define CCM_CCGR1_CG9_MASK (0xC0000U)
5403 #define CCM_CCGR1_CG9_SHIFT (18U)
5404 #define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
5405 #define CCM_CCGR1_CG10_MASK (0x300000U)
5406 #define CCM_CCGR1_CG10_SHIFT (20U)
5407 #define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
5408 #define CCM_CCGR1_CG11_MASK (0xC00000U)
5409 #define CCM_CCGR1_CG11_SHIFT (22U)
5410 #define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
5411 #define CCM_CCGR1_CG12_MASK (0x3000000U)
5412 #define CCM_CCGR1_CG12_SHIFT (24U)
5413 #define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
5414 #define CCM_CCGR1_CG13_MASK (0xC000000U)
5415 #define CCM_CCGR1_CG13_SHIFT (26U)
5416 #define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
5417 #define CCM_CCGR1_CG14_MASK (0x30000000U)
5418 #define CCM_CCGR1_CG14_SHIFT (28U)
5419 #define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
5420 #define CCM_CCGR1_CG15_MASK (0xC0000000U)
5421 #define CCM_CCGR1_CG15_SHIFT (30U)
5422 #define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
5427 #define CCM_CCGR2_CG0_MASK (0x3U)
5428 #define CCM_CCGR2_CG0_SHIFT (0U)
5429 #define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
5430 #define CCM_CCGR2_CG1_MASK (0xCU)
5431 #define CCM_CCGR2_CG1_SHIFT (2U)
5432 #define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
5433 #define CCM_CCGR2_CG2_MASK (0x30U)
5434 #define CCM_CCGR2_CG2_SHIFT (4U)
5435 #define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
5436 #define CCM_CCGR2_CG3_MASK (0xC0U)
5437 #define CCM_CCGR2_CG3_SHIFT (6U)
5438 #define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
5439 #define CCM_CCGR2_CG4_MASK (0x300U)
5440 #define CCM_CCGR2_CG4_SHIFT (8U)
5441 #define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
5442 #define CCM_CCGR2_CG5_MASK (0xC00U)
5443 #define CCM_CCGR2_CG5_SHIFT (10U)
5444 #define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
5445 #define CCM_CCGR2_CG6_MASK (0x3000U)
5446 #define CCM_CCGR2_CG6_SHIFT (12U)
5447 #define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
5448 #define CCM_CCGR2_CG7_MASK (0xC000U)
5449 #define CCM_CCGR2_CG7_SHIFT (14U)
5450 #define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
5451 #define CCM_CCGR2_CG8_MASK (0x30000U)
5452 #define CCM_CCGR2_CG8_SHIFT (16U)
5453 #define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
5454 #define CCM_CCGR2_CG9_MASK (0xC0000U)
5455 #define CCM_CCGR2_CG9_SHIFT (18U)
5456 #define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
5457 #define CCM_CCGR2_CG10_MASK (0x300000U)
5458 #define CCM_CCGR2_CG10_SHIFT (20U)
5459 #define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
5460 #define CCM_CCGR2_CG11_MASK (0xC00000U)
5461 #define CCM_CCGR2_CG11_SHIFT (22U)
5462 #define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
5463 #define CCM_CCGR2_CG12_MASK (0x3000000U)
5464 #define CCM_CCGR2_CG12_SHIFT (24U)
5465 #define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
5466 #define CCM_CCGR2_CG13_MASK (0xC000000U)
5467 #define CCM_CCGR2_CG13_SHIFT (26U)
5468 #define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
5469 #define CCM_CCGR2_CG14_MASK (0x30000000U)
5470 #define CCM_CCGR2_CG14_SHIFT (28U)
5471 #define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
5472 #define CCM_CCGR2_CG15_MASK (0xC0000000U)
5473 #define CCM_CCGR2_CG15_SHIFT (30U)
5474 #define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
5479 #define CCM_CCGR3_CG0_MASK (0x3U)
5480 #define CCM_CCGR3_CG0_SHIFT (0U)
5481 #define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
5482 #define CCM_CCGR3_CG1_MASK (0xCU)
5483 #define CCM_CCGR3_CG1_SHIFT (2U)
5484 #define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
5485 #define CCM_CCGR3_CG2_MASK (0x30U)
5486 #define CCM_CCGR3_CG2_SHIFT (4U)
5487 #define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
5488 #define CCM_CCGR3_CG3_MASK (0xC0U)
5489 #define CCM_CCGR3_CG3_SHIFT (6U)
5490 #define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
5491 #define CCM_CCGR3_CG4_MASK (0x300U)
5492 #define CCM_CCGR3_CG4_SHIFT (8U)
5493 #define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
5494 #define CCM_CCGR3_CG5_MASK (0xC00U)
5495 #define CCM_CCGR3_CG5_SHIFT (10U)
5496 #define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
5497 #define CCM_CCGR3_CG6_MASK (0x3000U)
5498 #define CCM_CCGR3_CG6_SHIFT (12U)
5499 #define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
5500 #define CCM_CCGR3_CG7_MASK (0xC000U)
5501 #define CCM_CCGR3_CG7_SHIFT (14U)
5502 #define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
5503 #define CCM_CCGR3_CG8_MASK (0x30000U)
5504 #define CCM_CCGR3_CG8_SHIFT (16U)
5505 #define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
5506 #define CCM_CCGR3_CG9_MASK (0xC0000U)
5507 #define CCM_CCGR3_CG9_SHIFT (18U)
5508 #define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
5509 #define CCM_CCGR3_CG10_MASK (0x300000U)
5510 #define CCM_CCGR3_CG10_SHIFT (20U)
5511 #define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
5512 #define CCM_CCGR3_CG11_MASK (0xC00000U)
5513 #define CCM_CCGR3_CG11_SHIFT (22U)
5514 #define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
5515 #define CCM_CCGR3_CG12_MASK (0x3000000U)
5516 #define CCM_CCGR3_CG12_SHIFT (24U)
5517 #define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
5518 #define CCM_CCGR3_CG13_MASK (0xC000000U)
5519 #define CCM_CCGR3_CG13_SHIFT (26U)
5520 #define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
5521 #define CCM_CCGR3_CG14_MASK (0x30000000U)
5522 #define CCM_CCGR3_CG14_SHIFT (28U)
5525 #define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
5526 #define CCM_CCGR3_CG15_MASK (0xC0000000U)
5527 #define CCM_CCGR3_CG15_SHIFT (30U)
5528 #define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
5533 #define CCM_CCGR4_CG0_MASK (0x3U)
5534 #define CCM_CCGR4_CG0_SHIFT (0U)
5535 #define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
5536 #define CCM_CCGR4_CG1_MASK (0xCU)
5537 #define CCM_CCGR4_CG1_SHIFT (2U)
5538 #define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
5539 #define CCM_CCGR4_CG2_MASK (0x30U)
5540 #define CCM_CCGR4_CG2_SHIFT (4U)
5541 #define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
5542 #define CCM_CCGR4_CG3_MASK (0xC0U)
5543 #define CCM_CCGR4_CG3_SHIFT (6U)
5544 #define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
5545 #define CCM_CCGR4_CG4_MASK (0x300U)
5546 #define CCM_CCGR4_CG4_SHIFT (8U)
5547 #define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
5548 #define CCM_CCGR4_CG5_MASK (0xC00U)
5549 #define CCM_CCGR4_CG5_SHIFT (10U)
5550 #define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
5551 #define CCM_CCGR4_CG6_MASK (0x3000U)
5552 #define CCM_CCGR4_CG6_SHIFT (12U)
5553 #define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
5554 #define CCM_CCGR4_CG7_MASK (0xC000U)
5555 #define CCM_CCGR4_CG7_SHIFT (14U)
5556 #define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
5557 #define CCM_CCGR4_CG8_MASK (0x30000U)
5558 #define CCM_CCGR4_CG8_SHIFT (16U)
5559 #define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
5560 #define CCM_CCGR4_CG9_MASK (0xC0000U)
5561 #define CCM_CCGR4_CG9_SHIFT (18U)
5562 #define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
5563 #define CCM_CCGR4_CG10_MASK (0x300000U)
5564 #define CCM_CCGR4_CG10_SHIFT (20U)
5565 #define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
5566 #define CCM_CCGR4_CG11_MASK (0xC00000U)
5567 #define CCM_CCGR4_CG11_SHIFT (22U)
5568 #define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
5569 #define CCM_CCGR4_CG12_MASK (0x3000000U)
5570 #define CCM_CCGR4_CG12_SHIFT (24U)
5571 #define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
5572 #define CCM_CCGR4_CG13_MASK (0xC000000U)
5573 #define CCM_CCGR4_CG13_SHIFT (26U)
5574 #define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
5575 #define CCM_CCGR4_CG14_MASK (0x30000000U)
5576 #define CCM_CCGR4_CG14_SHIFT (28U)
5577 #define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
5578 #define CCM_CCGR4_CG15_MASK (0xC0000000U)
5579 #define CCM_CCGR4_CG15_SHIFT (30U)
5580 #define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
5585 #define CCM_CCGR5_CG0_MASK (0x3U)
5586 #define CCM_CCGR5_CG0_SHIFT (0U)
5587 #define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
5588 #define CCM_CCGR5_CG1_MASK (0xCU)
5589 #define CCM_CCGR5_CG1_SHIFT (2U)
5590 #define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
5591 #define CCM_CCGR5_CG2_MASK (0x30U)
5592 #define CCM_CCGR5_CG2_SHIFT (4U)
5593 #define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
5594 #define CCM_CCGR5_CG3_MASK (0xC0U)
5595 #define CCM_CCGR5_CG3_SHIFT (6U)
5596 #define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
5597 #define CCM_CCGR5_CG4_MASK (0x300U)
5598 #define CCM_CCGR5_CG4_SHIFT (8U)
5599 #define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
5600 #define CCM_CCGR5_CG5_MASK (0xC00U)
5601 #define CCM_CCGR5_CG5_SHIFT (10U)
5602 #define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
5603 #define CCM_CCGR5_CG6_MASK (0x3000U)
5604 #define CCM_CCGR5_CG6_SHIFT (12U)
5605 #define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
5606 #define CCM_CCGR5_CG7_MASK (0xC000U)
5607 #define CCM_CCGR5_CG7_SHIFT (14U)
5608 #define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
5609 #define CCM_CCGR5_CG8_MASK (0x30000U)
5610 #define CCM_CCGR5_CG8_SHIFT (16U)
5611 #define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
5612 #define CCM_CCGR5_CG9_MASK (0xC0000U)
5613 #define CCM_CCGR5_CG9_SHIFT (18U)
5614 #define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
5615 #define CCM_CCGR5_CG10_MASK (0x300000U)
5616 #define CCM_CCGR5_CG10_SHIFT (20U)
5617 #define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
5618 #define CCM_CCGR5_CG11_MASK (0xC00000U)
5619 #define CCM_CCGR5_CG11_SHIFT (22U)
5620 #define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
5621 #define CCM_CCGR5_CG12_MASK (0x3000000U)
5622 #define CCM_CCGR5_CG12_SHIFT (24U)
5623 #define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
5624 #define CCM_CCGR5_CG13_MASK (0xC000000U)
5625 #define CCM_CCGR5_CG13_SHIFT (26U)
5626 #define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
5627 #define CCM_CCGR5_CG14_MASK (0x30000000U)
5628 #define CCM_CCGR5_CG14_SHIFT (28U)
5629 #define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
5630 #define CCM_CCGR5_CG15_MASK (0xC0000000U)
5631 #define CCM_CCGR5_CG15_SHIFT (30U)
5632 #define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
5637 #define CCM_CCGR6_CG0_MASK (0x3U)
5638 #define CCM_CCGR6_CG0_SHIFT (0U)
5639 #define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
5640 #define CCM_CCGR6_CG1_MASK (0xCU)
5641 #define CCM_CCGR6_CG1_SHIFT (2U)
5642 #define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
5643 #define CCM_CCGR6_CG2_MASK (0x30U)
5644 #define CCM_CCGR6_CG2_SHIFT (4U)
5645 #define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
5646 #define CCM_CCGR6_CG3_MASK (0xC0U)
5647 #define CCM_CCGR6_CG3_SHIFT (6U)
5648 #define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
5649 #define CCM_CCGR6_CG4_MASK (0x300U)
5650 #define CCM_CCGR6_CG4_SHIFT (8U)
5651 #define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
5652 #define CCM_CCGR6_CG5_MASK (0xC00U)
5653 #define CCM_CCGR6_CG5_SHIFT (10U)
5654 #define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
5655 #define CCM_CCGR6_CG6_MASK (0x3000U)
5656 #define CCM_CCGR6_CG6_SHIFT (12U)
5657 #define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
5658 #define CCM_CCGR6_CG7_MASK (0xC000U)
5659 #define CCM_CCGR6_CG7_SHIFT (14U)
5660 #define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
5661 #define CCM_CCGR6_CG8_MASK (0x30000U)
5662 #define CCM_CCGR6_CG8_SHIFT (16U)
5663 #define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
5664 #define CCM_CCGR6_CG9_MASK (0xC0000U)
5665 #define CCM_CCGR6_CG9_SHIFT (18U)
5666 #define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
5667 #define CCM_CCGR6_CG10_MASK (0x300000U)
5668 #define CCM_CCGR6_CG10_SHIFT (20U)
5669 #define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
5670 #define CCM_CCGR6_CG11_MASK (0xC00000U)
5671 #define CCM_CCGR6_CG11_SHIFT (22U)
5672 #define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
5673 #define CCM_CCGR6_CG12_MASK (0x3000000U)
5674 #define CCM_CCGR6_CG12_SHIFT (24U)
5675 #define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
5676 #define CCM_CCGR6_CG13_MASK (0xC000000U)
5677 #define CCM_CCGR6_CG13_SHIFT (26U)
5678 #define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
5679 #define CCM_CCGR6_CG14_MASK (0x30000000U)
5680 #define CCM_CCGR6_CG14_SHIFT (28U)
5681 #define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
5682 #define CCM_CCGR6_CG15_MASK (0xC0000000U)
5683 #define CCM_CCGR6_CG15_SHIFT (30U)
5684 #define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
5689 #define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
5690 #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
5695 #define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
5696 #define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
5697 #define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
5702 #define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
5703 #define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
5704 #define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
5709 #define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
5710 #define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
5711 #define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
5716 #define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
5717 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
5718 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
5723 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
5724 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
5725 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
5730 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) /* end of group CCM_Register_Masks */
5737 
5738 
5739 /* CCM - Peripheral instance base addresses */
5741 #define CCM_BASE (0x400FC000u)
5743 #define CCM ((CCM_Type *)CCM_BASE)
5745 #define CCM_BASE_ADDRS { CCM_BASE }
5747 #define CCM_BASE_PTRS { CCM }
5749 #define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
5750  /* end of group CCM_Peripheral_Access_Layer */
5754 
5755 
5756 /* ----------------------------------------------------------------------------
5757  -- CCM_ANALOG Peripheral Access Layer
5758  ---------------------------------------------------------------------------- */
5759 
5766 typedef struct {
5767  uint8_t RESERVED_0[16];
5768  __IO uint32_t PLL_USB1;
5769  __IO uint32_t PLL_USB1_SET;
5770  __IO uint32_t PLL_USB1_CLR;
5771  __IO uint32_t PLL_USB1_TOG;
5772  uint8_t RESERVED_1[16];
5773  __IO uint32_t PLL_SYS;
5774  __IO uint32_t PLL_SYS_SET;
5775  __IO uint32_t PLL_SYS_CLR;
5776  __IO uint32_t PLL_SYS_TOG;
5777  __IO uint32_t PLL_SYS_SS;
5778  uint8_t RESERVED_2[12];
5779  __IO uint32_t PLL_SYS_NUM;
5780  uint8_t RESERVED_3[12];
5781  __IO uint32_t PLL_SYS_DENOM;
5782  uint8_t RESERVED_4[12];
5783  __IO uint32_t PLL_AUDIO;
5784  __IO uint32_t PLL_AUDIO_SET;
5785  __IO uint32_t PLL_AUDIO_CLR;
5786  __IO uint32_t PLL_AUDIO_TOG;
5787  __IO uint32_t PLL_AUDIO_NUM;
5788  uint8_t RESERVED_5[12];
5789  __IO uint32_t PLL_AUDIO_DENOM;
5790  uint8_t RESERVED_6[76];
5791  __IO uint32_t PLL_ENET;
5792  __IO uint32_t PLL_ENET_SET;
5793  __IO uint32_t PLL_ENET_CLR;
5794  __IO uint32_t PLL_ENET_TOG;
5795  __IO uint32_t PFD_480;
5796  __IO uint32_t PFD_480_SET;
5797  __IO uint32_t PFD_480_CLR;
5798  __IO uint32_t PFD_480_TOG;
5799  __IO uint32_t PFD_528;
5800  __IO uint32_t PFD_528_SET;
5801  __IO uint32_t PFD_528_CLR;
5802  __IO uint32_t PFD_528_TOG;
5803  uint8_t RESERVED_7[64];
5804  __IO uint32_t MISC0;
5805  __IO uint32_t MISC0_SET;
5806  __IO uint32_t MISC0_CLR;
5807  __IO uint32_t MISC0_TOG;
5808  __IO uint32_t MISC1;
5809  __IO uint32_t MISC1_SET;
5810  __IO uint32_t MISC1_CLR;
5811  __IO uint32_t MISC1_TOG;
5812  __IO uint32_t MISC2;
5813  __IO uint32_t MISC2_SET;
5814  __IO uint32_t MISC2_CLR;
5815  __IO uint32_t MISC2_TOG;
5816 } CCM_ANALOG_Type;
5817 
5818 /* ----------------------------------------------------------------------------
5819  -- CCM_ANALOG Register Masks
5820  ---------------------------------------------------------------------------- */
5821 
5829 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
5830 #define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
5831 #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
5832 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
5833 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
5838 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
5839 #define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
5840 #define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
5841 #define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
5842 #define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
5843 #define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
5844 #define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
5845 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
5846 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
5850 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
5851 #define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
5852 #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
5853 #define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
5854 #define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
5855 #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
5856 #define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
5861 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
5862 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
5863 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
5864 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
5865 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
5870 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
5871 #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
5872 #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
5873 #define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
5874 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
5875 #define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
5876 #define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
5877 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
5878 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
5882 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
5883 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
5884 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
5885 #define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
5886 #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
5887 #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
5888 #define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
5893 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
5894 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
5895 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
5896 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
5897 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
5902 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
5903 #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
5904 #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
5905 #define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
5906 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
5907 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
5908 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
5909 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
5910 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
5914 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
5915 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
5916 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
5917 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
5918 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
5919 #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
5920 #define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
5925 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
5926 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
5927 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
5928 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
5929 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
5934 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
5935 #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
5936 #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
5937 #define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
5938 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
5939 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
5940 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
5941 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
5942 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
5946 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
5947 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
5948 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
5949 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
5950 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
5951 #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
5952 #define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
5957 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
5958 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
5959 #define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
5960 #define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
5961 #define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
5962 #define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
5963 #define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
5964 #define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
5965 #define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
5966 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
5967 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
5971 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
5972 #define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
5973 #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
5974 #define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
5975 #define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
5976 #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
5977 #define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
5982 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
5983 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
5984 #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
5985 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
5986 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
5987 #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
5988 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
5989 #define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
5990 #define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
5991 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
5992 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
5996 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
5997 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
5998 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
5999 #define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
6000 #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
6001 #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
6002 #define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
6007 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
6008 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
6009 #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
6010 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
6011 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
6012 #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
6013 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
6014 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
6015 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
6016 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6017 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6021 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
6022 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
6023 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
6024 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
6025 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
6026 #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
6027 #define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
6032 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
6033 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
6034 #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
6035 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
6036 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
6037 #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
6038 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
6039 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
6040 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
6041 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6042 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6046 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
6047 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
6048 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
6049 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
6050 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
6051 #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
6052 #define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
6057 #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
6058 #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
6059 #define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
6060 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
6061 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
6066 #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
6067 #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
6068 #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
6069 #define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
6074 #define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
6075 #define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
6076 #define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
6081 #define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
6082 #define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
6083 #define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
6088 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
6089 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
6090 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
6091 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
6092 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
6093 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
6094 #define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
6095 #define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
6096 #define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
6097 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
6098 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
6104 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
6105 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
6106 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
6107 #define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
6108 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
6109 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
6116 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
6117 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
6118 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
6119 #define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
6124 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
6125 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
6126 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
6127 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
6128 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
6129 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
6130 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
6131 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
6132 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
6133 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6134 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
6140 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
6141 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
6142 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
6143 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
6144 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
6145 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
6152 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
6153 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
6154 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
6155 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
6160 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
6161 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
6162 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
6163 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
6164 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
6165 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
6166 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
6167 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
6168 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
6169 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6170 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6176 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
6177 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
6178 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
6179 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
6180 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
6181 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
6188 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
6189 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
6190 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
6191 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
6196 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
6197 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
6198 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
6199 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
6200 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
6201 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
6202 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
6203 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
6204 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
6205 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6206 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6212 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
6213 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
6214 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
6215 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
6216 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
6217 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
6224 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
6225 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
6226 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
6227 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
6232 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
6233 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
6234 #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
6239 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
6240 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
6241 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
6246 #define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
6247 #define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
6248 #define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
6249 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
6250 #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
6251 #define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
6252 #define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
6253 #define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
6254 #define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
6255 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
6256 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
6262 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
6263 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
6264 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
6265 #define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
6266 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
6267 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
6268 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
6269 #define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK (0x400000U)
6270 #define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT (22U)
6271 #define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK)
6272 #define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
6273 #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
6274 #define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
6279 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
6280 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
6281 #define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
6282 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
6283 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
6284 #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
6285 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
6286 #define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
6287 #define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
6288 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6289 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
6295 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
6296 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
6297 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
6298 #define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
6299 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
6300 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
6301 #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
6302 #define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK (0x400000U)
6303 #define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT (22U)
6304 #define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK)
6305 #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
6306 #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
6307 #define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
6312 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
6313 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
6314 #define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
6315 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
6316 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
6317 #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
6318 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
6319 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
6320 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
6321 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6322 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6328 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
6329 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
6330 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
6331 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
6332 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
6333 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
6334 #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
6335 #define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK (0x400000U)
6336 #define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT (22U)
6337 #define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK)
6338 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
6339 #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
6340 #define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
6345 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
6346 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
6347 #define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
6348 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
6349 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
6350 #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
6351 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
6352 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
6353 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
6354 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6355 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6361 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
6362 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
6363 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
6364 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
6365 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
6366 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
6367 #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
6368 #define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK (0x400000U)
6369 #define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT (22U)
6370 #define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK)
6371 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
6372 #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
6373 #define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
6378 #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
6379 #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
6380 #define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
6381 #define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
6382 #define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
6383 #define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
6384 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
6385 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
6386 #define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
6387 #define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
6388 #define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
6389 #define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
6390 #define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
6391 #define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
6392 #define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
6393 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
6394 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
6395 #define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
6396 #define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
6397 #define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
6398 #define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
6399 #define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
6400 #define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
6401 #define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
6402 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
6403 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
6404 #define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
6405 #define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
6406 #define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
6407 #define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
6408 #define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
6409 #define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
6410 #define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
6411 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
6412 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
6413 #define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
6418 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
6419 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
6420 #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
6421 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
6422 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
6423 #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
6424 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
6425 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
6426 #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
6427 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
6428 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
6429 #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
6430 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
6431 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
6432 #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
6433 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
6434 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
6435 #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
6436 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
6437 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
6438 #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
6439 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
6440 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
6441 #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
6442 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
6443 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
6444 #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
6445 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
6446 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
6447 #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
6448 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
6449 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
6450 #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
6451 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
6452 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
6453 #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
6458 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
6459 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
6460 #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
6461 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
6462 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
6463 #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
6464 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
6465 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
6466 #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
6467 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
6468 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
6469 #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
6470 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
6471 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
6472 #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
6473 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
6474 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
6475 #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
6476 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
6477 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
6478 #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
6479 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
6480 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
6481 #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
6482 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
6483 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
6484 #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
6485 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
6486 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
6487 #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
6488 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
6489 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
6490 #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
6491 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
6492 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
6493 #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
6498 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
6499 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
6500 #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
6501 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
6502 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
6503 #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
6504 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
6505 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
6506 #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
6507 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
6508 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
6509 #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
6510 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
6511 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
6512 #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
6513 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
6514 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
6515 #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
6516 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
6517 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
6518 #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
6519 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
6520 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
6521 #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
6522 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
6523 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
6524 #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
6525 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
6526 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
6527 #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
6528 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
6529 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
6530 #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
6531 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
6532 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
6533 #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
6538 #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
6539 #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
6540 #define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
6541 #define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
6542 #define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
6543 #define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
6544 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
6545 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
6546 #define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
6547 #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
6548 #define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
6549 #define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
6550 #define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
6551 #define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
6552 #define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
6553 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
6554 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
6555 #define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
6556 #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
6557 #define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
6558 #define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
6559 #define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
6560 #define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
6561 #define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
6562 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
6563 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
6564 #define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
6565 #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
6566 #define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
6567 #define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
6568 #define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
6569 #define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
6570 #define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
6571 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
6572 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
6573 #define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
6578 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
6579 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
6580 #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
6581 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
6582 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
6583 #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
6584 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
6585 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
6586 #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
6587 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
6588 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
6589 #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
6590 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
6591 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
6592 #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
6593 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
6594 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
6595 #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
6596 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
6597 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
6598 #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
6599 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
6600 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
6601 #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
6602 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
6603 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
6604 #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
6605 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
6606 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
6607 #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
6608 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
6609 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
6610 #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
6611 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
6612 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
6613 #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
6618 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
6619 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
6620 #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
6621 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
6622 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
6623 #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
6624 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
6625 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
6626 #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
6627 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
6628 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
6629 #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
6630 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
6631 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
6632 #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
6633 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
6634 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
6635 #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
6636 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
6637 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
6638 #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
6639 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
6640 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
6641 #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
6642 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
6643 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
6644 #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
6645 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
6646 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
6647 #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
6648 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
6649 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
6650 #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
6651 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
6652 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
6653 #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
6658 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
6659 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
6660 #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
6661 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
6662 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
6663 #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
6664 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
6665 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
6666 #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
6667 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
6668 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
6669 #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
6670 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
6671 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
6672 #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
6673 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
6674 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
6675 #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
6676 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
6677 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
6678 #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
6679 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
6680 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
6681 #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
6682 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
6683 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
6684 #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
6685 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
6686 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
6687 #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
6688 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
6689 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
6690 #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
6691 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
6692 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
6693 #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
6698 #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
6699 #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
6700 #define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
6701 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
6702 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
6707 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
6708 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
6709 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
6720 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
6721 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
6722 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
6723 #define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
6724 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
6725 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
6733 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
6734 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
6735 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
6740 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
6741 #define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
6742 #define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
6749 #define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
6750 #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
6751 #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
6752 #define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
6753 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
6754 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
6755 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
6756 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
6757 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
6762 #define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
6763 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
6764 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
6775 #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
6776 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
6777 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
6782 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
6783 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
6784 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
6785 #define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
6790 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
6791 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
6792 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
6793 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
6794 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
6799 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
6800 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
6801 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
6812 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
6813 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
6814 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
6815 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
6816 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
6817 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
6825 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
6826 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
6827 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
6832 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
6833 #define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
6834 #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
6841 #define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
6842 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
6843 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
6844 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
6845 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
6846 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
6847 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
6848 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
6849 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
6854 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
6855 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
6856 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
6867 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
6868 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
6869 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
6874 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
6875 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
6876 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
6877 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
6882 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
6883 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
6884 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
6885 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
6886 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
6891 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
6892 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
6893 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
6904 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
6905 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
6906 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
6907 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
6908 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
6909 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
6917 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
6918 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
6919 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
6924 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
6925 #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
6926 #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
6933 #define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
6934 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
6935 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
6936 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
6937 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
6938 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
6939 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
6940 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
6941 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
6946 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
6947 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
6948 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
6959 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
6960 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
6961 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
6966 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
6967 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
6968 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
6969 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
6974 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
6975 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
6976 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
6977 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
6978 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
6983 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
6984 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
6985 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
6996 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
6997 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
6998 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
6999 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
7000 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
7001 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
7009 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
7010 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
7011 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
7016 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
7017 #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
7018 #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
7025 #define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
7026 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
7027 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
7028 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
7029 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
7030 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
7031 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
7032 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
7033 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
7038 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
7039 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
7040 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
7051 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
7052 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
7053 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
7058 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
7059 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
7060 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
7061 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
7066 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7067 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
7068 #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
7069 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7070 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
7071 #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
7072 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
7073 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
7074 #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
7075 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
7076 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
7077 #define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
7078 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
7079 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
7080 #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
7081 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
7082 #define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
7083 #define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
7084 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
7085 #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
7086 #define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
7091 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7092 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
7093 #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
7094 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7095 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
7096 #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
7097 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
7098 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
7099 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
7100 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
7101 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
7102 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
7103 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
7104 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
7105 #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
7106 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
7107 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
7108 #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
7109 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
7110 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
7111 #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
7116 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7117 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
7118 #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
7119 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7120 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
7121 #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
7122 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
7123 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
7124 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
7125 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
7126 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
7127 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
7128 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
7129 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
7130 #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
7131 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
7132 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
7133 #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
7134 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
7135 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
7136 #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
7141 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7142 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
7143 #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
7144 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7145 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
7146 #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
7147 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
7148 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
7149 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
7150 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
7151 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
7152 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
7153 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
7154 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
7155 #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
7156 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
7157 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
7158 #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
7159 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
7160 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
7161 #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
7166 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
7167 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
7172 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
7173 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
7174 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
7178 #define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
7179 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
7180 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
7181 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
7182 #define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
7183 #define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
7184 #define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
7185 #define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U)
7186 #define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U)
7191 #define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)
7192 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
7193 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
7198 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
7199 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
7200 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
7204 #define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
7205 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
7206 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
7207 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
7208 #define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
7209 #define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
7210 #define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
7211 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
7212 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
7217 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
7218 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
7219 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
7224 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
7225 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
7226 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
7227 #define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
7228 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
7229 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
7230 #define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
7231 #define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
7232 #define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
7233 #define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
7234 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
7235 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
7240 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
7241 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
7242 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
7249 #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
7250 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
7251 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
7258 #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
7259 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
7260 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
7267 #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
7272 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
7273 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
7278 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
7279 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
7280 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
7284 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
7285 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
7286 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
7287 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
7288 #define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
7289 #define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
7290 #define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
7291 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)
7292 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)
7297 #define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)
7298 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
7299 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
7304 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
7305 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
7306 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
7310 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
7311 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
7312 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
7313 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
7314 #define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
7315 #define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
7316 #define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
7317 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
7318 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
7323 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
7324 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
7325 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
7330 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
7331 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
7332 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
7333 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
7334 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
7335 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
7336 #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
7337 #define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
7338 #define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
7339 #define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
7340 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
7341 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
7346 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
7347 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
7348 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
7355 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
7356 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
7357 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
7364 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
7365 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
7366 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
7373 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
7378 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
7379 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
7384 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
7385 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
7386 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
7390 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
7391 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
7392 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
7393 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
7394 #define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
7395 #define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
7396 #define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
7397 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)
7398 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)
7403 #define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)
7404 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
7405 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
7410 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
7411 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
7412 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
7416 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
7417 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
7418 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
7419 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
7420 #define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
7421 #define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
7422 #define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
7423 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
7424 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
7429 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
7430 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
7431 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
7436 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
7437 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
7438 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
7439 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
7440 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
7441 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
7442 #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
7443 #define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
7444 #define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
7445 #define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
7446 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
7447 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
7452 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
7453 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
7454 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
7461 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
7462 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
7463 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
7470 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
7471 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
7472 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
7479 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
7484 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
7485 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
7490 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
7491 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
7492 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
7496 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
7497 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
7498 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
7499 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
7500 #define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
7501 #define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
7502 #define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
7503 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)
7504 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)
7509 #define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)
7510 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
7511 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
7516 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
7517 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
7518 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
7522 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
7523 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
7524 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
7525 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
7526 #define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
7527 #define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
7528 #define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
7529 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
7530 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
7535 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
7536 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
7537 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
7542 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
7543 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
7544 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
7545 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
7546 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
7547 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
7548 #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
7549 #define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
7550 #define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
7551 #define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
7552 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
7553 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
7558 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
7559 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
7560 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
7567 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
7568 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
7569 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
7576 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
7577 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
7578 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
7585 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) /* end of group CCM_ANALOG_Register_Masks */
7592 
7593 
7594 /* CCM_ANALOG - Peripheral instance base addresses */
7596 #define CCM_ANALOG_BASE (0x400D8000u)
7598 #define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
7600 #define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
7602 #define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
7603  /* end of group CCM_ANALOG_Peripheral_Access_Layer */
7607 
7608 
7609 /* ----------------------------------------------------------------------------
7610  -- CM7_MCM Peripheral Access Layer
7611  ---------------------------------------------------------------------------- */
7612 
7619 typedef struct {
7620  uint8_t RESERVED_0[16];
7621  __IO uint32_t ISCR;
7622 } CM7_MCM_Type;
7623 
7624 /* ----------------------------------------------------------------------------
7625  -- CM7_MCM Register Masks
7626  ---------------------------------------------------------------------------- */
7627 
7635 #define CM7_MCM_ISCR_WABS_MASK (0x20U)
7636 #define CM7_MCM_ISCR_WABS_SHIFT (5U)
7641 #define CM7_MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK)
7642 #define CM7_MCM_ISCR_WABSO_MASK (0x40U)
7643 #define CM7_MCM_ISCR_WABSO_SHIFT (6U)
7648 #define CM7_MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK)
7649 #define CM7_MCM_ISCR_FIOC_MASK (0x100U)
7650 #define CM7_MCM_ISCR_FIOC_SHIFT (8U)
7655 #define CM7_MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK)
7656 #define CM7_MCM_ISCR_FDZC_MASK (0x200U)
7657 #define CM7_MCM_ISCR_FDZC_SHIFT (9U)
7662 #define CM7_MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK)
7663 #define CM7_MCM_ISCR_FOFC_MASK (0x400U)
7664 #define CM7_MCM_ISCR_FOFC_SHIFT (10U)
7669 #define CM7_MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK)
7670 #define CM7_MCM_ISCR_FUFC_MASK (0x800U)
7671 #define CM7_MCM_ISCR_FUFC_SHIFT (11U)
7676 #define CM7_MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK)
7677 #define CM7_MCM_ISCR_FIXC_MASK (0x1000U)
7678 #define CM7_MCM_ISCR_FIXC_SHIFT (12U)
7683 #define CM7_MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK)
7684 #define CM7_MCM_ISCR_FIDC_MASK (0x8000U)
7685 #define CM7_MCM_ISCR_FIDC_SHIFT (15U)
7690 #define CM7_MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK)
7691 #define CM7_MCM_ISCR_WABE_MASK (0x200000U)
7692 #define CM7_MCM_ISCR_WABE_SHIFT (21U)
7697 #define CM7_MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK)
7698 #define CM7_MCM_ISCR_FIOCE_MASK (0x1000000U)
7699 #define CM7_MCM_ISCR_FIOCE_SHIFT (24U)
7704 #define CM7_MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK)
7705 #define CM7_MCM_ISCR_FDZCE_MASK (0x2000000U)
7706 #define CM7_MCM_ISCR_FDZCE_SHIFT (25U)
7711 #define CM7_MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK)
7712 #define CM7_MCM_ISCR_FOFCE_MASK (0x4000000U)
7713 #define CM7_MCM_ISCR_FOFCE_SHIFT (26U)
7718 #define CM7_MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK)
7719 #define CM7_MCM_ISCR_FUFCE_MASK (0x8000000U)
7720 #define CM7_MCM_ISCR_FUFCE_SHIFT (27U)
7725 #define CM7_MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK)
7726 #define CM7_MCM_ISCR_FIXCE_MASK (0x10000000U)
7727 #define CM7_MCM_ISCR_FIXCE_SHIFT (28U)
7732 #define CM7_MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK)
7733 #define CM7_MCM_ISCR_FIDCE_MASK (0x80000000U)
7734 #define CM7_MCM_ISCR_FIDCE_SHIFT (31U)
7739 #define CM7_MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK) /* end of group CM7_MCM_Register_Masks */
7746 
7747 
7748 /* CM7_MCM - Peripheral instance base addresses */
7750 #define CM7_MCM_BASE (0xE0080000u)
7752 #define CM7_MCM ((CM7_MCM_Type *)CM7_MCM_BASE)
7754 #define CM7_MCM_BASE_ADDRS { CM7_MCM_BASE }
7756 #define CM7_MCM_BASE_PTRS { CM7_MCM }
7757  /* end of group CM7_MCM_Peripheral_Access_Layer */
7761 
7762 
7763 /* ----------------------------------------------------------------------------
7764  -- CMP Peripheral Access Layer
7765  ---------------------------------------------------------------------------- */
7766 
7773 typedef struct {
7774  __IO uint8_t CR0;
7775  __IO uint8_t CR1;
7776  __IO uint8_t FPR;
7777  __IO uint8_t SCR;
7778  __IO uint8_t DACCR;
7779  __IO uint8_t MUXCR;
7780 } CMP_Type;
7781 
7782 /* ----------------------------------------------------------------------------
7783  -- CMP Register Masks
7784  ---------------------------------------------------------------------------- */
7785 
7793 #define CMP_CR0_HYSTCTR_MASK (0x3U)
7794 #define CMP_CR0_HYSTCTR_SHIFT (0U)
7801 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
7802 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
7803 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
7814 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
7819 #define CMP_CR1_EN_MASK (0x1U)
7820 #define CMP_CR1_EN_SHIFT (0U)
7825 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
7826 #define CMP_CR1_OPE_MASK (0x2U)
7827 #define CMP_CR1_OPE_SHIFT (1U)
7834 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
7835 #define CMP_CR1_COS_MASK (0x4U)
7836 #define CMP_CR1_COS_SHIFT (2U)
7841 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
7842 #define CMP_CR1_INV_MASK (0x8U)
7843 #define CMP_CR1_INV_SHIFT (3U)
7848 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
7849 #define CMP_CR1_PMODE_MASK (0x10U)
7850 #define CMP_CR1_PMODE_SHIFT (4U)
7855 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
7856 #define CMP_CR1_WE_MASK (0x40U)
7857 #define CMP_CR1_WE_SHIFT (6U)
7862 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
7863 #define CMP_CR1_SE_MASK (0x80U)
7864 #define CMP_CR1_SE_SHIFT (7U)
7869 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
7874 #define CMP_FPR_FILT_PER_MASK (0xFFU)
7875 #define CMP_FPR_FILT_PER_SHIFT (0U)
7878 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
7883 #define CMP_SCR_COUT_MASK (0x1U)
7884 #define CMP_SCR_COUT_SHIFT (0U)
7887 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
7888 #define CMP_SCR_CFF_MASK (0x2U)
7889 #define CMP_SCR_CFF_SHIFT (1U)
7894 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
7895 #define CMP_SCR_CFR_MASK (0x4U)
7896 #define CMP_SCR_CFR_SHIFT (2U)
7901 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
7902 #define CMP_SCR_IEF_MASK (0x8U)
7903 #define CMP_SCR_IEF_SHIFT (3U)
7908 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
7909 #define CMP_SCR_IER_MASK (0x10U)
7910 #define CMP_SCR_IER_SHIFT (4U)
7915 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
7916 #define CMP_SCR_DMAEN_MASK (0x40U)
7917 #define CMP_SCR_DMAEN_SHIFT (6U)
7922 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
7927 #define CMP_DACCR_VOSEL_MASK (0x3FU)
7928 #define CMP_DACCR_VOSEL_SHIFT (0U)
7931 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
7932 #define CMP_DACCR_VRSEL_MASK (0x40U)
7933 #define CMP_DACCR_VRSEL_SHIFT (6U)
7938 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
7939 #define CMP_DACCR_DACEN_MASK (0x80U)
7940 #define CMP_DACCR_DACEN_SHIFT (7U)
7945 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
7950 #define CMP_MUXCR_MSEL_MASK (0x7U)
7951 #define CMP_MUXCR_MSEL_SHIFT (0U)
7962 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
7963 #define CMP_MUXCR_PSEL_MASK (0x38U)
7964 #define CMP_MUXCR_PSEL_SHIFT (3U)
7975 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) /* end of group CMP_Register_Masks */
7982 
7983 
7984 /* CMP - Peripheral instance base addresses */
7986 #define CMP1_BASE (0x40094000u)
7988 #define CMP1 ((CMP_Type *)CMP1_BASE)
7990 #define CMP2_BASE (0x40094008u)
7992 #define CMP2 ((CMP_Type *)CMP2_BASE)
7994 #define CMP3_BASE (0x40094010u)
7996 #define CMP3 ((CMP_Type *)CMP3_BASE)
7998 #define CMP4_BASE (0x40094018u)
8000 #define CMP4 ((CMP_Type *)CMP4_BASE)
8002 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
8004 #define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
8006 #define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
8007  /* end of group CMP_Peripheral_Access_Layer */
8011 
8012 
8013 /* ----------------------------------------------------------------------------
8014  -- CSU Peripheral Access Layer
8015  ---------------------------------------------------------------------------- */
8016 
8023 typedef struct {
8024  __IO uint32_t CSL[32];
8025  uint8_t RESERVED_0[384];
8026  __IO uint32_t HP0;
8027  uint8_t RESERVED_1[20];
8028  __IO uint32_t SA;
8029  uint8_t RESERVED_2[316];
8030  __IO uint32_t HPCONTROL0;
8031 } CSU_Type;
8032 
8033 /* ----------------------------------------------------------------------------
8034  -- CSU Register Masks
8035  ---------------------------------------------------------------------------- */
8036 
8044 #define CSU_CSL_SUR_S2_MASK (0x1U)
8045 #define CSU_CSL_SUR_S2_SHIFT (0U)
8050 #define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
8051 #define CSU_CSL_SSR_S2_MASK (0x2U)
8052 #define CSU_CSL_SSR_S2_SHIFT (1U)
8057 #define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
8058 #define CSU_CSL_NUR_S2_MASK (0x4U)
8059 #define CSU_CSL_NUR_S2_SHIFT (2U)
8064 #define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
8065 #define CSU_CSL_NSR_S2_MASK (0x8U)
8066 #define CSU_CSL_NSR_S2_SHIFT (3U)
8071 #define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
8072 #define CSU_CSL_SUW_S2_MASK (0x10U)
8073 #define CSU_CSL_SUW_S2_SHIFT (4U)
8078 #define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
8079 #define CSU_CSL_SSW_S2_MASK (0x20U)
8080 #define CSU_CSL_SSW_S2_SHIFT (5U)
8085 #define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
8086 #define CSU_CSL_NUW_S2_MASK (0x40U)
8087 #define CSU_CSL_NUW_S2_SHIFT (6U)
8092 #define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
8093 #define CSU_CSL_NSW_S2_MASK (0x80U)
8094 #define CSU_CSL_NSW_S2_SHIFT (7U)
8099 #define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
8100 #define CSU_CSL_LOCK_S2_MASK (0x100U)
8101 #define CSU_CSL_LOCK_S2_SHIFT (8U)
8106 #define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
8107 #define CSU_CSL_SUR_S1_MASK (0x10000U)
8108 #define CSU_CSL_SUR_S1_SHIFT (16U)
8113 #define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
8114 #define CSU_CSL_SSR_S1_MASK (0x20000U)
8115 #define CSU_CSL_SSR_S1_SHIFT (17U)
8120 #define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
8121 #define CSU_CSL_NUR_S1_MASK (0x40000U)
8122 #define CSU_CSL_NUR_S1_SHIFT (18U)
8127 #define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
8128 #define CSU_CSL_NSR_S1_MASK (0x80000U)
8129 #define CSU_CSL_NSR_S1_SHIFT (19U)
8134 #define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
8135 #define CSU_CSL_SUW_S1_MASK (0x100000U)
8136 #define CSU_CSL_SUW_S1_SHIFT (20U)
8141 #define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
8142 #define CSU_CSL_SSW_S1_MASK (0x200000U)
8143 #define CSU_CSL_SSW_S1_SHIFT (21U)
8148 #define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
8149 #define CSU_CSL_NUW_S1_MASK (0x400000U)
8150 #define CSU_CSL_NUW_S1_SHIFT (22U)
8155 #define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
8156 #define CSU_CSL_NSW_S1_MASK (0x800000U)
8157 #define CSU_CSL_NSW_S1_SHIFT (23U)
8162 #define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
8163 #define CSU_CSL_LOCK_S1_MASK (0x1000000U)
8164 #define CSU_CSL_LOCK_S1_SHIFT (24U)
8169 #define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
8172 /* The count of CSU_CSL */
8173 #define CSU_CSL_COUNT (32U)
8174 
8177 #define CSU_HP0_HP_DMA_MASK (0x4U)
8178 #define CSU_HP0_HP_DMA_SHIFT (2U)
8183 #define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
8184 #define CSU_HP0_L_DMA_MASK (0x8U)
8185 #define CSU_HP0_L_DMA_SHIFT (3U)
8190 #define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
8191 #define CSU_HP0_HP_LCDIF_MASK (0x10U)
8192 #define CSU_HP0_HP_LCDIF_SHIFT (4U)
8197 #define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
8198 #define CSU_HP0_L_LCDIF_MASK (0x20U)
8199 #define CSU_HP0_L_LCDIF_SHIFT (5U)
8204 #define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
8205 #define CSU_HP0_HP_CSI_MASK (0x40U)
8206 #define CSU_HP0_HP_CSI_SHIFT (6U)
8211 #define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
8212 #define CSU_HP0_L_CSI_MASK (0x80U)
8213 #define CSU_HP0_L_CSI_SHIFT (7U)
8218 #define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
8219 #define CSU_HP0_HP_PXP_MASK (0x100U)
8220 #define CSU_HP0_HP_PXP_SHIFT (8U)
8225 #define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
8226 #define CSU_HP0_L_PXP_MASK (0x200U)
8227 #define CSU_HP0_L_PXP_SHIFT (9U)
8232 #define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
8233 #define CSU_HP0_HP_DCP_MASK (0x400U)
8234 #define CSU_HP0_HP_DCP_SHIFT (10U)
8239 #define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
8240 #define CSU_HP0_L_DCP_MASK (0x800U)
8241 #define CSU_HP0_L_DCP_SHIFT (11U)
8246 #define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
8247 #define CSU_HP0_HP_ENET_MASK (0x4000U)
8248 #define CSU_HP0_HP_ENET_SHIFT (14U)
8253 #define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
8254 #define CSU_HP0_L_ENET_MASK (0x8000U)
8255 #define CSU_HP0_L_ENET_SHIFT (15U)
8260 #define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
8261 #define CSU_HP0_HP_USDHC1_MASK (0x10000U)
8262 #define CSU_HP0_HP_USDHC1_SHIFT (16U)
8267 #define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
8268 #define CSU_HP0_L_USDHC1_MASK (0x20000U)
8269 #define CSU_HP0_L_USDHC1_SHIFT (17U)
8274 #define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
8275 #define CSU_HP0_HP_USDHC2_MASK (0x40000U)
8276 #define CSU_HP0_HP_USDHC2_SHIFT (18U)
8281 #define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
8282 #define CSU_HP0_L_USDHC2_MASK (0x80000U)
8283 #define CSU_HP0_L_USDHC2_SHIFT (19U)
8288 #define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
8289 #define CSU_HP0_HP_TPSMP_MASK (0x100000U)
8290 #define CSU_HP0_HP_TPSMP_SHIFT (20U)
8295 #define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
8296 #define CSU_HP0_L_TPSMP_MASK (0x200000U)
8297 #define CSU_HP0_L_TPSMP_SHIFT (21U)
8302 #define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
8303 #define CSU_HP0_HP_USB_MASK (0x400000U)
8304 #define CSU_HP0_HP_USB_SHIFT (22U)
8309 #define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
8310 #define CSU_HP0_L_USB_MASK (0x800000U)
8311 #define CSU_HP0_L_USB_SHIFT (23U)
8316 #define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
8321 #define CSU_SA_NSA_DMA_MASK (0x4U)
8322 #define CSU_SA_NSA_DMA_SHIFT (2U)
8327 #define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
8328 #define CSU_SA_L_DMA_MASK (0x8U)
8329 #define CSU_SA_L_DMA_SHIFT (3U)
8334 #define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
8335 #define CSU_SA_NSA_LCDIF_MASK (0x10U)
8336 #define CSU_SA_NSA_LCDIF_SHIFT (4U)
8341 #define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
8342 #define CSU_SA_L_LCDIF_MASK (0x20U)
8343 #define CSU_SA_L_LCDIF_SHIFT (5U)
8348 #define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
8349 #define CSU_SA_NSA_CSI_MASK (0x40U)
8350 #define CSU_SA_NSA_CSI_SHIFT (6U)
8355 #define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
8356 #define CSU_SA_L_CSI_MASK (0x80U)
8357 #define CSU_SA_L_CSI_SHIFT (7U)
8362 #define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
8363 #define CSU_SA_NSA_PXP_MASK (0x100U)
8364 #define CSU_SA_NSA_PXP_SHIFT (8U)
8369 #define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
8370 #define CSU_SA_L_PXP_MASK (0x200U)
8371 #define CSU_SA_L_PXP_SHIFT (9U)
8376 #define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
8377 #define CSU_SA_NSA_DCP_MASK (0x400U)
8378 #define CSU_SA_NSA_DCP_SHIFT (10U)
8383 #define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
8384 #define CSU_SA_L_DCP_MASK (0x800U)
8385 #define CSU_SA_L_DCP_SHIFT (11U)
8390 #define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
8391 #define CSU_SA_NSA_ENET_MASK (0x4000U)
8392 #define CSU_SA_NSA_ENET_SHIFT (14U)
8397 #define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
8398 #define CSU_SA_L_ENET_MASK (0x8000U)
8399 #define CSU_SA_L_ENET_SHIFT (15U)
8404 #define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
8405 #define CSU_SA_NSA_USDHC1_MASK (0x10000U)
8406 #define CSU_SA_NSA_USDHC1_SHIFT (16U)
8411 #define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
8412 #define CSU_SA_L_USDHC1_MASK (0x20000U)
8413 #define CSU_SA_L_USDHC1_SHIFT (17U)
8418 #define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
8419 #define CSU_SA_NSA_USDHC2_MASK (0x40000U)
8420 #define CSU_SA_NSA_USDHC2_SHIFT (18U)
8425 #define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
8426 #define CSU_SA_L_USDHC2_MASK (0x80000U)
8427 #define CSU_SA_L_USDHC2_SHIFT (19U)
8432 #define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
8433 #define CSU_SA_NSA_TPSMP_MASK (0x100000U)
8434 #define CSU_SA_NSA_TPSMP_SHIFT (20U)
8439 #define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
8440 #define CSU_SA_L_TPSMP_MASK (0x200000U)
8441 #define CSU_SA_L_TPSMP_SHIFT (21U)
8446 #define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
8447 #define CSU_SA_NSA_USB_MASK (0x400000U)
8448 #define CSU_SA_NSA_USB_SHIFT (22U)
8453 #define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
8454 #define CSU_SA_L_USB_MASK (0x800000U)
8455 #define CSU_SA_L_USB_SHIFT (23U)
8460 #define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
8465 #define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
8466 #define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
8471 #define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
8472 #define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
8473 #define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
8478 #define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
8479 #define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
8480 #define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
8485 #define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
8486 #define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
8487 #define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
8492 #define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
8493 #define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
8494 #define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
8499 #define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
8500 #define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
8501 #define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
8506 #define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
8507 #define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
8508 #define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
8513 #define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
8514 #define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
8515 #define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
8520 #define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
8521 #define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
8522 #define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
8527 #define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
8528 #define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
8529 #define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
8534 #define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
8535 #define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
8536 #define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
8541 #define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
8542 #define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
8543 #define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
8548 #define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
8549 #define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
8550 #define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
8555 #define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
8556 #define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
8557 #define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
8562 #define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
8563 #define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
8564 #define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
8569 #define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
8570 #define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
8571 #define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
8576 #define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
8577 #define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
8578 #define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
8583 #define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
8584 #define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
8585 #define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
8590 #define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
8591 #define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
8592 #define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
8597 #define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
8598 #define CSU_HPCONTROL0_L_USB_MASK (0x800000U)
8599 #define CSU_HPCONTROL0_L_USB_SHIFT (23U)
8604 #define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) /* end of group CSU_Register_Masks */
8611 
8612 
8613 /* CSU - Peripheral instance base addresses */
8615 #define CSU_BASE (0x400DC000u)
8617 #define CSU ((CSU_Type *)CSU_BASE)
8619 #define CSU_BASE_ADDRS { CSU_BASE }
8621 #define CSU_BASE_PTRS { CSU }
8622  /* end of group CSU_Peripheral_Access_Layer */
8626 
8627 
8628 /* ----------------------------------------------------------------------------
8629  -- DCDC Peripheral Access Layer
8630  ---------------------------------------------------------------------------- */
8631 
8638 typedef struct {
8639  __IO uint32_t REG0;
8640  __IO uint32_t REG1;
8641  __IO uint32_t REG2;
8642  __IO uint32_t REG3;
8643 } DCDC_Type;
8644 
8645 /* ----------------------------------------------------------------------------
8646  -- DCDC Register Masks
8647  ---------------------------------------------------------------------------- */
8648 
8656 #define DCDC_REG0_PWD_ZCD_MASK (0x1U)
8657 #define DCDC_REG0_PWD_ZCD_SHIFT (0U)
8662 #define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
8663 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
8664 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
8669 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
8670 #define DCDC_REG0_SEL_CLK_MASK (0x4U)
8671 #define DCDC_REG0_SEL_CLK_SHIFT (2U)
8676 #define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
8677 #define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
8678 #define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
8683 #define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
8684 #define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
8685 #define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
8690 #define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
8691 #define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
8692 #define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
8701 #define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
8702 #define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
8703 #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
8708 #define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
8709 #define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
8710 #define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
8717 #define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
8718 #define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
8719 #define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
8724 #define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
8725 #define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
8726 #define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
8731 #define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
8732 #define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
8733 #define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
8738 #define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
8739 #define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
8740 #define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
8747 #define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
8748 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
8749 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
8754 #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
8755 #define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
8756 #define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
8761 #define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
8762 #define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
8763 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
8768 #define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
8769 #define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
8770 #define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
8775 #define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
8776 #define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
8777 #define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
8782 #define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
8783 #define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
8784 #define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
8789 #define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
8790 #define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
8791 #define DCDC_REG0_STS_DC_OK_SHIFT (31U)
8796 #define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
8801 #define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
8802 #define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
8809 #define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
8810 #define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
8811 #define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
8816 #define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
8817 #define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
8818 #define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
8825 #define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
8826 #define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
8827 #define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
8832 #define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
8833 #define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
8834 #define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
8839 #define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
8840 #define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
8841 #define DCDC_REG1_VBG_TRIM_SHIFT (24U)
8844 #define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
8849 #define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
8850 #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
8851 #define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
8852 #define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
8853 #define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
8854 #define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
8855 #define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
8856 #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
8857 #define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
8858 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
8859 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
8862 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
8863 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
8864 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
8869 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
8870 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
8871 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
8876 #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
8877 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U)
8878 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U)
8879 #define DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
8880 #define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
8881 #define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
8886 #define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
8887 #define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
8888 #define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
8891 #define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
8896 #define DCDC_REG3_TRG_MASK (0x1FU)
8897 #define DCDC_REG3_TRG_SHIFT (0U)
8900 #define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
8901 #define DCDC_REG3_TARGET_LP_MASK (0x700U)
8902 #define DCDC_REG3_TARGET_LP_SHIFT (8U)
8910 #define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
8911 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
8912 #define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
8917 #define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
8918 #define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
8919 #define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
8920 #define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
8921 #define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
8922 #define DCDC_REG3_DISABLE_STEP_SHIFT (30U)
8927 #define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) /* end of group DCDC_Register_Masks */
8934 
8935 
8936 /* DCDC - Peripheral instance base addresses */
8938 #define DCDC_BASE (0x40080000u)
8940 #define DCDC ((DCDC_Type *)DCDC_BASE)
8942 #define DCDC_BASE_ADDRS { DCDC_BASE }
8944 #define DCDC_BASE_PTRS { DCDC }
8946 #define DCDC_IRQS { DCDC_IRQn }
8947  /* end of group DCDC_Peripheral_Access_Layer */
8951 
8952 
8953 /* ----------------------------------------------------------------------------
8954  -- DCP Peripheral Access Layer
8955  ---------------------------------------------------------------------------- */
8956 
8963 typedef struct {
8964  __IO uint32_t CTRL;
8965  __IO uint32_t CTRL_SET;
8966  __IO uint32_t CTRL_CLR;
8967  __IO uint32_t CTRL_TOG;
8968  __IO uint32_t STAT;
8969  __IO uint32_t STAT_SET;
8970  __IO uint32_t STAT_CLR;
8971  __IO uint32_t STAT_TOG;
8972  __IO uint32_t CHANNELCTRL;
8973  __IO uint32_t CHANNELCTRL_SET;
8974  __IO uint32_t CHANNELCTRL_CLR;
8975  __IO uint32_t CHANNELCTRL_TOG;
8976  __IO uint32_t CAPABILITY0;
8977  uint8_t RESERVED_0[12];
8978  __I uint32_t CAPABILITY1;
8979  uint8_t RESERVED_1[12];
8980  __IO uint32_t CONTEXT;
8981  uint8_t RESERVED_2[12];
8982  __IO uint32_t KEY;
8983  uint8_t RESERVED_3[12];
8984  __IO uint32_t KEYDATA;
8985  uint8_t RESERVED_4[12];
8986  __I uint32_t PACKET0;
8987  uint8_t RESERVED_5[12];
8988  __I uint32_t PACKET1;
8989  uint8_t RESERVED_6[12];
8990  __I uint32_t PACKET2;
8991  uint8_t RESERVED_7[12];
8992  __I uint32_t PACKET3;
8993  uint8_t RESERVED_8[12];
8994  __I uint32_t PACKET4;
8995  uint8_t RESERVED_9[12];
8996  __I uint32_t PACKET5;
8997  uint8_t RESERVED_10[12];
8998  __I uint32_t PACKET6;
8999  uint8_t RESERVED_11[28];
9000  __IO uint32_t CH0CMDPTR;
9001  uint8_t RESERVED_12[12];
9002  __IO uint32_t CH0SEMA;
9003  uint8_t RESERVED_13[12];
9004  __IO uint32_t CH0STAT;
9005  __IO uint32_t CH0STAT_SET;
9006  __IO uint32_t CH0STAT_CLR;
9007  __IO uint32_t CH0STAT_TOG;
9008  __IO uint32_t CH0OPTS;
9009  __IO uint32_t CH0OPTS_SET;
9010  __IO uint32_t CH0OPTS_CLR;
9011  __IO uint32_t CH0OPTS_TOG;
9012  __IO uint32_t CH1CMDPTR;
9013  uint8_t RESERVED_14[12];
9014  __IO uint32_t CH1SEMA;
9015  uint8_t RESERVED_15[12];
9016  __IO uint32_t CH1STAT;
9017  __IO uint32_t CH1STAT_SET;
9018  __IO uint32_t CH1STAT_CLR;
9019  __IO uint32_t CH1STAT_TOG;
9020  __IO uint32_t CH1OPTS;
9021  __IO uint32_t CH1OPTS_SET;
9022  __IO uint32_t CH1OPTS_CLR;
9023  __IO uint32_t CH1OPTS_TOG;
9024  __IO uint32_t CH2CMDPTR;
9025  uint8_t RESERVED_16[12];
9026  __IO uint32_t CH2SEMA;
9027  uint8_t RESERVED_17[12];
9028  __IO uint32_t CH2STAT;
9029  __IO uint32_t CH2STAT_SET;
9030  __IO uint32_t CH2STAT_CLR;
9031  __IO uint32_t CH2STAT_TOG;
9032  __IO uint32_t CH2OPTS;
9033  __IO uint32_t CH2OPTS_SET;
9034  __IO uint32_t CH2OPTS_CLR;
9035  __IO uint32_t CH2OPTS_TOG;
9036  __IO uint32_t CH3CMDPTR;
9037  uint8_t RESERVED_18[12];
9038  __IO uint32_t CH3SEMA;
9039  uint8_t RESERVED_19[12];
9040  __IO uint32_t CH3STAT;
9041  __IO uint32_t CH3STAT_SET;
9042  __IO uint32_t CH3STAT_CLR;
9043  __IO uint32_t CH3STAT_TOG;
9044  __IO uint32_t CH3OPTS;
9045  __IO uint32_t CH3OPTS_SET;
9046  __IO uint32_t CH3OPTS_CLR;
9047  __IO uint32_t CH3OPTS_TOG;
9048  uint8_t RESERVED_20[512];
9049  __IO uint32_t DBGSELECT;
9050  uint8_t RESERVED_21[12];
9051  __I uint32_t DBGDATA;
9052  uint8_t RESERVED_22[12];
9053  __IO uint32_t PAGETABLE;
9054  uint8_t RESERVED_23[12];
9055  __I uint32_t VERSION;
9056 } DCP_Type;
9057 
9058 /* ----------------------------------------------------------------------------
9059  -- DCP Register Masks
9060  ---------------------------------------------------------------------------- */
9061 
9069 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
9070 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
9077 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
9078 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
9079 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
9080 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
9081 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
9082 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
9083 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
9084 #define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
9085 #define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
9086 #define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
9087 #define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
9088 #define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
9089 #define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
9090 #define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
9091 #define DCP_CTRL_PRESENT_SHA_SHIFT (28U)
9096 #define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
9097 #define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
9098 #define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
9103 #define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
9104 #define DCP_CTRL_CLKGATE_MASK (0x40000000U)
9105 #define DCP_CTRL_CLKGATE_SHIFT (30U)
9106 #define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
9107 #define DCP_CTRL_SFTRST_MASK (0x80000000U)
9108 #define DCP_CTRL_SFTRST_SHIFT (31U)
9109 #define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
9114 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
9115 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
9122 #define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
9123 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
9124 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
9125 #define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
9126 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
9127 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
9128 #define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
9129 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
9130 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
9131 #define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
9132 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
9133 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
9134 #define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
9135 #define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U)
9136 #define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U)
9141 #define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
9142 #define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U)
9143 #define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U)
9148 #define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
9149 #define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U)
9150 #define DCP_CTRL_SET_CLKGATE_SHIFT (30U)
9151 #define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
9152 #define DCP_CTRL_SET_SFTRST_MASK (0x80000000U)
9153 #define DCP_CTRL_SET_SFTRST_SHIFT (31U)
9154 #define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
9159 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
9160 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
9167 #define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
9168 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
9169 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
9170 #define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
9171 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
9172 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
9173 #define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
9174 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
9175 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
9176 #define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
9177 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
9178 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
9179 #define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
9180 #define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U)
9181 #define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U)
9186 #define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
9187 #define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U)
9188 #define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U)
9193 #define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
9194 #define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
9195 #define DCP_CTRL_CLR_CLKGATE_SHIFT (30U)
9196 #define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
9197 #define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U)
9198 #define DCP_CTRL_CLR_SFTRST_SHIFT (31U)
9199 #define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
9204 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
9205 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
9212 #define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
9213 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
9214 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
9215 #define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
9216 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
9217 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
9218 #define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
9219 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
9220 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
9221 #define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
9222 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
9223 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
9224 #define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
9225 #define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U)
9226 #define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U)
9231 #define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
9232 #define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U)
9233 #define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U)
9238 #define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
9239 #define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
9240 #define DCP_CTRL_TOG_CLKGATE_SHIFT (30U)
9241 #define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
9242 #define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U)
9243 #define DCP_CTRL_TOG_SFTRST_SHIFT (31U)
9244 #define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
9249 #define DCP_STAT_IRQ_MASK (0xFU)
9250 #define DCP_STAT_IRQ_SHIFT (0U)
9251 #define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
9252 #define DCP_STAT_RSVD_IRQ_MASK (0x100U)
9253 #define DCP_STAT_RSVD_IRQ_SHIFT (8U)
9254 #define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
9255 #define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
9256 #define DCP_STAT_READY_CHANNELS_SHIFT (16U)
9263 #define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
9264 #define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
9265 #define DCP_STAT_CUR_CHANNEL_SHIFT (24U)
9273 #define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
9274 #define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
9275 #define DCP_STAT_OTP_KEY_READY_SHIFT (28U)
9276 #define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
9281 #define DCP_STAT_SET_IRQ_MASK (0xFU)
9282 #define DCP_STAT_SET_IRQ_SHIFT (0U)
9283 #define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
9284 #define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U)
9285 #define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U)
9286 #define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
9287 #define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U)
9288 #define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U)
9295 #define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
9296 #define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U)
9297 #define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U)
9305 #define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
9306 #define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U)
9307 #define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U)
9308 #define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
9313 #define DCP_STAT_CLR_IRQ_MASK (0xFU)
9314 #define DCP_STAT_CLR_IRQ_SHIFT (0U)
9315 #define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
9316 #define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U)
9317 #define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U)
9318 #define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
9319 #define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U)
9320 #define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U)
9327 #define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
9328 #define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U)
9329 #define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U)
9337 #define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
9338 #define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U)
9339 #define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U)
9340 #define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
9345 #define DCP_STAT_TOG_IRQ_MASK (0xFU)
9346 #define DCP_STAT_TOG_IRQ_SHIFT (0U)
9347 #define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
9348 #define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U)
9349 #define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U)
9350 #define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
9351 #define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U)
9352 #define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U)
9359 #define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
9360 #define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U)
9361 #define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U)
9369 #define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
9370 #define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U)
9371 #define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U)
9372 #define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
9377 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
9378 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
9385 #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
9386 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
9387 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
9394 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
9395 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
9396 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
9397 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
9398 #define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
9399 #define DCP_CHANNELCTRL_RSVD_SHIFT (17U)
9400 #define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
9405 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU)
9406 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
9413 #define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
9414 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
9415 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
9422 #define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
9423 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U)
9424 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
9425 #define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
9426 #define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U)
9427 #define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U)
9428 #define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
9433 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU)
9434 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
9441 #define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
9442 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
9443 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
9450 #define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
9451 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U)
9452 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
9453 #define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
9454 #define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U)
9455 #define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U)
9456 #define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
9461 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU)
9462 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
9469 #define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
9470 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
9471 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
9478 #define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
9479 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U)
9480 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
9481 #define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
9482 #define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U)
9483 #define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U)
9484 #define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
9489 #define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
9490 #define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
9491 #define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
9492 #define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
9493 #define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
9494 #define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
9495 #define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
9496 #define DCP_CAPABILITY0_RSVD_SHIFT (12U)
9497 #define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
9498 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
9499 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
9500 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
9501 #define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
9502 #define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
9503 #define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
9508 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
9509 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
9513 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
9514 #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
9515 #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
9521 #define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
9526 #define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
9527 #define DCP_CONTEXT_ADDR_SHIFT (0U)
9528 #define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
9533 #define DCP_KEY_SUBWORD_MASK (0x3U)
9534 #define DCP_KEY_SUBWORD_SHIFT (0U)
9535 #define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
9536 #define DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
9537 #define DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
9538 #define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
9539 #define DCP_KEY_INDEX_MASK (0x30U)
9540 #define DCP_KEY_INDEX_SHIFT (4U)
9541 #define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
9542 #define DCP_KEY_RSVD_INDEX_MASK (0xC0U)
9543 #define DCP_KEY_RSVD_INDEX_SHIFT (6U)
9544 #define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
9545 #define DCP_KEY_RSVD_MASK (0xFFFFFF00U)
9546 #define DCP_KEY_RSVD_SHIFT (8U)
9547 #define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
9552 #define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
9553 #define DCP_KEYDATA_DATA_SHIFT (0U)
9554 #define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
9559 #define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
9560 #define DCP_PACKET0_ADDR_SHIFT (0U)
9561 #define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
9566 #define DCP_PACKET1_INTERRUPT_MASK (0x1U)
9567 #define DCP_PACKET1_INTERRUPT_SHIFT (0U)
9568 #define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
9569 #define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
9570 #define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
9571 #define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
9572 #define DCP_PACKET1_CHAIN_MASK (0x4U)
9573 #define DCP_PACKET1_CHAIN_SHIFT (2U)
9574 #define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
9575 #define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
9576 #define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
9577 #define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
9578 #define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
9579 #define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
9580 #define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
9581 #define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
9582 #define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
9583 #define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
9584 #define DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
9585 #define DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
9586 #define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
9587 #define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
9588 #define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
9589 #define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
9590 #define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
9591 #define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
9596 #define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
9597 #define DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
9598 #define DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
9599 #define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
9600 #define DCP_PACKET1_OTP_KEY_MASK (0x400U)
9601 #define DCP_PACKET1_OTP_KEY_SHIFT (10U)
9602 #define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
9603 #define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
9604 #define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
9605 #define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
9606 #define DCP_PACKET1_HASH_INIT_MASK (0x1000U)
9607 #define DCP_PACKET1_HASH_INIT_SHIFT (12U)
9608 #define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
9609 #define DCP_PACKET1_HASH_TERM_MASK (0x2000U)
9610 #define DCP_PACKET1_HASH_TERM_SHIFT (13U)
9611 #define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
9612 #define DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
9613 #define DCP_PACKET1_CHECK_HASH_SHIFT (14U)
9614 #define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
9615 #define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
9616 #define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
9621 #define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
9622 #define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
9623 #define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
9624 #define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
9625 #define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
9626 #define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
9627 #define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
9628 #define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
9629 #define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
9630 #define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
9631 #define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
9632 #define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
9633 #define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
9634 #define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
9635 #define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
9636 #define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
9637 #define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
9638 #define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
9639 #define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
9640 #define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
9641 #define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
9642 #define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
9643 #define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
9644 #define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
9645 #define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
9646 #define DCP_PACKET1_TAG_MASK (0xFF000000U)
9647 #define DCP_PACKET1_TAG_SHIFT (24U)
9648 #define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
9653 #define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
9654 #define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
9658 #define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
9659 #define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
9660 #define DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
9665 #define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
9666 #define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
9667 #define DCP_PACKET2_KEY_SELECT_SHIFT (8U)
9676 #define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
9677 #define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
9678 #define DCP_PACKET2_HASH_SELECT_SHIFT (16U)
9684 #define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
9685 #define DCP_PACKET2_RSVD_MASK (0xF00000U)
9686 #define DCP_PACKET2_RSVD_SHIFT (20U)
9687 #define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
9688 #define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
9689 #define DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
9690 #define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
9695 #define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
9696 #define DCP_PACKET3_ADDR_SHIFT (0U)
9697 #define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
9702 #define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
9703 #define DCP_PACKET4_ADDR_SHIFT (0U)
9704 #define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
9709 #define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
9710 #define DCP_PACKET5_COUNT_SHIFT (0U)
9711 #define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
9716 #define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
9717 #define DCP_PACKET6_ADDR_SHIFT (0U)
9718 #define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
9723 #define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
9724 #define DCP_CH0CMDPTR_ADDR_SHIFT (0U)
9725 #define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
9730 #define DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
9731 #define DCP_CH0SEMA_INCREMENT_SHIFT (0U)
9732 #define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
9733 #define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
9734 #define DCP_CH0SEMA_VALUE_SHIFT (16U)
9735 #define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
9740 #define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
9741 #define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
9742 #define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
9743 #define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
9744 #define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
9745 #define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
9746 #define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
9747 #define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
9748 #define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
9749 #define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
9750 #define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
9751 #define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
9752 #define DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
9753 #define DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
9754 #define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
9755 #define DCP_CH0STAT_ERROR_DST_MASK (0x20U)
9756 #define DCP_CH0STAT_ERROR_DST_SHIFT (5U)
9757 #define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
9758 #define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
9759 #define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
9760 #define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
9761 #define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
9762 #define DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
9770 #define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
9771 #define DCP_CH0STAT_TAG_MASK (0xFF000000U)
9772 #define DCP_CH0STAT_TAG_SHIFT (24U)
9773 #define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
9778 #define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U)
9779 #define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U)
9780 #define DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
9781 #define DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U)
9782 #define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U)
9783 #define DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
9784 #define DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U)
9785 #define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U)
9786 #define DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
9787 #define DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U)
9788 #define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U)
9789 #define DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
9790 #define DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U)
9791 #define DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U)
9792 #define DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
9793 #define DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U)
9794 #define DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U)
9795 #define DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
9796 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
9797 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
9798 #define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
9799 #define DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U)
9800 #define DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U)
9808 #define DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
9809 #define DCP_CH0STAT_SET_TAG_MASK (0xFF000000U)
9810 #define DCP_CH0STAT_SET_TAG_SHIFT (24U)
9811 #define DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
9816 #define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
9817 #define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
9818 #define DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
9819 #define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U)
9820 #define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U)
9821 #define DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
9822 #define DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U)
9823 #define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U)
9824 #define DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
9825 #define DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U)
9826 #define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U)
9827 #define DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
9828 #define DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U)
9829 #define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U)
9830 #define DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
9831 #define DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U)
9832 #define DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U)
9833 #define DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
9834 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
9835 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
9836 #define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
9837 #define DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
9838 #define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U)
9846 #define DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
9847 #define DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U)
9848 #define DCP_CH0STAT_CLR_TAG_SHIFT (24U)
9849 #define DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
9854 #define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
9855 #define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
9856 #define DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
9857 #define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U)
9858 #define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U)
9859 #define DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
9860 #define DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U)
9861 #define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U)
9862 #define DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
9863 #define DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U)
9864 #define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U)
9865 #define DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
9866 #define DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U)
9867 #define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U)
9868 #define DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
9869 #define DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U)
9870 #define DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U)
9871 #define DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
9872 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
9873 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
9874 #define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
9875 #define DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
9876 #define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U)
9884 #define DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
9885 #define DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U)
9886 #define DCP_CH0STAT_TOG_TAG_SHIFT (24U)
9887 #define DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
9892 #define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
9893 #define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
9894 #define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
9895 #define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
9896 #define DCP_CH0OPTS_RSVD_SHIFT (16U)
9897 #define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
9902 #define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
9903 #define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
9904 #define DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
9905 #define DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U)
9906 #define DCP_CH0OPTS_SET_RSVD_SHIFT (16U)
9907 #define DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
9912 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
9913 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
9914 #define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
9915 #define DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U)
9916 #define DCP_CH0OPTS_CLR_RSVD_SHIFT (16U)
9917 #define DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
9922 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
9923 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
9924 #define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
9925 #define DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U)
9926 #define DCP_CH0OPTS_TOG_RSVD_SHIFT (16U)
9927 #define DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
9932 #define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
9933 #define DCP_CH1CMDPTR_ADDR_SHIFT (0U)
9934 #define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
9939 #define DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
9940 #define DCP_CH1SEMA_INCREMENT_SHIFT (0U)
9941 #define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
9942 #define DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
9943 #define DCP_CH1SEMA_VALUE_SHIFT (16U)
9944 #define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
9949 #define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
9950 #define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
9951 #define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
9952 #define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
9953 #define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
9954 #define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
9955 #define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
9956 #define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
9957 #define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
9958 #define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
9959 #define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
9960 #define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
9961 #define DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
9962 #define DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
9963 #define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
9964 #define DCP_CH1STAT_ERROR_DST_MASK (0x20U)
9965 #define DCP_CH1STAT_ERROR_DST_SHIFT (5U)
9966 #define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
9967 #define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
9968 #define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
9969 #define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
9970 #define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
9971 #define DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
9979 #define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
9980 #define DCP_CH1STAT_TAG_MASK (0xFF000000U)
9981 #define DCP_CH1STAT_TAG_SHIFT (24U)
9982 #define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
9987 #define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U)
9988 #define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U)
9989 #define DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
9990 #define DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U)
9991 #define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U)
9992 #define DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
9993 #define DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U)
9994 #define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U)
9995 #define DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
9996 #define DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U)
9997 #define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U)
9998 #define DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
9999 #define DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U)
10000 #define DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U)
10001 #define DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
10002 #define DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U)
10003 #define DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U)
10004 #define DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
10005 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
10006 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
10007 #define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
10008 #define DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U)
10009 #define DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U)
10017 #define DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
10018 #define DCP_CH1STAT_SET_TAG_MASK (0xFF000000U)
10019 #define DCP_CH1STAT_SET_TAG_SHIFT (24U)
10020 #define DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
10025 #define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
10026 #define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
10027 #define DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
10028 #define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U)
10029 #define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U)
10030 #define DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
10031 #define DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U)
10032 #define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U)
10033 #define DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
10034 #define DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U)
10035 #define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U)
10036 #define DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
10037 #define DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U)
10038 #define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U)
10039 #define DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
10040 #define DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U)
10041 #define DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U)
10042 #define DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
10043 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
10044 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
10045 #define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
10046 #define DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
10047 #define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U)
10055 #define DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
10056 #define DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U)
10057 #define DCP_CH1STAT_CLR_TAG_SHIFT (24U)
10058 #define DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
10063 #define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
10064 #define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
10065 #define DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
10066 #define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U)
10067 #define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U)
10068 #define DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
10069 #define DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U)
10070 #define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U)
10071 #define DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
10072 #define DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U)
10073 #define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U)
10074 #define DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
10075 #define DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U)
10076 #define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U)
10077 #define DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
10078 #define DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U)
10079 #define DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U)
10080 #define DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
10081 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
10082 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
10083 #define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
10084 #define DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
10085 #define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U)
10093 #define DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
10094 #define DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U)
10095 #define DCP_CH1STAT_TOG_TAG_SHIFT (24U)
10096 #define DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
10101 #define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
10102 #define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
10103 #define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
10104 #define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
10105 #define DCP_CH1OPTS_RSVD_SHIFT (16U)
10106 #define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
10111 #define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
10112 #define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
10113 #define DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
10114 #define DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U)
10115 #define DCP_CH1OPTS_SET_RSVD_SHIFT (16U)
10116 #define DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
10121 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
10122 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
10123 #define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
10124 #define DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U)
10125 #define DCP_CH1OPTS_CLR_RSVD_SHIFT (16U)
10126 #define DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
10131 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
10132 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
10133 #define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
10134 #define DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U)
10135 #define DCP_CH1OPTS_TOG_RSVD_SHIFT (16U)
10136 #define DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
10141 #define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
10142 #define DCP_CH2CMDPTR_ADDR_SHIFT (0U)
10143 #define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
10148 #define DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
10149 #define DCP_CH2SEMA_INCREMENT_SHIFT (0U)
10150 #define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
10151 #define DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
10152 #define DCP_CH2SEMA_VALUE_SHIFT (16U)
10153 #define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
10158 #define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
10159 #define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
10160 #define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
10161 #define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
10162 #define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
10163 #define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
10164 #define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
10165 #define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
10166 #define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
10167 #define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
10168 #define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
10169 #define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
10170 #define DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
10171 #define DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
10172 #define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
10173 #define DCP_CH2STAT_ERROR_DST_MASK (0x20U)
10174 #define DCP_CH2STAT_ERROR_DST_SHIFT (5U)
10175 #define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
10176 #define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
10177 #define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
10178 #define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
10179 #define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
10180 #define DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
10188 #define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
10189 #define DCP_CH2STAT_TAG_MASK (0xFF000000U)
10190 #define DCP_CH2STAT_TAG_SHIFT (24U)
10191 #define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
10196 #define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U)
10197 #define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U)
10198 #define DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
10199 #define DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U)
10200 #define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U)
10201 #define DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
10202 #define DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U)
10203 #define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U)
10204 #define DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
10205 #define DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U)
10206 #define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U)
10207 #define DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
10208 #define DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U)
10209 #define DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U)
10210 #define DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
10211 #define DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U)
10212 #define DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U)
10213 #define DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
10214 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
10215 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
10216 #define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
10217 #define DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U)
10218 #define DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U)
10226 #define DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
10227 #define DCP_CH2STAT_SET_TAG_MASK (0xFF000000U)
10228 #define DCP_CH2STAT_SET_TAG_SHIFT (24U)
10229 #define DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
10234 #define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
10235 #define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
10236 #define DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
10237 #define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U)
10238 #define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U)
10239 #define DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
10240 #define DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U)
10241 #define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U)
10242 #define DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
10243 #define DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U)
10244 #define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U)
10245 #define DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
10246 #define DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U)
10247 #define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U)
10248 #define DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
10249 #define DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U)
10250 #define DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U)
10251 #define DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
10252 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
10253 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
10254 #define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
10255 #define DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
10256 #define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U)
10264 #define DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
10265 #define DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U)
10266 #define DCP_CH2STAT_CLR_TAG_SHIFT (24U)
10267 #define DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
10272 #define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
10273 #define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
10274 #define DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
10275 #define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U)
10276 #define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U)
10277 #define DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
10278 #define DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U)
10279 #define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U)
10280 #define DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
10281 #define DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U)
10282 #define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U)
10283 #define DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
10284 #define DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U)
10285 #define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U)
10286 #define DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
10287 #define DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U)
10288 #define DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U)
10289 #define DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
10290 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
10291 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
10292 #define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
10293 #define DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
10294 #define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U)
10302 #define DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
10303 #define DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U)
10304 #define DCP_CH2STAT_TOG_TAG_SHIFT (24U)
10305 #define DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
10310 #define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
10311 #define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
10312 #define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
10313 #define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
10314 #define DCP_CH2OPTS_RSVD_SHIFT (16U)
10315 #define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
10320 #define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
10321 #define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
10322 #define DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
10323 #define DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U)
10324 #define DCP_CH2OPTS_SET_RSVD_SHIFT (16U)
10325 #define DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
10330 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
10331 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
10332 #define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
10333 #define DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U)
10334 #define DCP_CH2OPTS_CLR_RSVD_SHIFT (16U)
10335 #define DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
10340 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
10341 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
10342 #define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
10343 #define DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U)
10344 #define DCP_CH2OPTS_TOG_RSVD_SHIFT (16U)
10345 #define DCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)
10350 #define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)
10351 #define DCP_CH3CMDPTR_ADDR_SHIFT (0U)
10352 #define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
10357 #define DCP_CH3SEMA_INCREMENT_MASK (0xFFU)
10358 #define DCP_CH3SEMA_INCREMENT_SHIFT (0U)
10359 #define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
10360 #define DCP_CH3SEMA_VALUE_MASK (0xFF0000U)
10361 #define DCP_CH3SEMA_VALUE_SHIFT (16U)
10362 #define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
10367 #define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)
10368 #define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)
10369 #define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
10370 #define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)
10371 #define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)
10372 #define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
10373 #define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)
10374 #define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)
10375 #define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
10376 #define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)
10377 #define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)
10378 #define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
10379 #define DCP_CH3STAT_ERROR_SRC_MASK (0x10U)
10380 #define DCP_CH3STAT_ERROR_SRC_SHIFT (4U)
10381 #define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
10382 #define DCP_CH3STAT_ERROR_DST_MASK (0x20U)
10383 #define DCP_CH3STAT_ERROR_DST_SHIFT (5U)
10384 #define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
10385 #define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)
10386 #define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)
10387 #define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
10388 #define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)
10389 #define DCP_CH3STAT_ERROR_CODE_SHIFT (16U)
10397 #define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
10398 #define DCP_CH3STAT_TAG_MASK (0xFF000000U)
10399 #define DCP_CH3STAT_TAG_SHIFT (24U)
10400 #define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
10405 #define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U)
10406 #define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U)
10407 #define DCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)
10408 #define DCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U)
10409 #define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U)
10410 #define DCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)
10411 #define DCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U)
10412 #define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U)
10413 #define DCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)
10414 #define DCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U)
10415 #define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U)
10416 #define DCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)
10417 #define DCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U)
10418 #define DCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U)
10419 #define DCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)
10420 #define DCP_CH3STAT_SET_ERROR_DST_MASK (0x20U)
10421 #define DCP_CH3STAT_SET_ERROR_DST_SHIFT (5U)
10422 #define DCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)
10423 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
10424 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
10425 #define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)
10426 #define DCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U)
10427 #define DCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U)
10435 #define DCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)
10436 #define DCP_CH3STAT_SET_TAG_MASK (0xFF000000U)
10437 #define DCP_CH3STAT_SET_TAG_SHIFT (24U)
10438 #define DCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)
10443 #define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
10444 #define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
10445 #define DCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)
10446 #define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U)
10447 #define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U)
10448 #define DCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)
10449 #define DCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U)
10450 #define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U)
10451 #define DCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)
10452 #define DCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U)
10453 #define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U)
10454 #define DCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)
10455 #define DCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U)
10456 #define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U)
10457 #define DCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)
10458 #define DCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U)
10459 #define DCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U)
10460 #define DCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)
10461 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
10462 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
10463 #define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)
10464 #define DCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
10465 #define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U)
10473 #define DCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)
10474 #define DCP_CH3STAT_CLR_TAG_MASK (0xFF000000U)
10475 #define DCP_CH3STAT_CLR_TAG_SHIFT (24U)
10476 #define DCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)
10481 #define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
10482 #define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
10483 #define DCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)
10484 #define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U)
10485 #define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U)
10486 #define DCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)
10487 #define DCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U)
10488 #define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U)
10489 #define DCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)
10490 #define DCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U)
10491 #define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U)
10492 #define DCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)
10493 #define DCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U)
10494 #define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U)
10495 #define DCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)
10496 #define DCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U)
10497 #define DCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U)
10498 #define DCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)
10499 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
10500 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
10501 #define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)
10502 #define DCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
10503 #define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U)
10511 #define DCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)
10512 #define DCP_CH3STAT_TOG_TAG_MASK (0xFF000000U)
10513 #define DCP_CH3STAT_TOG_TAG_SHIFT (24U)
10514 #define DCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)
10519 #define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
10520 #define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)
10521 #define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
10522 #define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)
10523 #define DCP_CH3OPTS_RSVD_SHIFT (16U)
10524 #define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
10529 #define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
10530 #define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
10531 #define DCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)
10532 #define DCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U)
10533 #define DCP_CH3OPTS_SET_RSVD_SHIFT (16U)
10534 #define DCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)
10539 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
10540 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
10541 #define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)
10542 #define DCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U)
10543 #define DCP_CH3OPTS_CLR_RSVD_SHIFT (16U)
10544 #define DCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)
10549 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
10550 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
10551 #define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)
10552 #define DCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U)
10553 #define DCP_CH3OPTS_TOG_RSVD_SHIFT (16U)
10554 #define DCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)
10559 #define DCP_DBGSELECT_INDEX_MASK (0xFFU)
10560 #define DCP_DBGSELECT_INDEX_SHIFT (0U)
10568 #define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
10569 #define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)
10570 #define DCP_DBGSELECT_RSVD_SHIFT (8U)
10571 #define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
10576 #define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)
10577 #define DCP_DBGDATA_DATA_SHIFT (0U)
10578 #define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
10583 #define DCP_PAGETABLE_ENABLE_MASK (0x1U)
10584 #define DCP_PAGETABLE_ENABLE_SHIFT (0U)
10585 #define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
10586 #define DCP_PAGETABLE_FLUSH_MASK (0x2U)
10587 #define DCP_PAGETABLE_FLUSH_SHIFT (1U)
10588 #define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
10589 #define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)
10590 #define DCP_PAGETABLE_BASE_SHIFT (2U)
10591 #define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
10596 #define DCP_VERSION_STEP_MASK (0xFFFFU)
10597 #define DCP_VERSION_STEP_SHIFT (0U)
10598 #define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
10599 #define DCP_VERSION_MINOR_MASK (0xFF0000U)
10600 #define DCP_VERSION_MINOR_SHIFT (16U)
10601 #define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
10602 #define DCP_VERSION_MAJOR_MASK (0xFF000000U)
10603 #define DCP_VERSION_MAJOR_SHIFT (24U)
10604 #define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) /* end of group DCP_Register_Masks */
10611 
10612 
10613 /* DCP - Peripheral instance base addresses */
10615 #define DCP_BASE (0x402FC000u)
10617 #define DCP ((DCP_Type *)DCP_BASE)
10619 #define DCP_BASE_ADDRS { DCP_BASE }
10621 #define DCP_BASE_PTRS { DCP }
10623 #define DCP_IRQS { DCP_IRQn }
10624 #define DCP_VMI_IRQS { DCP_VMI_IRQn }
10625  /* end of group DCP_Peripheral_Access_Layer */
10629 
10630 
10631 /* ----------------------------------------------------------------------------
10632  -- DMA Peripheral Access Layer
10633  ---------------------------------------------------------------------------- */
10634 
10641 typedef struct {
10642  __IO uint32_t CR;
10643  __I uint32_t ES;
10644  uint8_t RESERVED_0[4];
10645  __IO uint32_t ERQ;
10646  uint8_t RESERVED_1[4];
10647  __IO uint32_t EEI;
10648  __O uint8_t CEEI;
10649  __O uint8_t SEEI;
10650  __O uint8_t CERQ;
10651  __O uint8_t SERQ;
10652  __O uint8_t CDNE;
10653  __O uint8_t SSRT;
10654  __O uint8_t CERR;
10655  __O uint8_t CINT;
10656  uint8_t RESERVED_2[4];
10657  __IO uint32_t INT;
10658  uint8_t RESERVED_3[4];
10659  __IO uint32_t ERR;
10660  uint8_t RESERVED_4[4];
10661  __I uint32_t HRS;
10662  uint8_t RESERVED_5[12];
10663  __IO uint32_t EARS;
10664  uint8_t RESERVED_6[184];
10665  __IO uint8_t DCHPRI3;
10666  __IO uint8_t DCHPRI2;
10667  __IO uint8_t DCHPRI1;
10668  __IO uint8_t DCHPRI0;
10669  __IO uint8_t DCHPRI7;
10670  __IO uint8_t DCHPRI6;
10671  __IO uint8_t DCHPRI5;
10672  __IO uint8_t DCHPRI4;
10673  __IO uint8_t DCHPRI11;
10674  __IO uint8_t DCHPRI10;
10675  __IO uint8_t DCHPRI9;
10676  __IO uint8_t DCHPRI8;
10677  __IO uint8_t DCHPRI15;
10678  __IO uint8_t DCHPRI14;
10679  __IO uint8_t DCHPRI13;
10680  __IO uint8_t DCHPRI12;
10681  __IO uint8_t DCHPRI19;
10682  __IO uint8_t DCHPRI18;
10683  __IO uint8_t DCHPRI17;
10684  __IO uint8_t DCHPRI16;
10685  __IO uint8_t DCHPRI23;
10686  __IO uint8_t DCHPRI22;
10687  __IO uint8_t DCHPRI21;
10688  __IO uint8_t DCHPRI20;
10689  __IO uint8_t DCHPRI27;
10690  __IO uint8_t DCHPRI26;
10691  __IO uint8_t DCHPRI25;
10692  __IO uint8_t DCHPRI24;
10693  __IO uint8_t DCHPRI31;
10694  __IO uint8_t DCHPRI30;
10695  __IO uint8_t DCHPRI29;
10696  __IO uint8_t DCHPRI28;
10697  uint8_t RESERVED_7[3808];
10698  struct { /* offset: 0x1000, array step: 0x20 */
10699  __IO uint32_t SADDR;
10700  __IO uint16_t SOFF;
10701  __IO uint16_t ATTR;
10702  union { /* offset: 0x1008, array step: 0x20 */
10703  __IO uint32_t NBYTES_MLNO;
10704  __IO uint32_t NBYTES_MLOFFNO;
10705  __IO uint32_t NBYTES_MLOFFYES;
10706  };
10707  __IO int32_t SLAST;
10708  __IO uint32_t DADDR;
10709  __IO uint16_t DOFF;
10710  union { /* offset: 0x1016, array step: 0x20 */
10711  __IO uint16_t CITER_ELINKNO;
10712  __IO uint16_t CITER_ELINKYES;
10713  };
10714  __IO int32_t DLAST_SGA;
10715  __IO uint16_t CSR;
10716  union { /* offset: 0x101E, array step: 0x20 */
10717  __IO uint16_t BITER_ELINKNO;
10718  __IO uint16_t BITER_ELINKYES;
10719  };
10720  } TCD[32];
10721 } DMA_Type;
10722 
10723 /* ----------------------------------------------------------------------------
10724  -- DMA Register Masks
10725  ---------------------------------------------------------------------------- */
10726 
10734 #define DMA_CR_EDBG_MASK (0x2U)
10735 #define DMA_CR_EDBG_SHIFT (1U)
10740 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
10741 #define DMA_CR_ERCA_MASK (0x4U)
10742 #define DMA_CR_ERCA_SHIFT (2U)
10747 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
10748 #define DMA_CR_ERGA_MASK (0x8U)
10749 #define DMA_CR_ERGA_SHIFT (3U)
10754 #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
10755 #define DMA_CR_HOE_MASK (0x10U)
10756 #define DMA_CR_HOE_SHIFT (4U)
10761 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
10762 #define DMA_CR_HALT_MASK (0x20U)
10763 #define DMA_CR_HALT_SHIFT (5U)
10768 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
10769 #define DMA_CR_CLM_MASK (0x40U)
10770 #define DMA_CR_CLM_SHIFT (6U)
10775 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
10776 #define DMA_CR_EMLM_MASK (0x80U)
10777 #define DMA_CR_EMLM_SHIFT (7U)
10782 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
10783 #define DMA_CR_GRP0PRI_MASK (0x100U)
10784 #define DMA_CR_GRP0PRI_SHIFT (8U)
10787 #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
10788 #define DMA_CR_GRP1PRI_MASK (0x400U)
10789 #define DMA_CR_GRP1PRI_SHIFT (10U)
10792 #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
10793 #define DMA_CR_ECX_MASK (0x10000U)
10794 #define DMA_CR_ECX_SHIFT (16U)
10799 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
10800 #define DMA_CR_CX_MASK (0x20000U)
10801 #define DMA_CR_CX_SHIFT (17U)
10806 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
10807 #define DMA_CR_VERSION_MASK (0x7F000000U)
10808 #define DMA_CR_VERSION_SHIFT (24U)
10811 #define DMA_CR_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)
10812 #define DMA_CR_ACTIVE_MASK (0x80000000U)
10813 #define DMA_CR_ACTIVE_SHIFT (31U)
10818 #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
10823 #define DMA_ES_DBE_MASK (0x1U)
10824 #define DMA_ES_DBE_SHIFT (0U)
10829 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
10830 #define DMA_ES_SBE_MASK (0x2U)
10831 #define DMA_ES_SBE_SHIFT (1U)
10836 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
10837 #define DMA_ES_SGE_MASK (0x4U)
10838 #define DMA_ES_SGE_SHIFT (2U)
10843 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
10844 #define DMA_ES_NCE_MASK (0x8U)
10845 #define DMA_ES_NCE_SHIFT (3U)
10852 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
10853 #define DMA_ES_DOE_MASK (0x10U)
10854 #define DMA_ES_DOE_SHIFT (4U)
10859 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
10860 #define DMA_ES_DAE_MASK (0x20U)
10861 #define DMA_ES_DAE_SHIFT (5U)
10867 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
10868 #define DMA_ES_SOE_MASK (0x40U)
10869 #define DMA_ES_SOE_SHIFT (6U)
10874 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
10875 #define DMA_ES_SAE_MASK (0x80U)
10876 #define DMA_ES_SAE_SHIFT (7U)
10882 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
10883 #define DMA_ES_ERRCHN_MASK (0x1F00U)
10884 #define DMA_ES_ERRCHN_SHIFT (8U)
10887 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
10888 #define DMA_ES_CPE_MASK (0x4000U)
10889 #define DMA_ES_CPE_SHIFT (14U)
10895 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
10896 #define DMA_ES_GPE_MASK (0x8000U)
10897 #define DMA_ES_GPE_SHIFT (15U)
10902 #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
10903 #define DMA_ES_ECX_MASK (0x10000U)
10904 #define DMA_ES_ECX_SHIFT (16U)
10909 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
10910 #define DMA_ES_VLD_MASK (0x80000000U)
10911 #define DMA_ES_VLD_SHIFT (31U)
10916 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
10921 #define DMA_ERQ_ERQ0_MASK (0x1U)
10922 #define DMA_ERQ_ERQ0_SHIFT (0U)
10927 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
10928 #define DMA_ERQ_ERQ1_MASK (0x2U)
10929 #define DMA_ERQ_ERQ1_SHIFT (1U)
10934 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
10935 #define DMA_ERQ_ERQ2_MASK (0x4U)
10936 #define DMA_ERQ_ERQ2_SHIFT (2U)
10941 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
10942 #define DMA_ERQ_ERQ3_MASK (0x8U)
10943 #define DMA_ERQ_ERQ3_SHIFT (3U)
10948 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
10949 #define DMA_ERQ_ERQ4_MASK (0x10U)
10950 #define DMA_ERQ_ERQ4_SHIFT (4U)
10955 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
10956 #define DMA_ERQ_ERQ5_MASK (0x20U)
10957 #define DMA_ERQ_ERQ5_SHIFT (5U)
10962 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
10963 #define DMA_ERQ_ERQ6_MASK (0x40U)
10964 #define DMA_ERQ_ERQ6_SHIFT (6U)
10969 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
10970 #define DMA_ERQ_ERQ7_MASK (0x80U)
10971 #define DMA_ERQ_ERQ7_SHIFT (7U)
10976 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
10977 #define DMA_ERQ_ERQ8_MASK (0x100U)
10978 #define DMA_ERQ_ERQ8_SHIFT (8U)
10983 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
10984 #define DMA_ERQ_ERQ9_MASK (0x200U)
10985 #define DMA_ERQ_ERQ9_SHIFT (9U)
10990 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
10991 #define DMA_ERQ_ERQ10_MASK (0x400U)
10992 #define DMA_ERQ_ERQ10_SHIFT (10U)
10997 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
10998 #define DMA_ERQ_ERQ11_MASK (0x800U)
10999 #define DMA_ERQ_ERQ11_SHIFT (11U)
11004 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
11005 #define DMA_ERQ_ERQ12_MASK (0x1000U)
11006 #define DMA_ERQ_ERQ12_SHIFT (12U)
11011 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
11012 #define DMA_ERQ_ERQ13_MASK (0x2000U)
11013 #define DMA_ERQ_ERQ13_SHIFT (13U)
11018 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
11019 #define DMA_ERQ_ERQ14_MASK (0x4000U)
11020 #define DMA_ERQ_ERQ14_SHIFT (14U)
11025 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
11026 #define DMA_ERQ_ERQ15_MASK (0x8000U)
11027 #define DMA_ERQ_ERQ15_SHIFT (15U)
11032 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
11033 #define DMA_ERQ_ERQ16_MASK (0x10000U)
11034 #define DMA_ERQ_ERQ16_SHIFT (16U)
11039 #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
11040 #define DMA_ERQ_ERQ17_MASK (0x20000U)
11041 #define DMA_ERQ_ERQ17_SHIFT (17U)
11046 #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
11047 #define DMA_ERQ_ERQ18_MASK (0x40000U)
11048 #define DMA_ERQ_ERQ18_SHIFT (18U)
11053 #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
11054 #define DMA_ERQ_ERQ19_MASK (0x80000U)
11055 #define DMA_ERQ_ERQ19_SHIFT (19U)
11060 #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
11061 #define DMA_ERQ_ERQ20_MASK (0x100000U)
11062 #define DMA_ERQ_ERQ20_SHIFT (20U)
11067 #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
11068 #define DMA_ERQ_ERQ21_MASK (0x200000U)
11069 #define DMA_ERQ_ERQ21_SHIFT (21U)
11074 #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
11075 #define DMA_ERQ_ERQ22_MASK (0x400000U)
11076 #define DMA_ERQ_ERQ22_SHIFT (22U)
11081 #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
11082 #define DMA_ERQ_ERQ23_MASK (0x800000U)
11083 #define DMA_ERQ_ERQ23_SHIFT (23U)
11088 #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
11089 #define DMA_ERQ_ERQ24_MASK (0x1000000U)
11090 #define DMA_ERQ_ERQ24_SHIFT (24U)
11095 #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
11096 #define DMA_ERQ_ERQ25_MASK (0x2000000U)
11097 #define DMA_ERQ_ERQ25_SHIFT (25U)
11102 #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
11103 #define DMA_ERQ_ERQ26_MASK (0x4000000U)
11104 #define DMA_ERQ_ERQ26_SHIFT (26U)
11109 #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
11110 #define DMA_ERQ_ERQ27_MASK (0x8000000U)
11111 #define DMA_ERQ_ERQ27_SHIFT (27U)
11116 #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
11117 #define DMA_ERQ_ERQ28_MASK (0x10000000U)
11118 #define DMA_ERQ_ERQ28_SHIFT (28U)
11123 #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
11124 #define DMA_ERQ_ERQ29_MASK (0x20000000U)
11125 #define DMA_ERQ_ERQ29_SHIFT (29U)
11130 #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
11131 #define DMA_ERQ_ERQ30_MASK (0x40000000U)
11132 #define DMA_ERQ_ERQ30_SHIFT (30U)
11137 #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
11138 #define DMA_ERQ_ERQ31_MASK (0x80000000U)
11139 #define DMA_ERQ_ERQ31_SHIFT (31U)
11144 #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
11149 #define DMA_EEI_EEI0_MASK (0x1U)
11150 #define DMA_EEI_EEI0_SHIFT (0U)
11155 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
11156 #define DMA_EEI_EEI1_MASK (0x2U)
11157 #define DMA_EEI_EEI1_SHIFT (1U)
11162 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
11163 #define DMA_EEI_EEI2_MASK (0x4U)
11164 #define DMA_EEI_EEI2_SHIFT (2U)
11169 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
11170 #define DMA_EEI_EEI3_MASK (0x8U)
11171 #define DMA_EEI_EEI3_SHIFT (3U)
11176 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
11177 #define DMA_EEI_EEI4_MASK (0x10U)
11178 #define DMA_EEI_EEI4_SHIFT (4U)
11183 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
11184 #define DMA_EEI_EEI5_MASK (0x20U)
11185 #define DMA_EEI_EEI5_SHIFT (5U)
11190 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
11191 #define DMA_EEI_EEI6_MASK (0x40U)
11192 #define DMA_EEI_EEI6_SHIFT (6U)
11197 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
11198 #define DMA_EEI_EEI7_MASK (0x80U)
11199 #define DMA_EEI_EEI7_SHIFT (7U)
11204 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
11205 #define DMA_EEI_EEI8_MASK (0x100U)
11206 #define DMA_EEI_EEI8_SHIFT (8U)
11211 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
11212 #define DMA_EEI_EEI9_MASK (0x200U)
11213 #define DMA_EEI_EEI9_SHIFT (9U)
11218 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
11219 #define DMA_EEI_EEI10_MASK (0x400U)
11220 #define DMA_EEI_EEI10_SHIFT (10U)
11225 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
11226 #define DMA_EEI_EEI11_MASK (0x800U)
11227 #define DMA_EEI_EEI11_SHIFT (11U)
11232 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
11233 #define DMA_EEI_EEI12_MASK (0x1000U)
11234 #define DMA_EEI_EEI12_SHIFT (12U)
11239 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
11240 #define DMA_EEI_EEI13_MASK (0x2000U)
11241 #define DMA_EEI_EEI13_SHIFT (13U)
11246 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
11247 #define DMA_EEI_EEI14_MASK (0x4000U)
11248 #define DMA_EEI_EEI14_SHIFT (14U)
11253 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
11254 #define DMA_EEI_EEI15_MASK (0x8000U)
11255 #define DMA_EEI_EEI15_SHIFT (15U)
11260 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
11261 #define DMA_EEI_EEI16_MASK (0x10000U)
11262 #define DMA_EEI_EEI16_SHIFT (16U)
11267 #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
11268 #define DMA_EEI_EEI17_MASK (0x20000U)
11269 #define DMA_EEI_EEI17_SHIFT (17U)
11274 #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
11275 #define DMA_EEI_EEI18_MASK (0x40000U)
11276 #define DMA_EEI_EEI18_SHIFT (18U)
11281 #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
11282 #define DMA_EEI_EEI19_MASK (0x80000U)
11283 #define DMA_EEI_EEI19_SHIFT (19U)
11288 #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
11289 #define DMA_EEI_EEI20_MASK (0x100000U)
11290 #define DMA_EEI_EEI20_SHIFT (20U)
11295 #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
11296 #define DMA_EEI_EEI21_MASK (0x200000U)
11297 #define DMA_EEI_EEI21_SHIFT (21U)
11302 #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
11303 #define DMA_EEI_EEI22_MASK (0x400000U)
11304 #define DMA_EEI_EEI22_SHIFT (22U)
11309 #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
11310 #define DMA_EEI_EEI23_MASK (0x800000U)
11311 #define DMA_EEI_EEI23_SHIFT (23U)
11316 #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
11317 #define DMA_EEI_EEI24_MASK (0x1000000U)
11318 #define DMA_EEI_EEI24_SHIFT (24U)
11323 #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
11324 #define DMA_EEI_EEI25_MASK (0x2000000U)
11325 #define DMA_EEI_EEI25_SHIFT (25U)
11330 #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
11331 #define DMA_EEI_EEI26_MASK (0x4000000U)
11332 #define DMA_EEI_EEI26_SHIFT (26U)
11337 #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
11338 #define DMA_EEI_EEI27_MASK (0x8000000U)
11339 #define DMA_EEI_EEI27_SHIFT (27U)
11344 #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
11345 #define DMA_EEI_EEI28_MASK (0x10000000U)
11346 #define DMA_EEI_EEI28_SHIFT (28U)
11351 #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
11352 #define DMA_EEI_EEI29_MASK (0x20000000U)
11353 #define DMA_EEI_EEI29_SHIFT (29U)
11358 #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
11359 #define DMA_EEI_EEI30_MASK (0x40000000U)
11360 #define DMA_EEI_EEI30_SHIFT (30U)
11365 #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
11366 #define DMA_EEI_EEI31_MASK (0x80000000U)
11367 #define DMA_EEI_EEI31_SHIFT (31U)
11372 #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
11377 #define DMA_CEEI_CEEI_MASK (0x1FU)
11378 #define DMA_CEEI_CEEI_SHIFT (0U)
11381 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
11382 #define DMA_CEEI_CAEE_MASK (0x40U)
11383 #define DMA_CEEI_CAEE_SHIFT (6U)
11388 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
11389 #define DMA_CEEI_NOP_MASK (0x80U)
11390 #define DMA_CEEI_NOP_SHIFT (7U)
11395 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
11400 #define DMA_SEEI_SEEI_MASK (0x1FU)
11401 #define DMA_SEEI_SEEI_SHIFT (0U)
11404 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
11405 #define DMA_SEEI_SAEE_MASK (0x40U)
11406 #define DMA_SEEI_SAEE_SHIFT (6U)
11411 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
11412 #define DMA_SEEI_NOP_MASK (0x80U)
11413 #define DMA_SEEI_NOP_SHIFT (7U)
11418 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
11423 #define DMA_CERQ_CERQ_MASK (0x1FU)
11424 #define DMA_CERQ_CERQ_SHIFT (0U)
11427 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
11428 #define DMA_CERQ_CAER_MASK (0x40U)
11429 #define DMA_CERQ_CAER_SHIFT (6U)
11434 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
11435 #define DMA_CERQ_NOP_MASK (0x80U)
11436 #define DMA_CERQ_NOP_SHIFT (7U)
11441 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
11446 #define DMA_SERQ_SERQ_MASK (0x1FU)
11447 #define DMA_SERQ_SERQ_SHIFT (0U)
11450 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
11451 #define DMA_SERQ_SAER_MASK (0x40U)
11452 #define DMA_SERQ_SAER_SHIFT (6U)
11457 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
11458 #define DMA_SERQ_NOP_MASK (0x80U)
11459 #define DMA_SERQ_NOP_SHIFT (7U)
11464 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
11469 #define DMA_CDNE_CDNE_MASK (0x1FU)
11470 #define DMA_CDNE_CDNE_SHIFT (0U)
11473 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
11474 #define DMA_CDNE_CADN_MASK (0x40U)
11475 #define DMA_CDNE_CADN_SHIFT (6U)
11480 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
11481 #define DMA_CDNE_NOP_MASK (0x80U)
11482 #define DMA_CDNE_NOP_SHIFT (7U)
11487 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
11492 #define DMA_SSRT_SSRT_MASK (0x1FU)
11493 #define DMA_SSRT_SSRT_SHIFT (0U)
11496 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
11497 #define DMA_SSRT_SAST_MASK (0x40U)
11498 #define DMA_SSRT_SAST_SHIFT (6U)
11503 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
11504 #define DMA_SSRT_NOP_MASK (0x80U)
11505 #define DMA_SSRT_NOP_SHIFT (7U)
11510 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
11515 #define DMA_CERR_CERR_MASK (0x1FU)
11516 #define DMA_CERR_CERR_SHIFT (0U)
11519 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
11520 #define DMA_CERR_CAEI_MASK (0x40U)
11521 #define DMA_CERR_CAEI_SHIFT (6U)
11526 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
11527 #define DMA_CERR_NOP_MASK (0x80U)
11528 #define DMA_CERR_NOP_SHIFT (7U)
11533 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
11538 #define DMA_CINT_CINT_MASK (0x1FU)
11539 #define DMA_CINT_CINT_SHIFT (0U)
11542 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
11543 #define DMA_CINT_CAIR_MASK (0x40U)
11544 #define DMA_CINT_CAIR_SHIFT (6U)
11549 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
11550 #define DMA_CINT_NOP_MASK (0x80U)
11551 #define DMA_CINT_NOP_SHIFT (7U)
11556 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
11561 #define DMA_INT_INT0_MASK (0x1U)
11562 #define DMA_INT_INT0_SHIFT (0U)
11567 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
11568 #define DMA_INT_INT1_MASK (0x2U)
11569 #define DMA_INT_INT1_SHIFT (1U)
11574 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
11575 #define DMA_INT_INT2_MASK (0x4U)
11576 #define DMA_INT_INT2_SHIFT (2U)
11581 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
11582 #define DMA_INT_INT3_MASK (0x8U)
11583 #define DMA_INT_INT3_SHIFT (3U)
11588 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
11589 #define DMA_INT_INT4_MASK (0x10U)
11590 #define DMA_INT_INT4_SHIFT (4U)
11595 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
11596 #define DMA_INT_INT5_MASK (0x20U)
11597 #define DMA_INT_INT5_SHIFT (5U)
11602 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
11603 #define DMA_INT_INT6_MASK (0x40U)
11604 #define DMA_INT_INT6_SHIFT (6U)
11609 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
11610 #define DMA_INT_INT7_MASK (0x80U)
11611 #define DMA_INT_INT7_SHIFT (7U)
11616 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
11617 #define DMA_INT_INT8_MASK (0x100U)
11618 #define DMA_INT_INT8_SHIFT (8U)
11623 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
11624 #define DMA_INT_INT9_MASK (0x200U)
11625 #define DMA_INT_INT9_SHIFT (9U)
11630 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
11631 #define DMA_INT_INT10_MASK (0x400U)
11632 #define DMA_INT_INT10_SHIFT (10U)
11637 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
11638 #define DMA_INT_INT11_MASK (0x800U)
11639 #define DMA_INT_INT11_SHIFT (11U)
11644 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
11645 #define DMA_INT_INT12_MASK (0x1000U)
11646 #define DMA_INT_INT12_SHIFT (12U)
11651 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
11652 #define DMA_INT_INT13_MASK (0x2000U)
11653 #define DMA_INT_INT13_SHIFT (13U)
11658 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
11659 #define DMA_INT_INT14_MASK (0x4000U)
11660 #define DMA_INT_INT14_SHIFT (14U)
11665 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
11666 #define DMA_INT_INT15_MASK (0x8000U)
11667 #define DMA_INT_INT15_SHIFT (15U)
11672 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
11673 #define DMA_INT_INT16_MASK (0x10000U)
11674 #define DMA_INT_INT16_SHIFT (16U)
11679 #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
11680 #define DMA_INT_INT17_MASK (0x20000U)
11681 #define DMA_INT_INT17_SHIFT (17U)
11686 #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
11687 #define DMA_INT_INT18_MASK (0x40000U)
11688 #define DMA_INT_INT18_SHIFT (18U)
11693 #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
11694 #define DMA_INT_INT19_MASK (0x80000U)
11695 #define DMA_INT_INT19_SHIFT (19U)
11700 #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
11701 #define DMA_INT_INT20_MASK (0x100000U)
11702 #define DMA_INT_INT20_SHIFT (20U)
11707 #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
11708 #define DMA_INT_INT21_MASK (0x200000U)
11709 #define DMA_INT_INT21_SHIFT (21U)
11714 #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
11715 #define DMA_INT_INT22_MASK (0x400000U)
11716 #define DMA_INT_INT22_SHIFT (22U)
11721 #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
11722 #define DMA_INT_INT23_MASK (0x800000U)
11723 #define DMA_INT_INT23_SHIFT (23U)
11728 #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
11729 #define DMA_INT_INT24_MASK (0x1000000U)
11730 #define DMA_INT_INT24_SHIFT (24U)
11735 #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
11736 #define DMA_INT_INT25_MASK (0x2000000U)
11737 #define DMA_INT_INT25_SHIFT (25U)
11742 #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
11743 #define DMA_INT_INT26_MASK (0x4000000U)
11744 #define DMA_INT_INT26_SHIFT (26U)
11749 #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
11750 #define DMA_INT_INT27_MASK (0x8000000U)
11751 #define DMA_INT_INT27_SHIFT (27U)
11756 #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
11757 #define DMA_INT_INT28_MASK (0x10000000U)
11758 #define DMA_INT_INT28_SHIFT (28U)
11763 #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
11764 #define DMA_INT_INT29_MASK (0x20000000U)
11765 #define DMA_INT_INT29_SHIFT (29U)
11770 #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
11771 #define DMA_INT_INT30_MASK (0x40000000U)
11772 #define DMA_INT_INT30_SHIFT (30U)
11777 #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
11778 #define DMA_INT_INT31_MASK (0x80000000U)
11779 #define DMA_INT_INT31_SHIFT (31U)
11784 #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
11789 #define DMA_ERR_ERR0_MASK (0x1U)
11790 #define DMA_ERR_ERR0_SHIFT (0U)
11795 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
11796 #define DMA_ERR_ERR1_MASK (0x2U)
11797 #define DMA_ERR_ERR1_SHIFT (1U)
11802 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
11803 #define DMA_ERR_ERR2_MASK (0x4U)
11804 #define DMA_ERR_ERR2_SHIFT (2U)
11809 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
11810 #define DMA_ERR_ERR3_MASK (0x8U)
11811 #define DMA_ERR_ERR3_SHIFT (3U)
11816 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
11817 #define DMA_ERR_ERR4_MASK (0x10U)
11818 #define DMA_ERR_ERR4_SHIFT (4U)
11823 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
11824 #define DMA_ERR_ERR5_MASK (0x20U)
11825 #define DMA_ERR_ERR5_SHIFT (5U)
11830 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
11831 #define DMA_ERR_ERR6_MASK (0x40U)
11832 #define DMA_ERR_ERR6_SHIFT (6U)
11837 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
11838 #define DMA_ERR_ERR7_MASK (0x80U)
11839 #define DMA_ERR_ERR7_SHIFT (7U)
11844 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
11845 #define DMA_ERR_ERR8_MASK (0x100U)
11846 #define DMA_ERR_ERR8_SHIFT (8U)
11851 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
11852 #define DMA_ERR_ERR9_MASK (0x200U)
11853 #define DMA_ERR_ERR9_SHIFT (9U)
11858 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
11859 #define DMA_ERR_ERR10_MASK (0x400U)
11860 #define DMA_ERR_ERR10_SHIFT (10U)
11865 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
11866 #define DMA_ERR_ERR11_MASK (0x800U)
11867 #define DMA_ERR_ERR11_SHIFT (11U)
11872 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
11873 #define DMA_ERR_ERR12_MASK (0x1000U)
11874 #define DMA_ERR_ERR12_SHIFT (12U)
11879 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
11880 #define DMA_ERR_ERR13_MASK (0x2000U)
11881 #define DMA_ERR_ERR13_SHIFT (13U)
11886 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
11887 #define DMA_ERR_ERR14_MASK (0x4000U)
11888 #define DMA_ERR_ERR14_SHIFT (14U)
11893 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
11894 #define DMA_ERR_ERR15_MASK (0x8000U)
11895 #define DMA_ERR_ERR15_SHIFT (15U)
11900 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
11901 #define DMA_ERR_ERR16_MASK (0x10000U)
11902 #define DMA_ERR_ERR16_SHIFT (16U)
11907 #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
11908 #define DMA_ERR_ERR17_MASK (0x20000U)
11909 #define DMA_ERR_ERR17_SHIFT (17U)
11914 #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
11915 #define DMA_ERR_ERR18_MASK (0x40000U)
11916 #define DMA_ERR_ERR18_SHIFT (18U)
11921 #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
11922 #define DMA_ERR_ERR19_MASK (0x80000U)
11923 #define DMA_ERR_ERR19_SHIFT (19U)
11928 #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
11929 #define DMA_ERR_ERR20_MASK (0x100000U)
11930 #define DMA_ERR_ERR20_SHIFT (20U)
11935 #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
11936 #define DMA_ERR_ERR21_MASK (0x200000U)
11937 #define DMA_ERR_ERR21_SHIFT (21U)
11942 #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
11943 #define DMA_ERR_ERR22_MASK (0x400000U)
11944 #define DMA_ERR_ERR22_SHIFT (22U)
11949 #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
11950 #define DMA_ERR_ERR23_MASK (0x800000U)
11951 #define DMA_ERR_ERR23_SHIFT (23U)
11956 #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
11957 #define DMA_ERR_ERR24_MASK (0x1000000U)
11958 #define DMA_ERR_ERR24_SHIFT (24U)
11963 #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
11964 #define DMA_ERR_ERR25_MASK (0x2000000U)
11965 #define DMA_ERR_ERR25_SHIFT (25U)
11970 #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
11971 #define DMA_ERR_ERR26_MASK (0x4000000U)
11972 #define DMA_ERR_ERR26_SHIFT (26U)
11977 #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
11978 #define DMA_ERR_ERR27_MASK (0x8000000U)
11979 #define DMA_ERR_ERR27_SHIFT (27U)
11984 #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
11985 #define DMA_ERR_ERR28_MASK (0x10000000U)
11986 #define DMA_ERR_ERR28_SHIFT (28U)
11991 #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
11992 #define DMA_ERR_ERR29_MASK (0x20000000U)
11993 #define DMA_ERR_ERR29_SHIFT (29U)
11998 #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
11999 #define DMA_ERR_ERR30_MASK (0x40000000U)
12000 #define DMA_ERR_ERR30_SHIFT (30U)
12005 #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
12006 #define DMA_ERR_ERR31_MASK (0x80000000U)
12007 #define DMA_ERR_ERR31_SHIFT (31U)
12012 #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
12017 #define DMA_HRS_HRS0_MASK (0x1U)
12018 #define DMA_HRS_HRS0_SHIFT (0U)
12023 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
12024 #define DMA_HRS_HRS1_MASK (0x2U)
12025 #define DMA_HRS_HRS1_SHIFT (1U)
12030 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
12031 #define DMA_HRS_HRS2_MASK (0x4U)
12032 #define DMA_HRS_HRS2_SHIFT (2U)
12037 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
12038 #define DMA_HRS_HRS3_MASK (0x8U)
12039 #define DMA_HRS_HRS3_SHIFT (3U)
12044 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
12045 #define DMA_HRS_HRS4_MASK (0x10U)
12046 #define DMA_HRS_HRS4_SHIFT (4U)
12051 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
12052 #define DMA_HRS_HRS5_MASK (0x20U)
12053 #define DMA_HRS_HRS5_SHIFT (5U)
12058 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
12059 #define DMA_HRS_HRS6_MASK (0x40U)
12060 #define DMA_HRS_HRS6_SHIFT (6U)
12065 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
12066 #define DMA_HRS_HRS7_MASK (0x80U)
12067 #define DMA_HRS_HRS7_SHIFT (7U)
12072 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
12073 #define DMA_HRS_HRS8_MASK (0x100U)
12074 #define DMA_HRS_HRS8_SHIFT (8U)
12079 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
12080 #define DMA_HRS_HRS9_MASK (0x200U)
12081 #define DMA_HRS_HRS9_SHIFT (9U)
12086 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
12087 #define DMA_HRS_HRS10_MASK (0x400U)
12088 #define DMA_HRS_HRS10_SHIFT (10U)
12093 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
12094 #define DMA_HRS_HRS11_MASK (0x800U)
12095 #define DMA_HRS_HRS11_SHIFT (11U)
12100 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
12101 #define DMA_HRS_HRS12_MASK (0x1000U)
12102 #define DMA_HRS_HRS12_SHIFT (12U)
12107 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
12108 #define DMA_HRS_HRS13_MASK (0x2000U)
12109 #define DMA_HRS_HRS13_SHIFT (13U)
12114 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
12115 #define DMA_HRS_HRS14_MASK (0x4000U)
12116 #define DMA_HRS_HRS14_SHIFT (14U)
12121 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
12122 #define DMA_HRS_HRS15_MASK (0x8000U)
12123 #define DMA_HRS_HRS15_SHIFT (15U)
12128 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
12129 #define DMA_HRS_HRS16_MASK (0x10000U)
12130 #define DMA_HRS_HRS16_SHIFT (16U)
12135 #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
12136 #define DMA_HRS_HRS17_MASK (0x20000U)
12137 #define DMA_HRS_HRS17_SHIFT (17U)
12142 #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
12143 #define DMA_HRS_HRS18_MASK (0x40000U)
12144 #define DMA_HRS_HRS18_SHIFT (18U)
12149 #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
12150 #define DMA_HRS_HRS19_MASK (0x80000U)
12151 #define DMA_HRS_HRS19_SHIFT (19U)
12156 #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
12157 #define DMA_HRS_HRS20_MASK (0x100000U)
12158 #define DMA_HRS_HRS20_SHIFT (20U)
12163 #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
12164 #define DMA_HRS_HRS21_MASK (0x200000U)
12165 #define DMA_HRS_HRS21_SHIFT (21U)
12170 #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
12171 #define DMA_HRS_HRS22_MASK (0x400000U)
12172 #define DMA_HRS_HRS22_SHIFT (22U)
12177 #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
12178 #define DMA_HRS_HRS23_MASK (0x800000U)
12179 #define DMA_HRS_HRS23_SHIFT (23U)
12184 #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
12185 #define DMA_HRS_HRS24_MASK (0x1000000U)
12186 #define DMA_HRS_HRS24_SHIFT (24U)
12191 #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
12192 #define DMA_HRS_HRS25_MASK (0x2000000U)
12193 #define DMA_HRS_HRS25_SHIFT (25U)
12198 #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
12199 #define DMA_HRS_HRS26_MASK (0x4000000U)
12200 #define DMA_HRS_HRS26_SHIFT (26U)
12205 #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
12206 #define DMA_HRS_HRS27_MASK (0x8000000U)
12207 #define DMA_HRS_HRS27_SHIFT (27U)
12212 #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
12213 #define DMA_HRS_HRS28_MASK (0x10000000U)
12214 #define DMA_HRS_HRS28_SHIFT (28U)
12219 #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
12220 #define DMA_HRS_HRS29_MASK (0x20000000U)
12221 #define DMA_HRS_HRS29_SHIFT (29U)
12226 #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
12227 #define DMA_HRS_HRS30_MASK (0x40000000U)
12228 #define DMA_HRS_HRS30_SHIFT (30U)
12233 #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
12234 #define DMA_HRS_HRS31_MASK (0x80000000U)
12235 #define DMA_HRS_HRS31_SHIFT (31U)
12240 #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
12245 #define DMA_EARS_EDREQ_0_MASK (0x1U)
12246 #define DMA_EARS_EDREQ_0_SHIFT (0U)
12251 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
12252 #define DMA_EARS_EDREQ_1_MASK (0x2U)
12253 #define DMA_EARS_EDREQ_1_SHIFT (1U)
12258 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
12259 #define DMA_EARS_EDREQ_2_MASK (0x4U)
12260 #define DMA_EARS_EDREQ_2_SHIFT (2U)
12265 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
12266 #define DMA_EARS_EDREQ_3_MASK (0x8U)
12267 #define DMA_EARS_EDREQ_3_SHIFT (3U)
12272 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
12273 #define DMA_EARS_EDREQ_4_MASK (0x10U)
12274 #define DMA_EARS_EDREQ_4_SHIFT (4U)
12279 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
12280 #define DMA_EARS_EDREQ_5_MASK (0x20U)
12281 #define DMA_EARS_EDREQ_5_SHIFT (5U)
12286 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
12287 #define DMA_EARS_EDREQ_6_MASK (0x40U)
12288 #define DMA_EARS_EDREQ_6_SHIFT (6U)
12293 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
12294 #define DMA_EARS_EDREQ_7_MASK (0x80U)
12295 #define DMA_EARS_EDREQ_7_SHIFT (7U)
12300 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
12301 #define DMA_EARS_EDREQ_8_MASK (0x100U)
12302 #define DMA_EARS_EDREQ_8_SHIFT (8U)
12307 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
12308 #define DMA_EARS_EDREQ_9_MASK (0x200U)
12309 #define DMA_EARS_EDREQ_9_SHIFT (9U)
12314 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
12315 #define DMA_EARS_EDREQ_10_MASK (0x400U)
12316 #define DMA_EARS_EDREQ_10_SHIFT (10U)
12321 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
12322 #define DMA_EARS_EDREQ_11_MASK (0x800U)
12323 #define DMA_EARS_EDREQ_11_SHIFT (11U)
12328 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
12329 #define DMA_EARS_EDREQ_12_MASK (0x1000U)
12330 #define DMA_EARS_EDREQ_12_SHIFT (12U)
12335 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
12336 #define DMA_EARS_EDREQ_13_MASK (0x2000U)
12337 #define DMA_EARS_EDREQ_13_SHIFT (13U)
12342 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
12343 #define DMA_EARS_EDREQ_14_MASK (0x4000U)
12344 #define DMA_EARS_EDREQ_14_SHIFT (14U)
12349 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
12350 #define DMA_EARS_EDREQ_15_MASK (0x8000U)
12351 #define DMA_EARS_EDREQ_15_SHIFT (15U)
12356 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
12357 #define DMA_EARS_EDREQ_16_MASK (0x10000U)
12358 #define DMA_EARS_EDREQ_16_SHIFT (16U)
12363 #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
12364 #define DMA_EARS_EDREQ_17_MASK (0x20000U)
12365 #define DMA_EARS_EDREQ_17_SHIFT (17U)
12370 #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
12371 #define DMA_EARS_EDREQ_18_MASK (0x40000U)
12372 #define DMA_EARS_EDREQ_18_SHIFT (18U)
12377 #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
12378 #define DMA_EARS_EDREQ_19_MASK (0x80000U)
12379 #define DMA_EARS_EDREQ_19_SHIFT (19U)
12384 #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
12385 #define DMA_EARS_EDREQ_20_MASK (0x100000U)
12386 #define DMA_EARS_EDREQ_20_SHIFT (20U)
12391 #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
12392 #define DMA_EARS_EDREQ_21_MASK (0x200000U)
12393 #define DMA_EARS_EDREQ_21_SHIFT (21U)
12398 #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
12399 #define DMA_EARS_EDREQ_22_MASK (0x400000U)
12400 #define DMA_EARS_EDREQ_22_SHIFT (22U)
12405 #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
12406 #define DMA_EARS_EDREQ_23_MASK (0x800000U)
12407 #define DMA_EARS_EDREQ_23_SHIFT (23U)
12412 #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
12413 #define DMA_EARS_EDREQ_24_MASK (0x1000000U)
12414 #define DMA_EARS_EDREQ_24_SHIFT (24U)
12419 #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
12420 #define DMA_EARS_EDREQ_25_MASK (0x2000000U)
12421 #define DMA_EARS_EDREQ_25_SHIFT (25U)
12426 #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
12427 #define DMA_EARS_EDREQ_26_MASK (0x4000000U)
12428 #define DMA_EARS_EDREQ_26_SHIFT (26U)
12433 #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
12434 #define DMA_EARS_EDREQ_27_MASK (0x8000000U)
12435 #define DMA_EARS_EDREQ_27_SHIFT (27U)
12440 #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
12441 #define DMA_EARS_EDREQ_28_MASK (0x10000000U)
12442 #define DMA_EARS_EDREQ_28_SHIFT (28U)
12447 #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
12448 #define DMA_EARS_EDREQ_29_MASK (0x20000000U)
12449 #define DMA_EARS_EDREQ_29_SHIFT (29U)
12454 #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
12455 #define DMA_EARS_EDREQ_30_MASK (0x40000000U)
12456 #define DMA_EARS_EDREQ_30_SHIFT (30U)
12461 #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
12462 #define DMA_EARS_EDREQ_31_MASK (0x80000000U)
12463 #define DMA_EARS_EDREQ_31_SHIFT (31U)
12468 #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
12473 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
12474 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
12477 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
12478 #define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
12479 #define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
12482 #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
12483 #define DMA_DCHPRI3_DPA_MASK (0x40U)
12484 #define DMA_DCHPRI3_DPA_SHIFT (6U)
12489 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
12490 #define DMA_DCHPRI3_ECP_MASK (0x80U)
12491 #define DMA_DCHPRI3_ECP_SHIFT (7U)
12496 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
12501 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
12502 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
12505 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
12506 #define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
12507 #define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
12510 #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
12511 #define DMA_DCHPRI2_DPA_MASK (0x40U)
12512 #define DMA_DCHPRI2_DPA_SHIFT (6U)
12517 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
12518 #define DMA_DCHPRI2_ECP_MASK (0x80U)
12519 #define DMA_DCHPRI2_ECP_SHIFT (7U)
12524 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
12529 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
12530 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
12533 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
12534 #define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
12535 #define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
12538 #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
12539 #define DMA_DCHPRI1_DPA_MASK (0x40U)
12540 #define DMA_DCHPRI1_DPA_SHIFT (6U)
12545 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
12546 #define DMA_DCHPRI1_ECP_MASK (0x80U)
12547 #define DMA_DCHPRI1_ECP_SHIFT (7U)
12552 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
12557 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
12558 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
12561 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
12562 #define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
12563 #define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
12566 #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
12567 #define DMA_DCHPRI0_DPA_MASK (0x40U)
12568 #define DMA_DCHPRI0_DPA_SHIFT (6U)
12573 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
12574 #define DMA_DCHPRI0_ECP_MASK (0x80U)
12575 #define DMA_DCHPRI0_ECP_SHIFT (7U)
12580 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
12585 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
12586 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
12589 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
12590 #define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
12591 #define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
12594 #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
12595 #define DMA_DCHPRI7_DPA_MASK (0x40U)
12596 #define DMA_DCHPRI7_DPA_SHIFT (6U)
12601 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
12602 #define DMA_DCHPRI7_ECP_MASK (0x80U)
12603 #define DMA_DCHPRI7_ECP_SHIFT (7U)
12608 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
12613 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
12614 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
12617 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
12618 #define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
12619 #define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
12622 #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
12623 #define DMA_DCHPRI6_DPA_MASK (0x40U)
12624 #define DMA_DCHPRI6_DPA_SHIFT (6U)
12629 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
12630 #define DMA_DCHPRI6_ECP_MASK (0x80U)
12631 #define DMA_DCHPRI6_ECP_SHIFT (7U)
12636 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
12641 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
12642 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
12645 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
12646 #define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
12647 #define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
12650 #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
12651 #define DMA_DCHPRI5_DPA_MASK (0x40U)
12652 #define DMA_DCHPRI5_DPA_SHIFT (6U)
12657 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
12658 #define DMA_DCHPRI5_ECP_MASK (0x80U)
12659 #define DMA_DCHPRI5_ECP_SHIFT (7U)
12664 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
12669 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
12670 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
12673 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
12674 #define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
12675 #define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
12678 #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
12679 #define DMA_DCHPRI4_DPA_MASK (0x40U)
12680 #define DMA_DCHPRI4_DPA_SHIFT (6U)
12685 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
12686 #define DMA_DCHPRI4_ECP_MASK (0x80U)
12687 #define DMA_DCHPRI4_ECP_SHIFT (7U)
12692 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
12697 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
12698 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
12701 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
12702 #define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
12703 #define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
12706 #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
12707 #define DMA_DCHPRI11_DPA_MASK (0x40U)
12708 #define DMA_DCHPRI11_DPA_SHIFT (6U)
12713 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
12714 #define DMA_DCHPRI11_ECP_MASK (0x80U)
12715 #define DMA_DCHPRI11_ECP_SHIFT (7U)
12720 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
12725 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
12726 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
12729 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
12730 #define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
12731 #define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
12734 #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
12735 #define DMA_DCHPRI10_DPA_MASK (0x40U)
12736 #define DMA_DCHPRI10_DPA_SHIFT (6U)
12741 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
12742 #define DMA_DCHPRI10_ECP_MASK (0x80U)
12743 #define DMA_DCHPRI10_ECP_SHIFT (7U)
12748 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
12753 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
12754 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
12757 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
12758 #define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
12759 #define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
12762 #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
12763 #define DMA_DCHPRI9_DPA_MASK (0x40U)
12764 #define DMA_DCHPRI9_DPA_SHIFT (6U)
12769 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
12770 #define DMA_DCHPRI9_ECP_MASK (0x80U)
12771 #define DMA_DCHPRI9_ECP_SHIFT (7U)
12776 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
12781 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
12782 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
12785 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
12786 #define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
12787 #define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
12790 #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
12791 #define DMA_DCHPRI8_DPA_MASK (0x40U)
12792 #define DMA_DCHPRI8_DPA_SHIFT (6U)
12797 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
12798 #define DMA_DCHPRI8_ECP_MASK (0x80U)
12799 #define DMA_DCHPRI8_ECP_SHIFT (7U)
12804 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
12809 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
12810 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
12813 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
12814 #define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
12815 #define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
12818 #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
12819 #define DMA_DCHPRI15_DPA_MASK (0x40U)
12820 #define DMA_DCHPRI15_DPA_SHIFT (6U)
12825 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
12826 #define DMA_DCHPRI15_ECP_MASK (0x80U)
12827 #define DMA_DCHPRI15_ECP_SHIFT (7U)
12832 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
12837 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
12838 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
12841 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
12842 #define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
12843 #define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
12846 #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
12847 #define DMA_DCHPRI14_DPA_MASK (0x40U)
12848 #define DMA_DCHPRI14_DPA_SHIFT (6U)
12853 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
12854 #define DMA_DCHPRI14_ECP_MASK (0x80U)
12855 #define DMA_DCHPRI14_ECP_SHIFT (7U)
12860 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
12865 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
12866 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
12869 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
12870 #define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
12871 #define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
12874 #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
12875 #define DMA_DCHPRI13_DPA_MASK (0x40U)
12876 #define DMA_DCHPRI13_DPA_SHIFT (6U)
12881 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
12882 #define DMA_DCHPRI13_ECP_MASK (0x80U)
12883 #define DMA_DCHPRI13_ECP_SHIFT (7U)
12888 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
12893 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
12894 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
12897 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
12898 #define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
12899 #define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
12902 #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
12903 #define DMA_DCHPRI12_DPA_MASK (0x40U)
12904 #define DMA_DCHPRI12_DPA_SHIFT (6U)
12909 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
12910 #define DMA_DCHPRI12_ECP_MASK (0x80U)
12911 #define DMA_DCHPRI12_ECP_SHIFT (7U)
12916 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
12921 #define DMA_DCHPRI19_CHPRI_MASK (0xFU)
12922 #define DMA_DCHPRI19_CHPRI_SHIFT (0U)
12925 #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
12926 #define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
12927 #define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
12930 #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
12931 #define DMA_DCHPRI19_DPA_MASK (0x40U)
12932 #define DMA_DCHPRI19_DPA_SHIFT (6U)
12937 #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
12938 #define DMA_DCHPRI19_ECP_MASK (0x80U)
12939 #define DMA_DCHPRI19_ECP_SHIFT (7U)
12944 #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
12949 #define DMA_DCHPRI18_CHPRI_MASK (0xFU)
12950 #define DMA_DCHPRI18_CHPRI_SHIFT (0U)
12953 #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
12954 #define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
12955 #define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
12958 #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
12959 #define DMA_DCHPRI18_DPA_MASK (0x40U)
12960 #define DMA_DCHPRI18_DPA_SHIFT (6U)
12965 #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
12966 #define DMA_DCHPRI18_ECP_MASK (0x80U)
12967 #define DMA_DCHPRI18_ECP_SHIFT (7U)
12972 #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
12977 #define DMA_DCHPRI17_CHPRI_MASK (0xFU)
12978 #define DMA_DCHPRI17_CHPRI_SHIFT (0U)
12981 #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
12982 #define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
12983 #define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
12986 #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
12987 #define DMA_DCHPRI17_DPA_MASK (0x40U)
12988 #define DMA_DCHPRI17_DPA_SHIFT (6U)
12993 #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
12994 #define DMA_DCHPRI17_ECP_MASK (0x80U)
12995 #define DMA_DCHPRI17_ECP_SHIFT (7U)
13000 #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
13005 #define DMA_DCHPRI16_CHPRI_MASK (0xFU)
13006 #define DMA_DCHPRI16_CHPRI_SHIFT (0U)
13009 #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
13010 #define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
13011 #define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
13014 #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
13015 #define DMA_DCHPRI16_DPA_MASK (0x40U)
13016 #define DMA_DCHPRI16_DPA_SHIFT (6U)
13021 #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
13022 #define DMA_DCHPRI16_ECP_MASK (0x80U)
13023 #define DMA_DCHPRI16_ECP_SHIFT (7U)
13028 #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
13033 #define DMA_DCHPRI23_CHPRI_MASK (0xFU)
13034 #define DMA_DCHPRI23_CHPRI_SHIFT (0U)
13037 #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
13038 #define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
13039 #define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
13042 #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
13043 #define DMA_DCHPRI23_DPA_MASK (0x40U)
13044 #define DMA_DCHPRI23_DPA_SHIFT (6U)
13049 #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
13050 #define DMA_DCHPRI23_ECP_MASK (0x80U)
13051 #define DMA_DCHPRI23_ECP_SHIFT (7U)
13056 #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
13061 #define DMA_DCHPRI22_CHPRI_MASK (0xFU)
13062 #define DMA_DCHPRI22_CHPRI_SHIFT (0U)
13065 #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
13066 #define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
13067 #define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
13070 #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
13071 #define DMA_DCHPRI22_DPA_MASK (0x40U)
13072 #define DMA_DCHPRI22_DPA_SHIFT (6U)
13077 #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
13078 #define DMA_DCHPRI22_ECP_MASK (0x80U)
13079 #define DMA_DCHPRI22_ECP_SHIFT (7U)
13084 #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
13089 #define DMA_DCHPRI21_CHPRI_MASK (0xFU)
13090 #define DMA_DCHPRI21_CHPRI_SHIFT (0U)
13093 #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
13094 #define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
13095 #define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
13098 #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
13099 #define DMA_DCHPRI21_DPA_MASK (0x40U)
13100 #define DMA_DCHPRI21_DPA_SHIFT (6U)
13105 #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
13106 #define DMA_DCHPRI21_ECP_MASK (0x80U)
13107 #define DMA_DCHPRI21_ECP_SHIFT (7U)
13112 #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
13117 #define DMA_DCHPRI20_CHPRI_MASK (0xFU)
13118 #define DMA_DCHPRI20_CHPRI_SHIFT (0U)
13121 #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
13122 #define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
13123 #define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
13126 #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
13127 #define DMA_DCHPRI20_DPA_MASK (0x40U)
13128 #define DMA_DCHPRI20_DPA_SHIFT (6U)
13133 #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
13134 #define DMA_DCHPRI20_ECP_MASK (0x80U)
13135 #define DMA_DCHPRI20_ECP_SHIFT (7U)
13140 #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
13145 #define DMA_DCHPRI27_CHPRI_MASK (0xFU)
13146 #define DMA_DCHPRI27_CHPRI_SHIFT (0U)
13149 #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
13150 #define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
13151 #define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
13154 #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
13155 #define DMA_DCHPRI27_DPA_MASK (0x40U)
13156 #define DMA_DCHPRI27_DPA_SHIFT (6U)
13161 #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
13162 #define DMA_DCHPRI27_ECP_MASK (0x80U)
13163 #define DMA_DCHPRI27_ECP_SHIFT (7U)
13168 #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
13173 #define DMA_DCHPRI26_CHPRI_MASK (0xFU)
13174 #define DMA_DCHPRI26_CHPRI_SHIFT (0U)
13177 #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
13178 #define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
13179 #define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
13182 #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
13183 #define DMA_DCHPRI26_DPA_MASK (0x40U)
13184 #define DMA_DCHPRI26_DPA_SHIFT (6U)
13189 #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
13190 #define DMA_DCHPRI26_ECP_MASK (0x80U)
13191 #define DMA_DCHPRI26_ECP_SHIFT (7U)
13196 #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
13201 #define DMA_DCHPRI25_CHPRI_MASK (0xFU)
13202 #define DMA_DCHPRI25_CHPRI_SHIFT (0U)
13205 #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
13206 #define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
13207 #define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
13210 #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
13211 #define DMA_DCHPRI25_DPA_MASK (0x40U)
13212 #define DMA_DCHPRI25_DPA_SHIFT (6U)
13217 #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
13218 #define DMA_DCHPRI25_ECP_MASK (0x80U)
13219 #define DMA_DCHPRI25_ECP_SHIFT (7U)
13224 #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
13229 #define DMA_DCHPRI24_CHPRI_MASK (0xFU)
13230 #define DMA_DCHPRI24_CHPRI_SHIFT (0U)
13233 #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
13234 #define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
13235 #define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
13238 #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
13239 #define DMA_DCHPRI24_DPA_MASK (0x40U)
13240 #define DMA_DCHPRI24_DPA_SHIFT (6U)
13245 #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
13246 #define DMA_DCHPRI24_ECP_MASK (0x80U)
13247 #define DMA_DCHPRI24_ECP_SHIFT (7U)
13252 #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
13257 #define DMA_DCHPRI31_CHPRI_MASK (0xFU)
13258 #define DMA_DCHPRI31_CHPRI_SHIFT (0U)
13261 #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
13262 #define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
13263 #define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
13266 #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
13267 #define DMA_DCHPRI31_DPA_MASK (0x40U)
13268 #define DMA_DCHPRI31_DPA_SHIFT (6U)
13273 #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
13274 #define DMA_DCHPRI31_ECP_MASK (0x80U)
13275 #define DMA_DCHPRI31_ECP_SHIFT (7U)
13280 #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
13285 #define DMA_DCHPRI30_CHPRI_MASK (0xFU)
13286 #define DMA_DCHPRI30_CHPRI_SHIFT (0U)
13289 #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
13290 #define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
13291 #define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
13294 #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
13295 #define DMA_DCHPRI30_DPA_MASK (0x40U)
13296 #define DMA_DCHPRI30_DPA_SHIFT (6U)
13301 #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
13302 #define DMA_DCHPRI30_ECP_MASK (0x80U)
13303 #define DMA_DCHPRI30_ECP_SHIFT (7U)
13308 #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
13313 #define DMA_DCHPRI29_CHPRI_MASK (0xFU)
13314 #define DMA_DCHPRI29_CHPRI_SHIFT (0U)
13317 #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
13318 #define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
13319 #define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
13322 #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
13323 #define DMA_DCHPRI29_DPA_MASK (0x40U)
13324 #define DMA_DCHPRI29_DPA_SHIFT (6U)
13329 #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
13330 #define DMA_DCHPRI29_ECP_MASK (0x80U)
13331 #define DMA_DCHPRI29_ECP_SHIFT (7U)
13336 #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
13341 #define DMA_DCHPRI28_CHPRI_MASK (0xFU)
13342 #define DMA_DCHPRI28_CHPRI_SHIFT (0U)
13345 #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
13346 #define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
13347 #define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
13350 #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
13351 #define DMA_DCHPRI28_DPA_MASK (0x40U)
13352 #define DMA_DCHPRI28_DPA_SHIFT (6U)
13357 #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
13358 #define DMA_DCHPRI28_ECP_MASK (0x80U)
13359 #define DMA_DCHPRI28_ECP_SHIFT (7U)
13364 #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
13369 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
13370 #define DMA_SADDR_SADDR_SHIFT (0U)
13373 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
13376 /* The count of DMA_SADDR */
13377 #define DMA_SADDR_COUNT (32U)
13378 
13381 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
13382 #define DMA_SOFF_SOFF_SHIFT (0U)
13385 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
13388 /* The count of DMA_SOFF */
13389 #define DMA_SOFF_COUNT (32U)
13390 
13393 #define DMA_ATTR_DSIZE_MASK (0x7U)
13394 #define DMA_ATTR_DSIZE_SHIFT (0U)
13397 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
13398 #define DMA_ATTR_DMOD_MASK (0xF8U)
13399 #define DMA_ATTR_DMOD_SHIFT (3U)
13402 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
13403 #define DMA_ATTR_SSIZE_MASK (0x700U)
13404 #define DMA_ATTR_SSIZE_SHIFT (8U)
13415 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
13416 #define DMA_ATTR_SMOD_MASK (0xF800U)
13417 #define DMA_ATTR_SMOD_SHIFT (11U)
13422 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
13425 /* The count of DMA_ATTR */
13426 #define DMA_ATTR_COUNT (32U)
13427 
13430 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
13431 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
13434 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
13437 /* The count of DMA_NBYTES_MLNO */
13438 #define DMA_NBYTES_MLNO_COUNT (32U)
13439 
13442 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
13443 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
13446 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
13447 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
13448 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
13453 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
13454 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
13455 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
13460 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
13463 /* The count of DMA_NBYTES_MLOFFNO */
13464 #define DMA_NBYTES_MLOFFNO_COUNT (32U)
13465 
13468 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
13469 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
13472 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
13473 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
13474 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
13478 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
13479 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
13480 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
13485 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
13486 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
13487 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
13492 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
13495 /* The count of DMA_NBYTES_MLOFFYES */
13496 #define DMA_NBYTES_MLOFFYES_COUNT (32U)
13497 
13500 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
13501 #define DMA_SLAST_SLAST_SHIFT (0U)
13504 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
13507 /* The count of DMA_SLAST */
13508 #define DMA_SLAST_COUNT (32U)
13509 
13512 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
13513 #define DMA_DADDR_DADDR_SHIFT (0U)
13516 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
13519 /* The count of DMA_DADDR */
13520 #define DMA_DADDR_COUNT (32U)
13521 
13524 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
13525 #define DMA_DOFF_DOFF_SHIFT (0U)
13528 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
13531 /* The count of DMA_DOFF */
13532 #define DMA_DOFF_COUNT (32U)
13533 
13536 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
13537 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
13540 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
13541 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
13542 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
13547 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
13550 /* The count of DMA_CITER_ELINKNO */
13551 #define DMA_CITER_ELINKNO_COUNT (32U)
13552 
13555 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
13556 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
13559 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
13560 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
13561 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
13564 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
13565 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
13566 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
13571 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
13574 /* The count of DMA_CITER_ELINKYES */
13575 #define DMA_CITER_ELINKYES_COUNT (32U)
13576 
13579 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
13580 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
13583 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
13586 /* The count of DMA_DLAST_SGA */
13587 #define DMA_DLAST_SGA_COUNT (32U)
13588 
13591 #define DMA_CSR_START_MASK (0x1U)
13592 #define DMA_CSR_START_SHIFT (0U)
13597 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
13598 #define DMA_CSR_INTMAJOR_MASK (0x2U)
13599 #define DMA_CSR_INTMAJOR_SHIFT (1U)
13604 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
13605 #define DMA_CSR_INTHALF_MASK (0x4U)
13606 #define DMA_CSR_INTHALF_SHIFT (2U)
13611 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
13612 #define DMA_CSR_DREQ_MASK (0x8U)
13613 #define DMA_CSR_DREQ_SHIFT (3U)
13618 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
13619 #define DMA_CSR_ESG_MASK (0x10U)
13620 #define DMA_CSR_ESG_SHIFT (4U)
13625 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
13626 #define DMA_CSR_MAJORELINK_MASK (0x20U)
13627 #define DMA_CSR_MAJORELINK_SHIFT (5U)
13632 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
13633 #define DMA_CSR_ACTIVE_MASK (0x40U)
13634 #define DMA_CSR_ACTIVE_SHIFT (6U)
13637 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
13638 #define DMA_CSR_DONE_MASK (0x80U)
13639 #define DMA_CSR_DONE_SHIFT (7U)
13642 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
13643 #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
13644 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
13647 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
13648 #define DMA_CSR_BWC_MASK (0xC000U)
13649 #define DMA_CSR_BWC_SHIFT (14U)
13656 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
13659 /* The count of DMA_CSR */
13660 #define DMA_CSR_COUNT (32U)
13661 
13664 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
13665 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
13668 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
13669 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
13670 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
13675 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
13678 /* The count of DMA_BITER_ELINKNO */
13679 #define DMA_BITER_ELINKNO_COUNT (32U)
13680 
13683 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
13684 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
13687 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
13688 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
13689 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
13692 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
13693 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
13694 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
13699 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
13702 /* The count of DMA_BITER_ELINKYES */
13703 #define DMA_BITER_ELINKYES_COUNT (32U)
13704 
13705  /* end of group DMA_Register_Masks */
13709 
13710 
13711 /* DMA - Peripheral instance base addresses */
13713 #define DMA0_BASE (0x400E8000u)
13715 #define DMA0 ((DMA_Type *)DMA0_BASE)
13717 #define DMA_BASE_ADDRS { DMA0_BASE }
13719 #define DMA_BASE_PTRS { DMA0 }
13721 #define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
13722 #define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
13723  /* end of group DMA_Peripheral_Access_Layer */
13727 
13728 
13729 /* ----------------------------------------------------------------------------
13730  -- DMAMUX Peripheral Access Layer
13731  ---------------------------------------------------------------------------- */
13732 
13739 typedef struct {
13740  __IO uint32_t CHCFG[32];
13741 } DMAMUX_Type;
13742 
13743 /* ----------------------------------------------------------------------------
13744  -- DMAMUX Register Masks
13745  ---------------------------------------------------------------------------- */
13746 
13754 #define DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
13755 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
13758 #define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
13759 #define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
13760 #define DMAMUX_CHCFG_A_ON_SHIFT (29U)
13765 #define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
13766 #define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
13767 #define DMAMUX_CHCFG_TRIG_SHIFT (30U)
13773 #define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
13774 #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
13775 #define DMAMUX_CHCFG_ENBL_SHIFT (31U)
13780 #define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
13783 /* The count of DMAMUX_CHCFG */
13784 #define DMAMUX_CHCFG_COUNT (32U)
13785 
13786  /* end of group DMAMUX_Register_Masks */
13790 
13791 
13792 /* DMAMUX - Peripheral instance base addresses */
13794 #define DMAMUX_BASE (0x400EC000u)
13796 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
13798 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
13800 #define DMAMUX_BASE_PTRS { DMAMUX }
13801  /* end of group DMAMUX_Peripheral_Access_Layer */
13805 
13806 
13807 /* ----------------------------------------------------------------------------
13808  -- ENC Peripheral Access Layer
13809  ---------------------------------------------------------------------------- */
13810 
13817 typedef struct {
13818  __IO uint16_t CTRL;
13819  __IO uint16_t FILT;
13820  __IO uint16_t WTR;
13821  __IO uint16_t POSD;
13822  __I uint16_t POSDH;
13823  __IO uint16_t REV;
13824  __I uint16_t REVH;
13825  __IO uint16_t UPOS;
13826  __IO uint16_t LPOS;
13827  __I uint16_t UPOSH;
13828  __I uint16_t LPOSH;
13829  __IO uint16_t UINIT;
13830  __IO uint16_t LINIT;
13831  __I uint16_t IMR;
13832  __IO uint16_t TST;
13833  __IO uint16_t CTRL2;
13834  __IO uint16_t UMOD;
13835  __IO uint16_t LMOD;
13836  __IO uint16_t UCOMP;
13837  __IO uint16_t LCOMP;
13838 } ENC_Type;
13839 
13840 /* ----------------------------------------------------------------------------
13841  -- ENC Register Masks
13842  ---------------------------------------------------------------------------- */
13843 
13851 #define ENC_CTRL_CMPIE_MASK (0x1U)
13852 #define ENC_CTRL_CMPIE_SHIFT (0U)
13857 #define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
13858 #define ENC_CTRL_CMPIRQ_MASK (0x2U)
13859 #define ENC_CTRL_CMPIRQ_SHIFT (1U)
13864 #define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
13865 #define ENC_CTRL_WDE_MASK (0x4U)
13866 #define ENC_CTRL_WDE_SHIFT (2U)
13871 #define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
13872 #define ENC_CTRL_DIE_MASK (0x8U)
13873 #define ENC_CTRL_DIE_SHIFT (3U)
13878 #define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
13879 #define ENC_CTRL_DIRQ_MASK (0x10U)
13880 #define ENC_CTRL_DIRQ_SHIFT (4U)
13885 #define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
13886 #define ENC_CTRL_XNE_MASK (0x20U)
13887 #define ENC_CTRL_XNE_SHIFT (5U)
13892 #define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
13893 #define ENC_CTRL_XIP_MASK (0x40U)
13894 #define ENC_CTRL_XIP_SHIFT (6U)
13899 #define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
13900 #define ENC_CTRL_XIE_MASK (0x80U)
13901 #define ENC_CTRL_XIE_SHIFT (7U)
13906 #define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
13907 #define ENC_CTRL_XIRQ_MASK (0x100U)
13908 #define ENC_CTRL_XIRQ_SHIFT (8U)
13913 #define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
13914 #define ENC_CTRL_PH1_MASK (0x200U)
13915 #define ENC_CTRL_PH1_SHIFT (9U)
13923 #define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
13924 #define ENC_CTRL_REV_MASK (0x400U)
13925 #define ENC_CTRL_REV_SHIFT (10U)
13930 #define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
13931 #define ENC_CTRL_SWIP_MASK (0x800U)
13932 #define ENC_CTRL_SWIP_SHIFT (11U)
13937 #define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
13938 #define ENC_CTRL_HNE_MASK (0x1000U)
13939 #define ENC_CTRL_HNE_SHIFT (12U)
13944 #define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
13945 #define ENC_CTRL_HIP_MASK (0x2000U)
13946 #define ENC_CTRL_HIP_SHIFT (13U)
13951 #define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
13952 #define ENC_CTRL_HIE_MASK (0x4000U)
13953 #define ENC_CTRL_HIE_SHIFT (14U)
13958 #define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
13959 #define ENC_CTRL_HIRQ_MASK (0x8000U)
13960 #define ENC_CTRL_HIRQ_SHIFT (15U)
13965 #define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
13970 #define ENC_FILT_FILT_PER_MASK (0xFFU)
13971 #define ENC_FILT_FILT_PER_SHIFT (0U)
13974 #define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
13975 #define ENC_FILT_FILT_CNT_MASK (0x700U)
13976 #define ENC_FILT_FILT_CNT_SHIFT (8U)
13979 #define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
13984 #define ENC_WTR_WDOG_MASK (0xFFFFU)
13985 #define ENC_WTR_WDOG_SHIFT (0U)
13988 #define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
13993 #define ENC_POSD_POSD_MASK (0xFFFFU)
13994 #define ENC_POSD_POSD_SHIFT (0U)
13997 #define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
14002 #define ENC_POSDH_POSDH_MASK (0xFFFFU)
14003 #define ENC_POSDH_POSDH_SHIFT (0U)
14006 #define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
14011 #define ENC_REV_REV_MASK (0xFFFFU)
14012 #define ENC_REV_REV_SHIFT (0U)
14015 #define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
14020 #define ENC_REVH_REVH_MASK (0xFFFFU)
14021 #define ENC_REVH_REVH_SHIFT (0U)
14024 #define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
14029 #define ENC_UPOS_POS_MASK (0xFFFFU)
14030 #define ENC_UPOS_POS_SHIFT (0U)
14033 #define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
14038 #define ENC_LPOS_POS_MASK (0xFFFFU)
14039 #define ENC_LPOS_POS_SHIFT (0U)
14042 #define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
14047 #define ENC_UPOSH_POSH_MASK (0xFFFFU)
14048 #define ENC_UPOSH_POSH_SHIFT (0U)
14051 #define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
14056 #define ENC_LPOSH_POSH_MASK (0xFFFFU)
14057 #define ENC_LPOSH_POSH_SHIFT (0U)
14060 #define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
14065 #define ENC_UINIT_INIT_MASK (0xFFFFU)
14066 #define ENC_UINIT_INIT_SHIFT (0U)
14069 #define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
14074 #define ENC_LINIT_INIT_MASK (0xFFFFU)
14075 #define ENC_LINIT_INIT_SHIFT (0U)
14078 #define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
14083 #define ENC_IMR_HOME_MASK (0x1U)
14084 #define ENC_IMR_HOME_SHIFT (0U)
14087 #define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
14088 #define ENC_IMR_INDEX_MASK (0x2U)
14089 #define ENC_IMR_INDEX_SHIFT (1U)
14092 #define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
14093 #define ENC_IMR_PHB_MASK (0x4U)
14094 #define ENC_IMR_PHB_SHIFT (2U)
14097 #define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
14098 #define ENC_IMR_PHA_MASK (0x8U)
14099 #define ENC_IMR_PHA_SHIFT (3U)
14102 #define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
14103 #define ENC_IMR_FHOM_MASK (0x10U)
14104 #define ENC_IMR_FHOM_SHIFT (4U)
14107 #define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
14108 #define ENC_IMR_FIND_MASK (0x20U)
14109 #define ENC_IMR_FIND_SHIFT (5U)
14112 #define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
14113 #define ENC_IMR_FPHB_MASK (0x40U)
14114 #define ENC_IMR_FPHB_SHIFT (6U)
14117 #define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
14118 #define ENC_IMR_FPHA_MASK (0x80U)
14119 #define ENC_IMR_FPHA_SHIFT (7U)
14122 #define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
14127 #define ENC_TST_TEST_COUNT_MASK (0xFFU)
14128 #define ENC_TST_TEST_COUNT_SHIFT (0U)
14131 #define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
14132 #define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
14133 #define ENC_TST_TEST_PERIOD_SHIFT (8U)
14136 #define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
14137 #define ENC_TST_QDN_MASK (0x2000U)
14138 #define ENC_TST_QDN_SHIFT (13U)
14143 #define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
14144 #define ENC_TST_TCE_MASK (0x4000U)
14145 #define ENC_TST_TCE_SHIFT (14U)
14150 #define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
14151 #define ENC_TST_TEN_MASK (0x8000U)
14152 #define ENC_TST_TEN_SHIFT (15U)
14157 #define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
14162 #define ENC_CTRL2_UPDHLD_MASK (0x1U)
14163 #define ENC_CTRL2_UPDHLD_SHIFT (0U)
14168 #define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
14169 #define ENC_CTRL2_UPDPOS_MASK (0x2U)
14170 #define ENC_CTRL2_UPDPOS_SHIFT (1U)
14175 #define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
14176 #define ENC_CTRL2_MOD_MASK (0x4U)
14177 #define ENC_CTRL2_MOD_SHIFT (2U)
14182 #define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
14183 #define ENC_CTRL2_DIR_MASK (0x8U)
14184 #define ENC_CTRL2_DIR_SHIFT (3U)
14189 #define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
14190 #define ENC_CTRL2_RUIE_MASK (0x10U)
14191 #define ENC_CTRL2_RUIE_SHIFT (4U)
14196 #define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
14197 #define ENC_CTRL2_RUIRQ_MASK (0x20U)
14198 #define ENC_CTRL2_RUIRQ_SHIFT (5U)
14203 #define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
14204 #define ENC_CTRL2_ROIE_MASK (0x40U)
14205 #define ENC_CTRL2_ROIE_SHIFT (6U)
14210 #define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
14211 #define ENC_CTRL2_ROIRQ_MASK (0x80U)
14212 #define ENC_CTRL2_ROIRQ_SHIFT (7U)
14217 #define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
14218 #define ENC_CTRL2_REVMOD_MASK (0x100U)
14219 #define ENC_CTRL2_REVMOD_SHIFT (8U)
14224 #define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
14225 #define ENC_CTRL2_OUTCTL_MASK (0x200U)
14226 #define ENC_CTRL2_OUTCTL_SHIFT (9U)
14231 #define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
14232 #define ENC_CTRL2_SABIE_MASK (0x400U)
14233 #define ENC_CTRL2_SABIE_SHIFT (10U)
14238 #define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
14239 #define ENC_CTRL2_SABIRQ_MASK (0x800U)
14240 #define ENC_CTRL2_SABIRQ_SHIFT (11U)
14245 #define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
14250 #define ENC_UMOD_MOD_MASK (0xFFFFU)
14251 #define ENC_UMOD_MOD_SHIFT (0U)
14254 #define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
14259 #define ENC_LMOD_MOD_MASK (0xFFFFU)
14260 #define ENC_LMOD_MOD_SHIFT (0U)
14263 #define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
14268 #define ENC_UCOMP_COMP_MASK (0xFFFFU)
14269 #define ENC_UCOMP_COMP_SHIFT (0U)
14272 #define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
14277 #define ENC_LCOMP_COMP_MASK (0xFFFFU)
14278 #define ENC_LCOMP_COMP_SHIFT (0U)
14281 #define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) /* end of group ENC_Register_Masks */
14288 
14289 
14290 /* ENC - Peripheral instance base addresses */
14292 #define ENC1_BASE (0x403C8000u)
14294 #define ENC1 ((ENC_Type *)ENC1_BASE)
14296 #define ENC2_BASE (0x403CC000u)
14298 #define ENC2 ((ENC_Type *)ENC2_BASE)
14300 #define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE }
14302 #define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2 }
14304 #define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn }
14305 #define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn }
14306 #define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn }
14307 #define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn }
14308 #define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn }
14309  /* end of group ENC_Peripheral_Access_Layer */
14313 
14314 
14315 /* ----------------------------------------------------------------------------
14316  -- ENET Peripheral Access Layer
14317  ---------------------------------------------------------------------------- */
14318 
14325 typedef struct {
14326  uint8_t RESERVED_0[4];
14327  __IO uint32_t EIR;
14328  __IO uint32_t EIMR;
14329  uint8_t RESERVED_1[4];
14330  __IO uint32_t RDAR;
14331  __IO uint32_t TDAR;
14332  uint8_t RESERVED_2[12];
14333  __IO uint32_t ECR;
14334  uint8_t RESERVED_3[24];
14335  __IO uint32_t MMFR;
14336  __IO uint32_t MSCR;
14337  uint8_t RESERVED_4[28];
14338  __IO uint32_t MIBC;
14339  uint8_t RESERVED_5[28];
14340  __IO uint32_t RCR;
14341  uint8_t RESERVED_6[60];
14342  __IO uint32_t TCR;
14343  uint8_t RESERVED_7[28];
14344  __IO uint32_t PALR;
14345  __IO uint32_t PAUR;
14346  __IO uint32_t OPD;
14347  __IO uint32_t TXIC;
14348  uint8_t RESERVED_8[12];
14349  __IO uint32_t RXIC;
14350  uint8_t RESERVED_9[20];
14351  __IO uint32_t IAUR;
14352  __IO uint32_t IALR;
14353  __IO uint32_t GAUR;
14354  __IO uint32_t GALR;
14355  uint8_t RESERVED_10[28];
14356  __IO uint32_t TFWR;
14357  uint8_t RESERVED_11[56];
14358  __IO uint32_t RDSR;
14359  __IO uint32_t TDSR;
14360  __IO uint32_t MRBR;
14361  uint8_t RESERVED_12[4];
14362  __IO uint32_t RSFL;
14363  __IO uint32_t RSEM;
14364  __IO uint32_t RAEM;
14365  __IO uint32_t RAFL;
14366  __IO uint32_t TSEM;
14367  __IO uint32_t TAEM;
14368  __IO uint32_t TAFL;
14369  __IO uint32_t TIPG;
14370  __IO uint32_t FTRL;
14371  uint8_t RESERVED_13[12];
14372  __IO uint32_t TACC;
14373  __IO uint32_t RACC;
14374  uint8_t RESERVED_14[56];
14375  uint32_t RMON_T_DROP;
14376  __I uint32_t RMON_T_PACKETS;
14377  __I uint32_t RMON_T_BC_PKT;
14378  __I uint32_t RMON_T_MC_PKT;
14379  __I uint32_t RMON_T_CRC_ALIGN;
14380  __I uint32_t RMON_T_UNDERSIZE;
14381  __I uint32_t RMON_T_OVERSIZE;
14382  __I uint32_t RMON_T_FRAG;
14383  __I uint32_t RMON_T_JAB;
14384  __I uint32_t RMON_T_COL;
14385  __I uint32_t RMON_T_P64;
14386  __I uint32_t RMON_T_P65TO127;
14387  __I uint32_t RMON_T_P128TO255;
14388  __I uint32_t RMON_T_P256TO511;
14389  __I uint32_t RMON_T_P512TO1023;
14390  __I uint32_t RMON_T_P1024TO2047;
14391  __I uint32_t RMON_T_P_GTE2048;
14392  __I uint32_t RMON_T_OCTETS;
14393  uint32_t IEEE_T_DROP;
14394  __I uint32_t IEEE_T_FRAME_OK;
14395  __I uint32_t IEEE_T_1COL;
14396  __I uint32_t IEEE_T_MCOL;
14397  __I uint32_t IEEE_T_DEF;
14398  __I uint32_t IEEE_T_LCOL;
14399  __I uint32_t IEEE_T_EXCOL;
14400  __I uint32_t IEEE_T_MACERR;
14401  __I uint32_t IEEE_T_CSERR;
14402  __I uint32_t IEEE_T_SQE;
14403  __I uint32_t IEEE_T_FDXFC;
14404  __I uint32_t IEEE_T_OCTETS_OK;
14405  uint8_t RESERVED_15[12];
14406  __I uint32_t RMON_R_PACKETS;
14407  __I uint32_t RMON_R_BC_PKT;
14408  __I uint32_t RMON_R_MC_PKT;
14409  __I uint32_t RMON_R_CRC_ALIGN;
14410  __I uint32_t RMON_R_UNDERSIZE;
14411  __I uint32_t RMON_R_OVERSIZE;
14412  __I uint32_t RMON_R_FRAG;
14413  __I uint32_t RMON_R_JAB;
14414  uint32_t RMON_R_RESVD_0;
14415  __I uint32_t RMON_R_P64;
14416  __I uint32_t RMON_R_P65TO127;
14417  __I uint32_t RMON_R_P128TO255;
14418  __I uint32_t RMON_R_P256TO511;
14419  __I uint32_t RMON_R_P512TO1023;
14420  __I uint32_t RMON_R_P1024TO2047;
14421  __I uint32_t RMON_R_P_GTE2048;
14422  __I uint32_t RMON_R_OCTETS;
14423  __I uint32_t IEEE_R_DROP;
14424  __I uint32_t IEEE_R_FRAME_OK;
14425  __I uint32_t IEEE_R_CRC;
14426  __I uint32_t IEEE_R_ALIGN;
14427  __I uint32_t IEEE_R_MACERR;
14428  __I uint32_t IEEE_R_FDXFC;
14429  __I uint32_t IEEE_R_OCTETS_OK;
14430  uint8_t RESERVED_16[284];
14431  __IO uint32_t ATCR;
14432  __IO uint32_t ATVR;
14433  __IO uint32_t ATOFF;
14434  __IO uint32_t ATPER;
14435  __IO uint32_t ATCOR;
14436  __IO uint32_t ATINC;
14437  __I uint32_t ATSTMP;
14438  uint8_t RESERVED_17[488];
14439  __IO uint32_t TGSR;
14440  struct { /* offset: 0x608, array step: 0x8 */
14441  __IO uint32_t TCSR;
14442  __IO uint32_t TCCR;
14443  } CHANNEL[4];
14444 } ENET_Type;
14445 
14446 /* ----------------------------------------------------------------------------
14447  -- ENET Register Masks
14448  ---------------------------------------------------------------------------- */
14449 
14457 #define ENET_EIR_TS_TIMER_MASK (0x8000U)
14458 #define ENET_EIR_TS_TIMER_SHIFT (15U)
14461 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
14462 #define ENET_EIR_TS_AVAIL_MASK (0x10000U)
14463 #define ENET_EIR_TS_AVAIL_SHIFT (16U)
14466 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
14467 #define ENET_EIR_WAKEUP_MASK (0x20000U)
14468 #define ENET_EIR_WAKEUP_SHIFT (17U)
14471 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
14472 #define ENET_EIR_PLR_MASK (0x40000U)
14473 #define ENET_EIR_PLR_SHIFT (18U)
14476 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
14477 #define ENET_EIR_UN_MASK (0x80000U)
14478 #define ENET_EIR_UN_SHIFT (19U)
14481 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
14482 #define ENET_EIR_RL_MASK (0x100000U)
14483 #define ENET_EIR_RL_SHIFT (20U)
14486 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
14487 #define ENET_EIR_LC_MASK (0x200000U)
14488 #define ENET_EIR_LC_SHIFT (21U)
14491 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
14492 #define ENET_EIR_EBERR_MASK (0x400000U)
14493 #define ENET_EIR_EBERR_SHIFT (22U)
14496 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
14497 #define ENET_EIR_MII_MASK (0x800000U)
14498 #define ENET_EIR_MII_SHIFT (23U)
14501 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
14502 #define ENET_EIR_RXB_MASK (0x1000000U)
14503 #define ENET_EIR_RXB_SHIFT (24U)
14506 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
14507 #define ENET_EIR_RXF_MASK (0x2000000U)
14508 #define ENET_EIR_RXF_SHIFT (25U)
14511 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
14512 #define ENET_EIR_TXB_MASK (0x4000000U)
14513 #define ENET_EIR_TXB_SHIFT (26U)
14516 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
14517 #define ENET_EIR_TXF_MASK (0x8000000U)
14518 #define ENET_EIR_TXF_SHIFT (27U)
14521 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
14522 #define ENET_EIR_GRA_MASK (0x10000000U)
14523 #define ENET_EIR_GRA_SHIFT (28U)
14526 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
14527 #define ENET_EIR_BABT_MASK (0x20000000U)
14528 #define ENET_EIR_BABT_SHIFT (29U)
14531 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
14532 #define ENET_EIR_BABR_MASK (0x40000000U)
14533 #define ENET_EIR_BABR_SHIFT (30U)
14536 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
14541 #define ENET_EIMR_TS_TIMER_MASK (0x8000U)
14542 #define ENET_EIMR_TS_TIMER_SHIFT (15U)
14545 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
14546 #define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
14547 #define ENET_EIMR_TS_AVAIL_SHIFT (16U)
14550 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
14551 #define ENET_EIMR_WAKEUP_MASK (0x20000U)
14552 #define ENET_EIMR_WAKEUP_SHIFT (17U)
14555 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
14556 #define ENET_EIMR_PLR_MASK (0x40000U)
14557 #define ENET_EIMR_PLR_SHIFT (18U)
14560 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
14561 #define ENET_EIMR_UN_MASK (0x80000U)
14562 #define ENET_EIMR_UN_SHIFT (19U)
14565 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
14566 #define ENET_EIMR_RL_MASK (0x100000U)
14567 #define ENET_EIMR_RL_SHIFT (20U)
14570 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
14571 #define ENET_EIMR_LC_MASK (0x200000U)
14572 #define ENET_EIMR_LC_SHIFT (21U)
14575 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
14576 #define ENET_EIMR_EBERR_MASK (0x400000U)
14577 #define ENET_EIMR_EBERR_SHIFT (22U)
14580 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
14581 #define ENET_EIMR_MII_MASK (0x800000U)
14582 #define ENET_EIMR_MII_SHIFT (23U)
14585 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
14586 #define ENET_EIMR_RXB_MASK (0x1000000U)
14587 #define ENET_EIMR_RXB_SHIFT (24U)
14590 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
14591 #define ENET_EIMR_RXF_MASK (0x2000000U)
14592 #define ENET_EIMR_RXF_SHIFT (25U)
14595 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
14596 #define ENET_EIMR_TXB_MASK (0x4000000U)
14597 #define ENET_EIMR_TXB_SHIFT (26U)
14602 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
14603 #define ENET_EIMR_TXF_MASK (0x8000000U)
14604 #define ENET_EIMR_TXF_SHIFT (27U)
14609 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
14610 #define ENET_EIMR_GRA_MASK (0x10000000U)
14611 #define ENET_EIMR_GRA_SHIFT (28U)
14616 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
14617 #define ENET_EIMR_BABT_MASK (0x20000000U)
14618 #define ENET_EIMR_BABT_SHIFT (29U)
14623 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
14624 #define ENET_EIMR_BABR_MASK (0x40000000U)
14625 #define ENET_EIMR_BABR_SHIFT (30U)
14630 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
14635 #define ENET_RDAR_RDAR_MASK (0x1000000U)
14636 #define ENET_RDAR_RDAR_SHIFT (24U)
14639 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
14644 #define ENET_TDAR_TDAR_MASK (0x1000000U)
14645 #define ENET_TDAR_TDAR_SHIFT (24U)
14648 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
14653 #define ENET_ECR_RESET_MASK (0x1U)
14654 #define ENET_ECR_RESET_SHIFT (0U)
14657 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
14658 #define ENET_ECR_ETHEREN_MASK (0x2U)
14659 #define ENET_ECR_ETHEREN_SHIFT (1U)
14664 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
14665 #define ENET_ECR_MAGICEN_MASK (0x4U)
14666 #define ENET_ECR_MAGICEN_SHIFT (2U)
14671 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
14672 #define ENET_ECR_SLEEP_MASK (0x8U)
14673 #define ENET_ECR_SLEEP_SHIFT (3U)
14678 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
14679 #define ENET_ECR_EN1588_MASK (0x10U)
14680 #define ENET_ECR_EN1588_SHIFT (4U)
14685 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
14686 #define ENET_ECR_DBGEN_MASK (0x40U)
14687 #define ENET_ECR_DBGEN_SHIFT (6U)
14692 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
14693 #define ENET_ECR_DBSWP_MASK (0x100U)
14694 #define ENET_ECR_DBSWP_SHIFT (8U)
14699 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
14704 #define ENET_MMFR_DATA_MASK (0xFFFFU)
14705 #define ENET_MMFR_DATA_SHIFT (0U)
14708 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
14709 #define ENET_MMFR_TA_MASK (0x30000U)
14710 #define ENET_MMFR_TA_SHIFT (16U)
14713 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
14714 #define ENET_MMFR_RA_MASK (0x7C0000U)
14715 #define ENET_MMFR_RA_SHIFT (18U)
14718 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
14719 #define ENET_MMFR_PA_MASK (0xF800000U)
14720 #define ENET_MMFR_PA_SHIFT (23U)
14723 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
14724 #define ENET_MMFR_OP_MASK (0x30000000U)
14725 #define ENET_MMFR_OP_SHIFT (28U)
14728 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
14729 #define ENET_MMFR_ST_MASK (0xC0000000U)
14730 #define ENET_MMFR_ST_SHIFT (30U)
14733 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
14738 #define ENET_MSCR_MII_SPEED_MASK (0x7EU)
14739 #define ENET_MSCR_MII_SPEED_SHIFT (1U)
14742 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
14743 #define ENET_MSCR_DIS_PRE_MASK (0x80U)
14744 #define ENET_MSCR_DIS_PRE_SHIFT (7U)
14749 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
14750 #define ENET_MSCR_HOLDTIME_MASK (0x700U)
14751 #define ENET_MSCR_HOLDTIME_SHIFT (8U)
14758 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
14763 #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
14764 #define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
14769 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
14770 #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
14771 #define ENET_MIBC_MIB_IDLE_SHIFT (30U)
14776 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
14777 #define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
14778 #define ENET_MIBC_MIB_DIS_SHIFT (31U)
14783 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
14788 #define ENET_RCR_LOOP_MASK (0x1U)
14789 #define ENET_RCR_LOOP_SHIFT (0U)
14794 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
14795 #define ENET_RCR_DRT_MASK (0x2U)
14796 #define ENET_RCR_DRT_SHIFT (1U)
14801 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
14802 #define ENET_RCR_MII_MODE_MASK (0x4U)
14803 #define ENET_RCR_MII_MODE_SHIFT (2U)
14808 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
14809 #define ENET_RCR_PROM_MASK (0x8U)
14810 #define ENET_RCR_PROM_SHIFT (3U)
14815 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
14816 #define ENET_RCR_BC_REJ_MASK (0x10U)
14817 #define ENET_RCR_BC_REJ_SHIFT (4U)
14820 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
14821 #define ENET_RCR_FCE_MASK (0x20U)
14822 #define ENET_RCR_FCE_SHIFT (5U)
14825 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
14826 #define ENET_RCR_RMII_MODE_MASK (0x100U)
14827 #define ENET_RCR_RMII_MODE_SHIFT (8U)
14832 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
14833 #define ENET_RCR_RMII_10T_MASK (0x200U)
14834 #define ENET_RCR_RMII_10T_SHIFT (9U)
14839 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
14840 #define ENET_RCR_PADEN_MASK (0x1000U)
14841 #define ENET_RCR_PADEN_SHIFT (12U)
14846 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
14847 #define ENET_RCR_PAUFWD_MASK (0x2000U)
14848 #define ENET_RCR_PAUFWD_SHIFT (13U)
14853 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
14854 #define ENET_RCR_CRCFWD_MASK (0x4000U)
14855 #define ENET_RCR_CRCFWD_SHIFT (14U)
14860 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
14861 #define ENET_RCR_CFEN_MASK (0x8000U)
14862 #define ENET_RCR_CFEN_SHIFT (15U)
14867 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
14868 #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
14869 #define ENET_RCR_MAX_FL_SHIFT (16U)
14872 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
14873 #define ENET_RCR_NLC_MASK (0x40000000U)
14874 #define ENET_RCR_NLC_SHIFT (30U)
14879 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
14880 #define ENET_RCR_GRS_MASK (0x80000000U)
14881 #define ENET_RCR_GRS_SHIFT (31U)
14884 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
14889 #define ENET_TCR_GTS_MASK (0x1U)
14890 #define ENET_TCR_GTS_SHIFT (0U)
14893 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
14894 #define ENET_TCR_FDEN_MASK (0x4U)
14895 #define ENET_TCR_FDEN_SHIFT (2U)
14898 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
14899 #define ENET_TCR_TFC_PAUSE_MASK (0x8U)
14900 #define ENET_TCR_TFC_PAUSE_SHIFT (3U)
14905 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
14906 #define ENET_TCR_RFC_PAUSE_MASK (0x10U)
14907 #define ENET_TCR_RFC_PAUSE_SHIFT (4U)
14910 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
14911 #define ENET_TCR_ADDSEL_MASK (0xE0U)
14912 #define ENET_TCR_ADDSEL_SHIFT (5U)
14919 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
14920 #define ENET_TCR_ADDINS_MASK (0x100U)
14921 #define ENET_TCR_ADDINS_SHIFT (8U)
14926 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
14927 #define ENET_TCR_CRCFWD_MASK (0x200U)
14928 #define ENET_TCR_CRCFWD_SHIFT (9U)
14933 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
14938 #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
14939 #define ENET_PALR_PADDR1_SHIFT (0U)
14942 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
14947 #define ENET_PAUR_TYPE_MASK (0xFFFFU)
14948 #define ENET_PAUR_TYPE_SHIFT (0U)
14951 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
14952 #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
14953 #define ENET_PAUR_PADDR2_SHIFT (16U)
14954 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
14959 #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
14960 #define ENET_OPD_PAUSE_DUR_SHIFT (0U)
14963 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
14964 #define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
14965 #define ENET_OPD_OPCODE_SHIFT (16U)
14968 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
14973 #define ENET_TXIC_ICTT_MASK (0xFFFFU)
14974 #define ENET_TXIC_ICTT_SHIFT (0U)
14977 #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
14978 #define ENET_TXIC_ICFT_MASK (0xFF00000U)
14979 #define ENET_TXIC_ICFT_SHIFT (20U)
14982 #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
14983 #define ENET_TXIC_ICCS_MASK (0x40000000U)
14984 #define ENET_TXIC_ICCS_SHIFT (30U)
14989 #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
14990 #define ENET_TXIC_ICEN_MASK (0x80000000U)
14991 #define ENET_TXIC_ICEN_SHIFT (31U)
14996 #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
15001 #define ENET_RXIC_ICTT_MASK (0xFFFFU)
15002 #define ENET_RXIC_ICTT_SHIFT (0U)
15005 #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
15006 #define ENET_RXIC_ICFT_MASK (0xFF00000U)
15007 #define ENET_RXIC_ICFT_SHIFT (20U)
15010 #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
15011 #define ENET_RXIC_ICCS_MASK (0x40000000U)
15012 #define ENET_RXIC_ICCS_SHIFT (30U)
15017 #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
15018 #define ENET_RXIC_ICEN_MASK (0x80000000U)
15019 #define ENET_RXIC_ICEN_SHIFT (31U)
15024 #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
15029 #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
15030 #define ENET_IAUR_IADDR1_SHIFT (0U)
15031 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
15036 #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
15037 #define ENET_IALR_IADDR2_SHIFT (0U)
15038 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
15043 #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
15044 #define ENET_GAUR_GADDR1_SHIFT (0U)
15045 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
15050 #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
15051 #define ENET_GALR_GADDR2_SHIFT (0U)
15052 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
15057 #define ENET_TFWR_TFWR_MASK (0x3FU)
15058 #define ENET_TFWR_TFWR_SHIFT (0U)
15066 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
15067 #define ENET_TFWR_STRFWD_MASK (0x100U)
15068 #define ENET_TFWR_STRFWD_SHIFT (8U)
15073 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
15078 #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
15079 #define ENET_RDSR_R_DES_START_SHIFT (3U)
15080 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
15085 #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
15086 #define ENET_TDSR_X_DES_START_SHIFT (3U)
15087 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
15092 #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
15093 #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
15094 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
15099 #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
15100 #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
15103 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
15108 #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
15109 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
15112 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
15113 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
15114 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
15117 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
15122 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
15123 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
15126 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
15131 #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
15132 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
15135 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
15140 #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
15141 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
15144 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
15149 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
15150 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
15153 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
15158 #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
15159 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
15162 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
15167 #define ENET_TIPG_IPG_MASK (0x1FU)
15168 #define ENET_TIPG_IPG_SHIFT (0U)
15171 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
15176 #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
15177 #define ENET_FTRL_TRUNC_FL_SHIFT (0U)
15180 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
15185 #define ENET_TACC_SHIFT16_MASK (0x1U)
15186 #define ENET_TACC_SHIFT16_SHIFT (0U)
15194 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
15195 #define ENET_TACC_IPCHK_MASK (0x8U)
15196 #define ENET_TACC_IPCHK_SHIFT (3U)
15202 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
15203 #define ENET_TACC_PROCHK_MASK (0x10U)
15204 #define ENET_TACC_PROCHK_SHIFT (4U)
15210 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
15215 #define ENET_RACC_PADREM_MASK (0x1U)
15216 #define ENET_RACC_PADREM_SHIFT (0U)
15221 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
15222 #define ENET_RACC_IPDIS_MASK (0x2U)
15223 #define ENET_RACC_IPDIS_SHIFT (1U)
15230 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
15231 #define ENET_RACC_PRODIS_MASK (0x4U)
15232 #define ENET_RACC_PRODIS_SHIFT (2U)
15239 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
15240 #define ENET_RACC_LINEDIS_MASK (0x40U)
15241 #define ENET_RACC_LINEDIS_SHIFT (6U)
15246 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
15247 #define ENET_RACC_SHIFT16_MASK (0x80U)
15248 #define ENET_RACC_SHIFT16_SHIFT (7U)
15253 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
15258 #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
15259 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
15262 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
15267 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
15268 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
15271 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
15276 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
15277 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
15280 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
15285 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
15286 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
15289 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
15294 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
15295 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
15298 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
15303 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
15304 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
15307 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
15312 #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
15313 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
15316 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
15321 #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
15322 #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
15325 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
15330 #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
15331 #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
15334 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
15339 #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
15340 #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
15343 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
15348 #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
15349 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
15352 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
15357 #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
15358 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
15361 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
15366 #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
15367 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
15370 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
15375 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
15376 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
15379 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
15384 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
15385 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
15388 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
15393 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
15394 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
15397 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
15402 #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
15403 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
15406 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
15411 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
15412 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
15415 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
15420 #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
15421 #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
15424 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
15429 #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
15430 #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
15433 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
15438 #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
15439 #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
15442 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
15447 #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
15448 #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
15451 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
15456 #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
15457 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
15460 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
15465 #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
15466 #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
15469 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
15474 #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
15475 #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
15478 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
15483 #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
15484 #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
15485 #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
15490 #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
15491 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
15494 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
15499 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
15500 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
15503 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
15508 #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
15509 #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
15512 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
15517 #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
15518 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
15521 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
15526 #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
15527 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
15530 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
15535 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
15536 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
15539 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
15544 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
15545 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
15548 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
15553 #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
15554 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
15557 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
15562 #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
15563 #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
15566 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
15571 #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
15572 #define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
15575 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
15580 #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
15581 #define ENET_RMON_R_P64_COUNT_SHIFT (0U)
15584 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
15589 #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
15590 #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
15593 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
15598 #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
15599 #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
15602 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
15607 #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
15608 #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
15611 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
15616 #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
15617 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
15620 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
15625 #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
15626 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
15629 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
15634 #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
15635 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
15638 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
15643 #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
15644 #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
15647 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
15652 #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
15653 #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
15656 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
15661 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
15662 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
15665 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
15670 #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
15671 #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
15674 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
15679 #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
15680 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
15683 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
15688 #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
15689 #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
15692 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
15697 #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
15698 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
15701 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
15706 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
15707 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
15710 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
15715 #define ENET_ATCR_EN_MASK (0x1U)
15716 #define ENET_ATCR_EN_SHIFT (0U)
15721 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
15722 #define ENET_ATCR_OFFEN_MASK (0x4U)
15723 #define ENET_ATCR_OFFEN_SHIFT (2U)
15730 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
15731 #define ENET_ATCR_OFFRST_MASK (0x8U)
15732 #define ENET_ATCR_OFFRST_SHIFT (3U)
15737 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
15738 #define ENET_ATCR_PEREN_MASK (0x10U)
15739 #define ENET_ATCR_PEREN_SHIFT (4U)
15746 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
15747 #define ENET_ATCR_PINPER_MASK (0x80U)
15748 #define ENET_ATCR_PINPER_SHIFT (7U)
15753 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
15754 #define ENET_ATCR_RESTART_MASK (0x200U)
15755 #define ENET_ATCR_RESTART_SHIFT (9U)
15758 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
15759 #define ENET_ATCR_CAPTURE_MASK (0x800U)
15760 #define ENET_ATCR_CAPTURE_SHIFT (11U)
15765 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
15766 #define ENET_ATCR_SLAVE_MASK (0x2000U)
15767 #define ENET_ATCR_SLAVE_SHIFT (13U)
15773 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
15778 #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
15779 #define ENET_ATVR_ATIME_SHIFT (0U)
15780 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
15785 #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
15786 #define ENET_ATOFF_OFFSET_SHIFT (0U)
15787 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
15792 #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
15793 #define ENET_ATPER_PERIOD_SHIFT (0U)
15794 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
15799 #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
15800 #define ENET_ATCOR_COR_SHIFT (0U)
15803 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
15808 #define ENET_ATINC_INC_MASK (0x7FU)
15809 #define ENET_ATINC_INC_SHIFT (0U)
15812 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
15813 #define ENET_ATINC_INC_CORR_MASK (0x7F00U)
15814 #define ENET_ATINC_INC_CORR_SHIFT (8U)
15817 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
15822 #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
15823 #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
15824 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
15829 #define ENET_TGSR_TF0_MASK (0x1U)
15830 #define ENET_TGSR_TF0_SHIFT (0U)
15835 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
15836 #define ENET_TGSR_TF1_MASK (0x2U)
15837 #define ENET_TGSR_TF1_SHIFT (1U)
15842 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
15843 #define ENET_TGSR_TF2_MASK (0x4U)
15844 #define ENET_TGSR_TF2_SHIFT (2U)
15849 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
15850 #define ENET_TGSR_TF3_MASK (0x8U)
15851 #define ENET_TGSR_TF3_SHIFT (3U)
15856 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
15861 #define ENET_TCSR_TDRE_MASK (0x1U)
15862 #define ENET_TCSR_TDRE_SHIFT (0U)
15867 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
15868 #define ENET_TCSR_TMODE_MASK (0x3CU)
15869 #define ENET_TCSR_TMODE_SHIFT (2U)
15886 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
15887 #define ENET_TCSR_TIE_MASK (0x40U)
15888 #define ENET_TCSR_TIE_SHIFT (6U)
15893 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
15894 #define ENET_TCSR_TF_MASK (0x80U)
15895 #define ENET_TCSR_TF_SHIFT (7U)
15900 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
15901 #define ENET_TCSR_TPWC_MASK (0xF800U)
15902 #define ENET_TCSR_TPWC_SHIFT (11U)
15910 #define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
15913 /* The count of ENET_TCSR */
15914 #define ENET_TCSR_COUNT (4U)
15915 
15918 #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
15919 #define ENET_TCCR_TCC_SHIFT (0U)
15922 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
15925 /* The count of ENET_TCCR */
15926 #define ENET_TCCR_COUNT (4U)
15927 
15928  /* end of group ENET_Register_Masks */
15932 
15933 
15934 /* ENET - Peripheral instance base addresses */
15936 #define ENET_BASE (0x402D8000u)
15938 #define ENET ((ENET_Type *)ENET_BASE)
15940 #define ENET_BASE_ADDRS { ENET_BASE }
15942 #define ENET_BASE_PTRS { ENET }
15944 #define ENET_Transmit_IRQS { ENET_IRQn }
15945 #define ENET_Receive_IRQS { ENET_IRQn }
15946 #define ENET_Error_IRQS { ENET_IRQn }
15947 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
15948 /* ENET Buffer Descriptor and Buffer Address Alignment. */
15949 #define ENET_BUFF_ALIGNMENT (64U)
15950 
15951  /* end of group ENET_Peripheral_Access_Layer */
15955 
15956 
15957 /* ----------------------------------------------------------------------------
15958  -- EWM Peripheral Access Layer
15959  ---------------------------------------------------------------------------- */
15960 
15967 typedef struct {
15968  __IO uint8_t CTRL;
15969  __O uint8_t SERV;
15970  __IO uint8_t CMPL;
15971  __IO uint8_t CMPH;
15972  __IO uint8_t CLKCTRL;
15973  __IO uint8_t CLKPRESCALER;
15974 } EWM_Type;
15975 
15976 /* ----------------------------------------------------------------------------
15977  -- EWM Register Masks
15978  ---------------------------------------------------------------------------- */
15979 
15987 #define EWM_CTRL_EWMEN_MASK (0x1U)
15988 #define EWM_CTRL_EWMEN_SHIFT (0U)
15991 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
15992 #define EWM_CTRL_ASSIN_MASK (0x2U)
15993 #define EWM_CTRL_ASSIN_SHIFT (1U)
15996 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
15997 #define EWM_CTRL_INEN_MASK (0x4U)
15998 #define EWM_CTRL_INEN_SHIFT (2U)
16001 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
16002 #define EWM_CTRL_INTEN_MASK (0x8U)
16003 #define EWM_CTRL_INTEN_SHIFT (3U)
16006 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
16011 #define EWM_SERV_SERVICE_MASK (0xFFU)
16012 #define EWM_SERV_SERVICE_SHIFT (0U)
16015 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
16020 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
16021 #define EWM_CMPL_COMPAREL_SHIFT (0U)
16024 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
16029 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
16030 #define EWM_CMPH_COMPAREH_SHIFT (0U)
16033 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
16038 #define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
16039 #define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
16042 #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
16047 #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
16048 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
16051 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) /* end of group EWM_Register_Masks */
16058 
16059 
16060 /* EWM - Peripheral instance base addresses */
16062 #define EWM_BASE (0x400B4000u)
16064 #define EWM ((EWM_Type *)EWM_BASE)
16066 #define EWM_BASE_ADDRS { EWM_BASE }
16068 #define EWM_BASE_PTRS { EWM }
16070 #define EWM_IRQS { EWM_IRQn }
16071  /* end of group EWM_Peripheral_Access_Layer */
16075 
16076 
16077 /* ----------------------------------------------------------------------------
16078  -- FLEXIO Peripheral Access Layer
16079  ---------------------------------------------------------------------------- */
16080 
16087 typedef struct {
16088  __I uint32_t VERID;
16089  __I uint32_t PARAM;
16090  __IO uint32_t CTRL;
16091  __I uint32_t PIN;
16092  __IO uint32_t SHIFTSTAT;
16093  __IO uint32_t SHIFTERR;
16094  __IO uint32_t TIMSTAT;
16095  uint8_t RESERVED_0[4];
16096  __IO uint32_t SHIFTSIEN;
16097  __IO uint32_t SHIFTEIEN;
16098  __IO uint32_t TIMIEN;
16099  uint8_t RESERVED_1[4];
16100  __IO uint32_t SHIFTSDEN;
16101  uint8_t RESERVED_2[12];
16102  __IO uint32_t SHIFTSTATE;
16103  uint8_t RESERVED_3[60];
16104  __IO uint32_t SHIFTCTL[8];
16105  uint8_t RESERVED_4[96];
16106  __IO uint32_t SHIFTCFG[8];
16107  uint8_t RESERVED_5[224];
16108  __IO uint32_t SHIFTBUF[8];
16109  uint8_t RESERVED_6[96];
16110  __IO uint32_t SHIFTBUFBIS[8];
16111  uint8_t RESERVED_7[96];
16112  __IO uint32_t SHIFTBUFBYS[8];
16113  uint8_t RESERVED_8[96];
16114  __IO uint32_t SHIFTBUFBBS[8];
16115  uint8_t RESERVED_9[96];
16116  __IO uint32_t TIMCTL[8];
16117  uint8_t RESERVED_10[96];
16118  __IO uint32_t TIMCFG[8];
16119  uint8_t RESERVED_11[96];
16120  __IO uint32_t TIMCMP[8];
16121  uint8_t RESERVED_12[352];
16122  __IO uint32_t SHIFTBUFNBS[8];
16123  uint8_t RESERVED_13[96];
16124  __IO uint32_t SHIFTBUFHWS[8];
16125  uint8_t RESERVED_14[96];
16126  __IO uint32_t SHIFTBUFNIS[8];
16127 } FLEXIO_Type;
16128 
16129 /* ----------------------------------------------------------------------------
16130  -- FLEXIO Register Masks
16131  ---------------------------------------------------------------------------- */
16132 
16140 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
16141 #define FLEXIO_VERID_FEATURE_SHIFT (0U)
16146 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
16147 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
16148 #define FLEXIO_VERID_MINOR_SHIFT (16U)
16151 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
16152 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
16153 #define FLEXIO_VERID_MAJOR_SHIFT (24U)
16156 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
16161 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
16162 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
16165 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
16166 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
16167 #define FLEXIO_PARAM_TIMER_SHIFT (8U)
16170 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
16171 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
16172 #define FLEXIO_PARAM_PIN_SHIFT (16U)
16175 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
16176 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
16177 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
16180 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
16185 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
16186 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
16191 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
16192 #define FLEXIO_CTRL_SWRST_MASK (0x2U)
16193 #define FLEXIO_CTRL_SWRST_SHIFT (1U)
16198 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
16199 #define FLEXIO_CTRL_FASTACC_MASK (0x4U)
16200 #define FLEXIO_CTRL_FASTACC_SHIFT (2U)
16205 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
16206 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
16207 #define FLEXIO_CTRL_DBGE_SHIFT (30U)
16212 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
16213 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
16214 #define FLEXIO_CTRL_DOZEN_SHIFT (31U)
16219 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
16224 #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
16225 #define FLEXIO_PIN_PDI_SHIFT (0U)
16228 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
16233 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
16234 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
16237 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
16242 #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
16243 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
16246 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
16251 #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
16252 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
16255 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
16260 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
16261 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
16264 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
16269 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
16270 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
16273 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
16278 #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
16279 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
16282 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
16287 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
16288 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
16291 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
16296 #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
16297 #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
16300 #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
16305 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
16306 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
16317 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
16318 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
16319 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
16324 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
16325 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
16326 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
16329 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
16330 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
16331 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
16338 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
16339 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
16340 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
16345 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
16346 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
16347 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
16350 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
16353 /* The count of FLEXIO_SHIFTCTL */
16354 #define FLEXIO_SHIFTCTL_COUNT (8U)
16355 
16358 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
16359 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
16366 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
16367 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
16368 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
16375 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
16376 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
16377 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
16382 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
16383 #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
16384 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
16387 #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
16390 /* The count of FLEXIO_SHIFTCFG */
16391 #define FLEXIO_SHIFTCFG_COUNT (8U)
16392 
16395 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
16396 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
16399 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
16402 /* The count of FLEXIO_SHIFTBUF */
16403 #define FLEXIO_SHIFTBUF_COUNT (8U)
16404 
16407 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
16408 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
16411 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
16414 /* The count of FLEXIO_SHIFTBUFBIS */
16415 #define FLEXIO_SHIFTBUFBIS_COUNT (8U)
16416 
16419 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
16420 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
16423 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
16426 /* The count of FLEXIO_SHIFTBUFBYS */
16427 #define FLEXIO_SHIFTBUFBYS_COUNT (8U)
16428 
16431 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
16432 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
16435 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
16438 /* The count of FLEXIO_SHIFTBUFBBS */
16439 #define FLEXIO_SHIFTBUFBBS_COUNT (8U)
16440 
16443 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
16444 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
16451 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
16452 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
16453 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
16458 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
16459 #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
16460 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
16463 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
16464 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
16465 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
16472 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
16473 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
16474 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
16479 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
16480 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
16481 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
16486 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
16487 #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
16488 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
16491 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
16494 /* The count of FLEXIO_TIMCTL */
16495 #define FLEXIO_TIMCTL_COUNT (8U)
16496 
16499 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
16500 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
16505 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
16506 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
16507 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
16514 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
16515 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
16516 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
16527 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
16528 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
16529 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
16540 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
16541 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
16542 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
16553 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
16554 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
16555 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
16562 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
16563 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
16564 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
16571 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
16574 /* The count of FLEXIO_TIMCFG */
16575 #define FLEXIO_TIMCFG_COUNT (8U)
16576 
16579 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
16580 #define FLEXIO_TIMCMP_CMP_SHIFT (0U)
16583 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
16586 /* The count of FLEXIO_TIMCMP */
16587 #define FLEXIO_TIMCMP_COUNT (8U)
16588 
16591 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
16592 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
16595 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
16598 /* The count of FLEXIO_SHIFTBUFNBS */
16599 #define FLEXIO_SHIFTBUFNBS_COUNT (8U)
16600 
16603 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
16604 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
16607 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
16610 /* The count of FLEXIO_SHIFTBUFHWS */
16611 #define FLEXIO_SHIFTBUFHWS_COUNT (8U)
16612 
16615 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
16616 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
16619 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
16622 /* The count of FLEXIO_SHIFTBUFNIS */
16623 #define FLEXIO_SHIFTBUFNIS_COUNT (8U)
16624 
16625  /* end of group FLEXIO_Register_Masks */
16629 
16630 
16631 /* FLEXIO - Peripheral instance base addresses */
16633 #define FLEXIO1_BASE (0x401AC000u)
16635 #define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
16637 #define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE }
16639 #define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1 }
16641 #define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn }
16642  /* end of group FLEXIO_Peripheral_Access_Layer */
16646 
16647 
16648 /* ----------------------------------------------------------------------------
16649  -- FLEXRAM Peripheral Access Layer
16650  ---------------------------------------------------------------------------- */
16651 
16658 typedef struct {
16659  __IO uint32_t TCM_CTRL;
16660  uint8_t RESERVED_0[12];
16661  __IO uint32_t INT_STATUS;
16662  __IO uint32_t INT_STAT_EN;
16663  __IO uint32_t INT_SIG_EN;
16664 } FLEXRAM_Type;
16665 
16666 /* ----------------------------------------------------------------------------
16667  -- FLEXRAM Register Masks
16668  ---------------------------------------------------------------------------- */
16669 
16677 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
16678 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
16683 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
16684 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
16685 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
16690 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
16691 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
16692 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
16695 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
16700 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
16701 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
16706 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
16707 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
16708 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
16713 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
16714 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
16715 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
16720 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
16725 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
16726 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
16731 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
16732 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
16733 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
16738 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
16739 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
16740 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
16745 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
16750 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
16751 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
16756 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
16757 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
16758 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
16763 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
16764 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
16765 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
16770 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) /* end of group FLEXRAM_Register_Masks */
16777 
16778 
16779 /* FLEXRAM - Peripheral instance base addresses */
16781 #define FLEXRAM_BASE (0x400B0000u)
16783 #define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
16785 #define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
16787 #define FLEXRAM_BASE_PTRS { FLEXRAM }
16789 #define FLEXRAM_IRQS { FLEXRAM_IRQn }
16790  /* end of group FLEXRAM_Peripheral_Access_Layer */
16794 
16795 
16796 /* ----------------------------------------------------------------------------
16797  -- FLEXSPI Peripheral Access Layer
16798  ---------------------------------------------------------------------------- */
16799 
16806 typedef struct {
16807  __IO uint32_t MCR0;
16808  __IO uint32_t MCR1;
16809  __IO uint32_t MCR2;
16810  __IO uint32_t AHBCR;
16811  __IO uint32_t INTEN;
16812  __IO uint32_t INTR;
16813  __IO uint32_t LUTKEY;
16814  __IO uint32_t LUTCR;
16815  __IO uint32_t AHBRXBUFCR0[4];
16816  uint8_t RESERVED_0[48];
16817  __IO uint32_t FLSHCR0[4];
16818  __IO uint32_t FLSHCR1[4];
16819  __IO uint32_t FLSHCR2[4];
16820  uint8_t RESERVED_1[4];
16821  __IO uint32_t FLSHCR4;
16822  uint8_t RESERVED_2[8];
16823  __IO uint32_t IPCR0;
16824  __IO uint32_t IPCR1;
16825  uint8_t RESERVED_3[8];
16826  __IO uint32_t IPCMD;
16827  uint8_t RESERVED_4[4];
16828  __IO uint32_t IPRXFCR;
16829  __IO uint32_t IPTXFCR;
16830  __IO uint32_t DLLCR[2];
16831  uint8_t RESERVED_5[24];
16832  __I uint32_t STS0;
16833  __I uint32_t STS1;
16834  __I uint32_t STS2;
16835  __I uint32_t AHBSPNDSTS;
16836  __I uint32_t IPRXFSTS;
16837  __I uint32_t IPTXFSTS;
16838  uint8_t RESERVED_6[8];
16839  __I uint32_t RFDR[32];
16840  __O uint32_t TFDR[32];
16841  __IO uint32_t LUT[64];
16842 } FLEXSPI_Type;
16843 
16844 /* ----------------------------------------------------------------------------
16845  -- FLEXSPI Register Masks
16846  ---------------------------------------------------------------------------- */
16847 
16855 #define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
16856 #define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
16859 #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
16860 #define FLEXSPI_MCR0_MDIS_MASK (0x2U)
16861 #define FLEXSPI_MCR0_MDIS_SHIFT (1U)
16864 #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
16865 #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
16866 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
16873 #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
16874 #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
16875 #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
16880 #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
16881 #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
16882 #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
16887 #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
16888 #define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U)
16889 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U)
16900 #define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
16901 #define FLEXSPI_MCR0_HSEN_MASK (0x800U)
16902 #define FLEXSPI_MCR0_HSEN_SHIFT (11U)
16907 #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
16908 #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
16909 #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
16914 #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
16915 #define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
16916 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
16921 #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
16922 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
16923 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
16930 #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
16931 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
16932 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
16935 #define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
16936 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
16937 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
16940 #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
16945 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
16946 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
16947 #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
16948 #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
16949 #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
16950 #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
16955 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
16956 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
16964 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
16965 #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
16966 #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
16970 #define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
16971 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
16972 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
16980 #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
16981 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
16982 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
16989 #define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
16990 #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
16991 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
16994 #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
16999 #define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
17000 #define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
17005 #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
17006 #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
17007 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
17012 #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
17013 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
17014 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
17022 #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
17023 #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
17024 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
17027 #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
17028 #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
17029 #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
17035 #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
17040 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
17041 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
17044 #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
17045 #define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
17046 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
17049 #define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
17050 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
17051 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
17054 #define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
17055 #define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
17056 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
17059 #define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
17060 #define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
17061 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
17064 #define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
17065 #define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
17066 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
17069 #define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
17070 #define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
17071 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
17074 #define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
17075 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
17076 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
17079 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
17080 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
17081 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
17084 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
17085 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
17086 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
17089 #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
17090 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
17091 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
17094 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
17099 #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
17100 #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
17104 #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
17105 #define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
17106 #define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
17109 #define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
17110 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
17111 #define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
17114 #define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
17115 #define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
17116 #define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
17120 #define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
17121 #define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
17122 #define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
17126 #define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
17127 #define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
17128 #define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
17131 #define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
17132 #define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
17133 #define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
17136 #define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
17137 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
17138 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
17141 #define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
17142 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
17143 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
17146 #define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
17147 #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
17148 #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
17151 #define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
17152 #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
17153 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
17156 #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
17161 #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
17162 #define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
17165 #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
17170 #define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
17171 #define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
17174 #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
17175 #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
17176 #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
17179 #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
17184 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)
17185 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
17188 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
17189 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
17190 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
17193 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
17194 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)
17195 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
17198 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
17199 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
17200 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
17203 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
17206 /* The count of FLEXSPI_AHBRXBUFCR0 */
17207 #define FLEXSPI_AHBRXBUFCR0_COUNT (4U)
17208 
17211 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
17212 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
17215 #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
17218 /* The count of FLEXSPI_FLSHCR0 */
17219 #define FLEXSPI_FLSHCR0_COUNT (4U)
17220 
17223 #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
17224 #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
17227 #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
17228 #define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
17229 #define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
17232 #define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
17233 #define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
17234 #define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
17237 #define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
17238 #define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
17239 #define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
17242 #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
17243 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
17244 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
17249 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
17250 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
17251 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
17257 #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
17260 /* The count of FLEXSPI_FLSHCR1 */
17261 #define FLEXSPI_FLSHCR1_COUNT (4U)
17262 
17265 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
17266 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
17269 #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
17270 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
17271 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
17274 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
17275 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
17276 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
17279 #define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
17280 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
17281 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
17284 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
17285 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
17286 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
17287 #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
17288 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
17289 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
17300 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
17301 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
17302 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
17306 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
17309 /* The count of FLEXSPI_FLSHCR2 */
17310 #define FLEXSPI_FLSHCR2_COUNT (4U)
17311 
17314 #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
17315 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
17322 #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
17323 #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
17324 #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
17330 #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
17331 #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
17332 #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
17338 #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
17343 #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
17344 #define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
17347 #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
17352 #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
17353 #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
17356 #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
17357 #define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
17358 #define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
17361 #define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
17362 #define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
17363 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
17366 #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
17367 #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
17368 #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
17373 #define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
17378 #define FLEXSPI_IPCMD_TRG_MASK (0x1U)
17379 #define FLEXSPI_IPCMD_TRG_SHIFT (0U)
17382 #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
17387 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
17388 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
17391 #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
17392 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
17393 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
17398 #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
17399 #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)
17400 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
17403 #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
17408 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
17409 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
17412 #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
17413 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
17414 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
17419 #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
17420 #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)
17421 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
17424 #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
17429 #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
17430 #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
17433 #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
17434 #define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
17435 #define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
17441 #define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
17442 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
17443 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
17448 #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
17449 #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
17450 #define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
17453 #define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
17454 #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
17455 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
17458 #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
17461 /* The count of FLEXSPI_DLLCR */
17462 #define FLEXSPI_DLLCR_COUNT (2U)
17463 
17466 #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
17467 #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
17471 #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
17472 #define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
17473 #define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
17479 #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
17480 #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
17481 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
17489 #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
17494 #define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
17495 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
17499 #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
17500 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
17501 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
17511 #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
17512 #define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
17513 #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
17517 #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
17518 #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
17519 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
17531 #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
17536 #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
17537 #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
17540 #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
17541 #define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
17542 #define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
17545 #define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
17546 #define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
17547 #define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
17550 #define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
17551 #define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
17552 #define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
17555 #define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
17556 #define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
17557 #define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
17560 #define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
17561 #define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
17562 #define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
17565 #define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
17566 #define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
17567 #define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
17570 #define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
17571 #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
17572 #define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
17575 #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
17580 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
17581 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
17584 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
17585 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
17586 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
17589 #define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
17590 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
17591 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
17594 #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
17599 #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
17600 #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
17603 #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
17604 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
17605 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
17608 #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
17613 #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
17614 #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
17617 #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
17618 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
17619 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
17622 #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
17627 #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
17628 #define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
17631 #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
17634 /* The count of FLEXSPI_RFDR */
17635 #define FLEXSPI_RFDR_COUNT (32U)
17636 
17639 #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
17640 #define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
17643 #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
17646 /* The count of FLEXSPI_TFDR */
17647 #define FLEXSPI_TFDR_COUNT (32U)
17648 
17651 #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
17652 #define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
17655 #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
17656 #define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
17657 #define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
17660 #define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
17661 #define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
17662 #define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
17665 #define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
17666 #define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
17667 #define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
17670 #define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
17671 #define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
17672 #define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
17675 #define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
17676 #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
17677 #define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
17680 #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
17683 /* The count of FLEXSPI_LUT */
17684 #define FLEXSPI_LUT_COUNT (64U)
17685 
17686  /* end of group FLEXSPI_Register_Masks */
17690 
17691 
17692 /* FLEXSPI - Peripheral instance base addresses */
17694 #define FLEXSPI_BASE (0x402A8000u)
17696 #define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
17698 #define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE }
17700 #define FLEXSPI_BASE_PTRS { FLEXSPI }
17702 #define FLEXSPI_IRQS { FLEXSPI_IRQn }
17703 /* FlexSPI AMBA address. */
17704 #define FlexSPI_AMBA_BASE (0x60000000U)
17705 /* FlexSPI ASFM address. */
17706 #define FlexSPI_ASFM_BASE (0x60000000U)
17707 /* Base Address of AHB address space mapped to IP RX FIFO. */
17708 #define FlexSPI_ARDF_BASE (0x7FC00000U)
17709 /* Base Address of AHB address space mapped to IP TX FIFO. */
17710 #define FlexSPI_ATDF_BASE (0x7F800000U)
17711 
17712  /* end of group FLEXSPI_Peripheral_Access_Layer */
17716 
17717 
17718 /* ----------------------------------------------------------------------------
17719  -- GPC Peripheral Access Layer
17720  ---------------------------------------------------------------------------- */
17721 
17728 typedef struct {
17729  __IO uint32_t CNTR;
17730  uint8_t RESERVED_0[4];
17731  __IO uint32_t IMR[4];
17732  __I uint32_t ISR[4];
17733  uint8_t RESERVED_1[12];
17734  __IO uint32_t IMR5;
17735  __I uint32_t ISR5;
17736 } GPC_Type;
17737 
17738 /* ----------------------------------------------------------------------------
17739  -- GPC Register Masks
17740  ---------------------------------------------------------------------------- */
17741 
17749 #define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
17750 #define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
17755 #define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
17756 #define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
17757 #define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
17762 #define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
17763 #define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
17764 #define GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
17769 #define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
17774 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
17775 #define GPC_IMR_IMR1_SHIFT (0U)
17776 #define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
17777 #define GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
17778 #define GPC_IMR_IMR2_SHIFT (0U)
17779 #define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
17780 #define GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
17781 #define GPC_IMR_IMR3_SHIFT (0U)
17782 #define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
17783 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
17784 #define GPC_IMR_IMR4_SHIFT (0U)
17785 #define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
17788 /* The count of GPC_IMR */
17789 #define GPC_IMR_COUNT (4U)
17790 
17793 #define GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
17794 #define GPC_ISR_ISR1_SHIFT (0U)
17795 #define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
17796 #define GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
17797 #define GPC_ISR_ISR2_SHIFT (0U)
17798 #define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
17799 #define GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
17800 #define GPC_ISR_ISR3_SHIFT (0U)
17801 #define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
17802 #define GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
17803 #define GPC_ISR_ISR4_SHIFT (0U)
17804 #define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
17807 /* The count of GPC_ISR */
17808 #define GPC_ISR_COUNT (4U)
17809 
17812 #define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
17813 #define GPC_IMR5_IMR5_SHIFT (0U)
17814 #define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
17819 #define GPC_ISR5_ISR5_MASK (0xFFFFFFFFU)
17820 #define GPC_ISR5_ISR5_SHIFT (0U)
17821 #define GPC_ISR5_ISR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR5_SHIFT)) & GPC_ISR5_ISR5_MASK) /* end of group GPC_Register_Masks */
17828 
17829 
17830 /* GPC - Peripheral instance base addresses */
17832 #define GPC_BASE (0x400F4000u)
17834 #define GPC ((GPC_Type *)GPC_BASE)
17836 #define GPC_BASE_ADDRS { GPC_BASE }
17838 #define GPC_BASE_PTRS { GPC }
17840 #define GPC_IRQS { GPC_IRQn }
17841  /* end of group GPC_Peripheral_Access_Layer */
17845 
17846 
17847 /* ----------------------------------------------------------------------------
17848  -- GPIO Peripheral Access Layer
17849  ---------------------------------------------------------------------------- */
17850 
17857 typedef struct {
17858  __IO uint32_t DR;
17859  __IO uint32_t GDIR;
17860  __I uint32_t PSR;
17861  __IO uint32_t ICR1;
17862  __IO uint32_t ICR2;
17863  __IO uint32_t IMR;
17864  __IO uint32_t ISR;
17865  __IO uint32_t EDGE_SEL;
17866  uint8_t RESERVED_0[100];
17867  __O uint32_t DR_SET;
17868  __O uint32_t DR_CLEAR;
17869  __O uint32_t DR_TOGGLE;
17870 } GPIO_Type;
17871 
17872 /* ----------------------------------------------------------------------------
17873  -- GPIO Register Masks
17874  ---------------------------------------------------------------------------- */
17875 
17883 #define GPIO_DR_DR_MASK (0xFFFFFFFFU)
17884 #define GPIO_DR_DR_SHIFT (0U)
17887 #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
17892 #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
17893 #define GPIO_GDIR_GDIR_SHIFT (0U)
17896 #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
17901 #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
17902 #define GPIO_PSR_PSR_SHIFT (0U)
17905 #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
17910 #define GPIO_ICR1_ICR0_MASK (0x3U)
17911 #define GPIO_ICR1_ICR0_SHIFT (0U)
17918 #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
17919 #define GPIO_ICR1_ICR1_MASK (0xCU)
17920 #define GPIO_ICR1_ICR1_SHIFT (2U)
17927 #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
17928 #define GPIO_ICR1_ICR2_MASK (0x30U)
17929 #define GPIO_ICR1_ICR2_SHIFT (4U)
17936 #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
17937 #define GPIO_ICR1_ICR3_MASK (0xC0U)
17938 #define GPIO_ICR1_ICR3_SHIFT (6U)
17945 #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
17946 #define GPIO_ICR1_ICR4_MASK (0x300U)
17947 #define GPIO_ICR1_ICR4_SHIFT (8U)
17954 #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
17955 #define GPIO_ICR1_ICR5_MASK (0xC00U)
17956 #define GPIO_ICR1_ICR5_SHIFT (10U)
17963 #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
17964 #define GPIO_ICR1_ICR6_MASK (0x3000U)
17965 #define GPIO_ICR1_ICR6_SHIFT (12U)
17972 #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
17973 #define GPIO_ICR1_ICR7_MASK (0xC000U)
17974 #define GPIO_ICR1_ICR7_SHIFT (14U)
17981 #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
17982 #define GPIO_ICR1_ICR8_MASK (0x30000U)
17983 #define GPIO_ICR1_ICR8_SHIFT (16U)
17990 #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
17991 #define GPIO_ICR1_ICR9_MASK (0xC0000U)
17992 #define GPIO_ICR1_ICR9_SHIFT (18U)
17999 #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
18000 #define GPIO_ICR1_ICR10_MASK (0x300000U)
18001 #define GPIO_ICR1_ICR10_SHIFT (20U)
18008 #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
18009 #define GPIO_ICR1_ICR11_MASK (0xC00000U)
18010 #define GPIO_ICR1_ICR11_SHIFT (22U)
18017 #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
18018 #define GPIO_ICR1_ICR12_MASK (0x3000000U)
18019 #define GPIO_ICR1_ICR12_SHIFT (24U)
18026 #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
18027 #define GPIO_ICR1_ICR13_MASK (0xC000000U)
18028 #define GPIO_ICR1_ICR13_SHIFT (26U)
18035 #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
18036 #define GPIO_ICR1_ICR14_MASK (0x30000000U)
18037 #define GPIO_ICR1_ICR14_SHIFT (28U)
18044 #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
18045 #define GPIO_ICR1_ICR15_MASK (0xC0000000U)
18046 #define GPIO_ICR1_ICR15_SHIFT (30U)
18053 #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
18058 #define GPIO_ICR2_ICR16_MASK (0x3U)
18059 #define GPIO_ICR2_ICR16_SHIFT (0U)
18066 #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
18067 #define GPIO_ICR2_ICR17_MASK (0xCU)
18068 #define GPIO_ICR2_ICR17_SHIFT (2U)
18075 #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
18076 #define GPIO_ICR2_ICR18_MASK (0x30U)
18077 #define GPIO_ICR2_ICR18_SHIFT (4U)
18084 #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
18085 #define GPIO_ICR2_ICR19_MASK (0xC0U)
18086 #define GPIO_ICR2_ICR19_SHIFT (6U)
18093 #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
18094 #define GPIO_ICR2_ICR20_MASK (0x300U)
18095 #define GPIO_ICR2_ICR20_SHIFT (8U)
18102 #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
18103 #define GPIO_ICR2_ICR21_MASK (0xC00U)
18104 #define GPIO_ICR2_ICR21_SHIFT (10U)
18111 #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
18112 #define GPIO_ICR2_ICR22_MASK (0x3000U)
18113 #define GPIO_ICR2_ICR22_SHIFT (12U)
18120 #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
18121 #define GPIO_ICR2_ICR23_MASK (0xC000U)
18122 #define GPIO_ICR2_ICR23_SHIFT (14U)
18129 #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
18130 #define GPIO_ICR2_ICR24_MASK (0x30000U)
18131 #define GPIO_ICR2_ICR24_SHIFT (16U)
18138 #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
18139 #define GPIO_ICR2_ICR25_MASK (0xC0000U)
18140 #define GPIO_ICR2_ICR25_SHIFT (18U)
18147 #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
18148 #define GPIO_ICR2_ICR26_MASK (0x300000U)
18149 #define GPIO_ICR2_ICR26_SHIFT (20U)
18156 #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
18157 #define GPIO_ICR2_ICR27_MASK (0xC00000U)
18158 #define GPIO_ICR2_ICR27_SHIFT (22U)
18165 #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
18166 #define GPIO_ICR2_ICR28_MASK (0x3000000U)
18167 #define GPIO_ICR2_ICR28_SHIFT (24U)
18174 #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
18175 #define GPIO_ICR2_ICR29_MASK (0xC000000U)
18176 #define GPIO_ICR2_ICR29_SHIFT (26U)
18183 #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
18184 #define GPIO_ICR2_ICR30_MASK (0x30000000U)
18185 #define GPIO_ICR2_ICR30_SHIFT (28U)
18192 #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
18193 #define GPIO_ICR2_ICR31_MASK (0xC0000000U)
18194 #define GPIO_ICR2_ICR31_SHIFT (30U)
18201 #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
18206 #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
18207 #define GPIO_IMR_IMR_SHIFT (0U)
18210 #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
18215 #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
18216 #define GPIO_ISR_ISR_SHIFT (0U)
18219 #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
18224 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
18225 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
18228 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
18233 #define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
18234 #define GPIO_DR_SET_DR_SET_SHIFT (0U)
18237 #define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
18242 #define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
18243 #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
18246 #define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
18251 #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
18252 #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
18255 #define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) /* end of group GPIO_Register_Masks */
18262 
18263 
18264 /* GPIO - Peripheral instance base addresses */
18266 #define GPIO1_BASE (0x401B8000u)
18268 #define GPIO1 ((GPIO_Type *)GPIO1_BASE)
18270 #define GPIO2_BASE (0x401BC000u)
18272 #define GPIO2 ((GPIO_Type *)GPIO2_BASE)
18274 #define GPIO3_BASE (0x401C0000u)
18276 #define GPIO3 ((GPIO_Type *)GPIO3_BASE)
18278 #define GPIO5_BASE (0x400C0000u)
18280 #define GPIO5 ((GPIO_Type *)GPIO5_BASE)
18282 #define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, 0u, GPIO5_BASE }
18284 #define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, (GPIO_Type *)0u, GPIO5 }
18286 #define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
18287 #define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, NotAvail_IRQn, GPIO5_Combined_0_15_IRQn }
18288 #define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, NotAvail_IRQn, GPIO5_Combined_16_31_IRQn }
18289  /* end of group GPIO_Peripheral_Access_Layer */
18293 
18294 
18295 /* ----------------------------------------------------------------------------
18296  -- GPT Peripheral Access Layer
18297  ---------------------------------------------------------------------------- */
18298 
18305 typedef struct {
18306  __IO uint32_t CR;
18307  __IO uint32_t PR;
18308  __IO uint32_t SR;
18309  __IO uint32_t IR;
18310  __IO uint32_t OCR[3];
18311  __I uint32_t ICR[2];
18312  __I uint32_t CNT;
18313 } GPT_Type;
18314 
18315 /* ----------------------------------------------------------------------------
18316  -- GPT Register Masks
18317  ---------------------------------------------------------------------------- */
18318 
18326 #define GPT_CR_EN_MASK (0x1U)
18327 #define GPT_CR_EN_SHIFT (0U)
18332 #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
18333 #define GPT_CR_ENMOD_MASK (0x2U)
18334 #define GPT_CR_ENMOD_SHIFT (1U)
18339 #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
18340 #define GPT_CR_DBGEN_MASK (0x4U)
18341 #define GPT_CR_DBGEN_SHIFT (2U)
18346 #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
18347 #define GPT_CR_WAITEN_MASK (0x8U)
18348 #define GPT_CR_WAITEN_SHIFT (3U)
18353 #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
18354 #define GPT_CR_DOZEEN_MASK (0x10U)
18355 #define GPT_CR_DOZEEN_SHIFT (4U)
18360 #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
18361 #define GPT_CR_STOPEN_MASK (0x20U)
18362 #define GPT_CR_STOPEN_SHIFT (5U)
18367 #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
18368 #define GPT_CR_CLKSRC_MASK (0x1C0U)
18369 #define GPT_CR_CLKSRC_SHIFT (6U)
18378 #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
18379 #define GPT_CR_FRR_MASK (0x200U)
18380 #define GPT_CR_FRR_SHIFT (9U)
18385 #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
18386 #define GPT_CR_EN_24M_MASK (0x400U)
18387 #define GPT_CR_EN_24M_SHIFT (10U)
18392 #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
18393 #define GPT_CR_SWR_MASK (0x8000U)
18394 #define GPT_CR_SWR_SHIFT (15U)
18399 #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
18400 #define GPT_CR_IM1_MASK (0x30000U)
18401 #define GPT_CR_IM1_SHIFT (16U)
18402 #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
18403 #define GPT_CR_IM2_MASK (0xC0000U)
18404 #define GPT_CR_IM2_SHIFT (18U)
18411 #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
18412 #define GPT_CR_OM1_MASK (0x700000U)
18413 #define GPT_CR_OM1_SHIFT (20U)
18414 #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
18415 #define GPT_CR_OM2_MASK (0x3800000U)
18416 #define GPT_CR_OM2_SHIFT (23U)
18417 #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
18418 #define GPT_CR_OM3_MASK (0x1C000000U)
18419 #define GPT_CR_OM3_SHIFT (26U)
18427 #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
18428 #define GPT_CR_FO1_MASK (0x20000000U)
18429 #define GPT_CR_FO1_SHIFT (29U)
18430 #define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
18431 #define GPT_CR_FO2_MASK (0x40000000U)
18432 #define GPT_CR_FO2_SHIFT (30U)
18433 #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
18434 #define GPT_CR_FO3_MASK (0x80000000U)
18435 #define GPT_CR_FO3_SHIFT (31U)
18440 #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
18445 #define GPT_PR_PRESCALER_MASK (0xFFFU)
18446 #define GPT_PR_PRESCALER_SHIFT (0U)
18452 #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
18453 #define GPT_PR_PRESCALER24M_MASK (0xF000U)
18454 #define GPT_PR_PRESCALER24M_SHIFT (12U)
18460 #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
18465 #define GPT_SR_OF1_MASK (0x1U)
18466 #define GPT_SR_OF1_SHIFT (0U)
18467 #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
18468 #define GPT_SR_OF2_MASK (0x2U)
18469 #define GPT_SR_OF2_SHIFT (1U)
18470 #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
18471 #define GPT_SR_OF3_MASK (0x4U)
18472 #define GPT_SR_OF3_SHIFT (2U)
18477 #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
18478 #define GPT_SR_IF1_MASK (0x8U)
18479 #define GPT_SR_IF1_SHIFT (3U)
18480 #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
18481 #define GPT_SR_IF2_MASK (0x10U)
18482 #define GPT_SR_IF2_SHIFT (4U)
18487 #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
18488 #define GPT_SR_ROV_MASK (0x20U)
18489 #define GPT_SR_ROV_SHIFT (5U)
18494 #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
18499 #define GPT_IR_OF1IE_MASK (0x1U)
18500 #define GPT_IR_OF1IE_SHIFT (0U)
18501 #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
18502 #define GPT_IR_OF2IE_MASK (0x2U)
18503 #define GPT_IR_OF2IE_SHIFT (1U)
18504 #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
18505 #define GPT_IR_OF3IE_MASK (0x4U)
18506 #define GPT_IR_OF3IE_SHIFT (2U)
18511 #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
18512 #define GPT_IR_IF1IE_MASK (0x8U)
18513 #define GPT_IR_IF1IE_SHIFT (3U)
18514 #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
18515 #define GPT_IR_IF2IE_MASK (0x10U)
18516 #define GPT_IR_IF2IE_SHIFT (4U)
18521 #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
18522 #define GPT_IR_ROVIE_MASK (0x20U)
18523 #define GPT_IR_ROVIE_SHIFT (5U)
18528 #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
18533 #define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
18534 #define GPT_OCR_COMP_SHIFT (0U)
18535 #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
18538 /* The count of GPT_OCR */
18539 #define GPT_OCR_COUNT (3U)
18540 
18543 #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
18544 #define GPT_ICR_CAPT_SHIFT (0U)
18545 #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
18548 /* The count of GPT_ICR */
18549 #define GPT_ICR_COUNT (2U)
18550 
18553 #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
18554 #define GPT_CNT_COUNT_SHIFT (0U)
18555 #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) /* end of group GPT_Register_Masks */
18562 
18563 
18564 /* GPT - Peripheral instance base addresses */
18566 #define GPT1_BASE (0x401EC000u)
18568 #define GPT1 ((GPT_Type *)GPT1_BASE)
18570 #define GPT2_BASE (0x401F0000u)
18572 #define GPT2 ((GPT_Type *)GPT2_BASE)
18574 #define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }
18576 #define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }
18578 #define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
18579  /* end of group GPT_Peripheral_Access_Layer */
18583 
18584 
18585 /* ----------------------------------------------------------------------------
18586  -- I2S Peripheral Access Layer
18587  ---------------------------------------------------------------------------- */
18588 
18595 typedef struct {
18596  __I uint32_t VERID;
18597  __I uint32_t PARAM;
18598  __IO uint32_t TCSR;
18599  __IO uint32_t TCR1;
18600  __IO uint32_t TCR2;
18601  __IO uint32_t TCR3;
18602  __IO uint32_t TCR4;
18603  __IO uint32_t TCR5;
18604  __O uint32_t TDR[4];
18605  uint8_t RESERVED_0[16];
18606  __I uint32_t TFR[4];
18607  uint8_t RESERVED_1[16];
18608  __IO uint32_t TMR;
18609  uint8_t RESERVED_2[36];
18610  __IO uint32_t RCSR;
18611  __IO uint32_t RCR1;
18612  __IO uint32_t RCR2;
18613  __IO uint32_t RCR3;
18614  __IO uint32_t RCR4;
18615  __IO uint32_t RCR5;
18616  __I uint32_t RDR[4];
18617  uint8_t RESERVED_3[16];
18618  __I uint32_t RFR[4];
18619  uint8_t RESERVED_4[16];
18620  __IO uint32_t RMR;
18621 } I2S_Type;
18622 
18623 /* ----------------------------------------------------------------------------
18624  -- I2S Register Masks
18625  ---------------------------------------------------------------------------- */
18626 
18634 #define I2S_VERID_FEATURE_MASK (0xFFFFU)
18635 #define I2S_VERID_FEATURE_SHIFT (0U)
18639 #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
18640 #define I2S_VERID_MINOR_MASK (0xFF0000U)
18641 #define I2S_VERID_MINOR_SHIFT (16U)
18644 #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
18645 #define I2S_VERID_MAJOR_MASK (0xFF000000U)
18646 #define I2S_VERID_MAJOR_SHIFT (24U)
18649 #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
18654 #define I2S_PARAM_DATALINE_MASK (0xFU)
18655 #define I2S_PARAM_DATALINE_SHIFT (0U)
18658 #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
18659 #define I2S_PARAM_FIFO_MASK (0xF00U)
18660 #define I2S_PARAM_FIFO_SHIFT (8U)
18663 #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
18664 #define I2S_PARAM_FRAME_MASK (0xF0000U)
18665 #define I2S_PARAM_FRAME_SHIFT (16U)
18668 #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
18673 #define I2S_TCSR_FRDE_MASK (0x1U)
18674 #define I2S_TCSR_FRDE_SHIFT (0U)
18679 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
18680 #define I2S_TCSR_FWDE_MASK (0x2U)
18681 #define I2S_TCSR_FWDE_SHIFT (1U)
18686 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
18687 #define I2S_TCSR_FRIE_MASK (0x100U)
18688 #define I2S_TCSR_FRIE_SHIFT (8U)
18693 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
18694 #define I2S_TCSR_FWIE_MASK (0x200U)
18695 #define I2S_TCSR_FWIE_SHIFT (9U)
18700 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
18701 #define I2S_TCSR_FEIE_MASK (0x400U)
18702 #define I2S_TCSR_FEIE_SHIFT (10U)
18707 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
18708 #define I2S_TCSR_SEIE_MASK (0x800U)
18709 #define I2S_TCSR_SEIE_SHIFT (11U)
18714 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
18715 #define I2S_TCSR_WSIE_MASK (0x1000U)
18716 #define I2S_TCSR_WSIE_SHIFT (12U)
18721 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
18722 #define I2S_TCSR_FRF_MASK (0x10000U)
18723 #define I2S_TCSR_FRF_SHIFT (16U)
18728 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
18729 #define I2S_TCSR_FWF_MASK (0x20000U)
18730 #define I2S_TCSR_FWF_SHIFT (17U)
18735 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
18736 #define I2S_TCSR_FEF_MASK (0x40000U)
18737 #define I2S_TCSR_FEF_SHIFT (18U)
18742 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
18743 #define I2S_TCSR_SEF_MASK (0x80000U)
18744 #define I2S_TCSR_SEF_SHIFT (19U)
18749 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
18750 #define I2S_TCSR_WSF_MASK (0x100000U)
18751 #define I2S_TCSR_WSF_SHIFT (20U)
18756 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
18757 #define I2S_TCSR_SR_MASK (0x1000000U)
18758 #define I2S_TCSR_SR_SHIFT (24U)
18763 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
18764 #define I2S_TCSR_FR_MASK (0x2000000U)
18765 #define I2S_TCSR_FR_SHIFT (25U)
18770 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
18771 #define I2S_TCSR_BCE_MASK (0x10000000U)
18772 #define I2S_TCSR_BCE_SHIFT (28U)
18777 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
18778 #define I2S_TCSR_DBGE_MASK (0x20000000U)
18779 #define I2S_TCSR_DBGE_SHIFT (29U)
18784 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
18785 #define I2S_TCSR_STOPE_MASK (0x40000000U)
18786 #define I2S_TCSR_STOPE_SHIFT (30U)
18791 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
18792 #define I2S_TCSR_TE_MASK (0x80000000U)
18793 #define I2S_TCSR_TE_SHIFT (31U)
18798 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
18803 #define I2S_TCR1_TFW_MASK (0x1FU)
18804 #define I2S_TCR1_TFW_SHIFT (0U)
18807 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
18812 #define I2S_TCR2_DIV_MASK (0xFFU)
18813 #define I2S_TCR2_DIV_SHIFT (0U)
18816 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
18817 #define I2S_TCR2_BCD_MASK (0x1000000U)
18818 #define I2S_TCR2_BCD_SHIFT (24U)
18823 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
18824 #define I2S_TCR2_BCP_MASK (0x2000000U)
18825 #define I2S_TCR2_BCP_SHIFT (25U)
18830 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
18831 #define I2S_TCR2_MSEL_MASK (0xC000000U)
18832 #define I2S_TCR2_MSEL_SHIFT (26U)
18839 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
18840 #define I2S_TCR2_BCI_MASK (0x10000000U)
18841 #define I2S_TCR2_BCI_SHIFT (28U)
18846 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
18847 #define I2S_TCR2_BCS_MASK (0x20000000U)
18848 #define I2S_TCR2_BCS_SHIFT (29U)
18853 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
18854 #define I2S_TCR2_SYNC_MASK (0x40000000U)
18855 #define I2S_TCR2_SYNC_SHIFT (30U)
18860 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
18865 #define I2S_TCR3_WDFL_MASK (0x1FU)
18866 #define I2S_TCR3_WDFL_SHIFT (0U)
18869 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
18870 #define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
18871 #define I2S_TCR3_TCE_SHIFT (16U)
18874 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
18875 #define I2S_TCR3_CFR_MASK (0xF000000U)
18876 #define I2S_TCR3_CFR_SHIFT (24U)
18879 #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
18884 #define I2S_TCR4_FSD_MASK (0x1U)
18885 #define I2S_TCR4_FSD_SHIFT (0U)
18890 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
18891 #define I2S_TCR4_FSP_MASK (0x2U)
18892 #define I2S_TCR4_FSP_SHIFT (1U)
18897 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
18898 #define I2S_TCR4_ONDEM_MASK (0x4U)
18899 #define I2S_TCR4_ONDEM_SHIFT (2U)
18904 #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
18905 #define I2S_TCR4_FSE_MASK (0x8U)
18906 #define I2S_TCR4_FSE_SHIFT (3U)
18911 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
18912 #define I2S_TCR4_MF_MASK (0x10U)
18913 #define I2S_TCR4_MF_SHIFT (4U)
18918 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
18919 #define I2S_TCR4_CHMOD_MASK (0x20U)
18920 #define I2S_TCR4_CHMOD_SHIFT (5U)
18925 #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
18926 #define I2S_TCR4_SYWD_MASK (0x1F00U)
18927 #define I2S_TCR4_SYWD_SHIFT (8U)
18930 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
18931 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
18932 #define I2S_TCR4_FRSZ_SHIFT (16U)
18935 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
18936 #define I2S_TCR4_FPACK_MASK (0x3000000U)
18937 #define I2S_TCR4_FPACK_SHIFT (24U)
18944 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
18945 #define I2S_TCR4_FCOMB_MASK (0xC000000U)
18946 #define I2S_TCR4_FCOMB_SHIFT (26U)
18953 #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
18954 #define I2S_TCR4_FCONT_MASK (0x10000000U)
18955 #define I2S_TCR4_FCONT_SHIFT (28U)
18960 #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
18965 #define I2S_TCR5_FBT_MASK (0x1F00U)
18966 #define I2S_TCR5_FBT_SHIFT (8U)
18969 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
18970 #define I2S_TCR5_W0W_MASK (0x1F0000U)
18971 #define I2S_TCR5_W0W_SHIFT (16U)
18974 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
18975 #define I2S_TCR5_WNW_MASK (0x1F000000U)
18976 #define I2S_TCR5_WNW_SHIFT (24U)
18979 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
18984 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
18985 #define I2S_TDR_TDR_SHIFT (0U)
18988 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
18991 /* The count of I2S_TDR */
18992 #define I2S_TDR_COUNT (4U)
18993 
18996 #define I2S_TFR_RFP_MASK (0x3FU)
18997 #define I2S_TFR_RFP_SHIFT (0U)
19000 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
19001 #define I2S_TFR_WFP_MASK (0x3F0000U)
19002 #define I2S_TFR_WFP_SHIFT (16U)
19005 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
19006 #define I2S_TFR_WCP_MASK (0x80000000U)
19007 #define I2S_TFR_WCP_SHIFT (31U)
19012 #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
19015 /* The count of I2S_TFR */
19016 #define I2S_TFR_COUNT (4U)
19017 
19020 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
19021 #define I2S_TMR_TWM_SHIFT (0U)
19026 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
19031 #define I2S_RCSR_FRDE_MASK (0x1U)
19032 #define I2S_RCSR_FRDE_SHIFT (0U)
19037 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
19038 #define I2S_RCSR_FWDE_MASK (0x2U)
19039 #define I2S_RCSR_FWDE_SHIFT (1U)
19044 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
19045 #define I2S_RCSR_FRIE_MASK (0x100U)
19046 #define I2S_RCSR_FRIE_SHIFT (8U)
19051 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
19052 #define I2S_RCSR_FWIE_MASK (0x200U)
19053 #define I2S_RCSR_FWIE_SHIFT (9U)
19058 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
19059 #define I2S_RCSR_FEIE_MASK (0x400U)
19060 #define I2S_RCSR_FEIE_SHIFT (10U)
19065 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
19066 #define I2S_RCSR_SEIE_MASK (0x800U)
19067 #define I2S_RCSR_SEIE_SHIFT (11U)
19072 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
19073 #define I2S_RCSR_WSIE_MASK (0x1000U)
19074 #define I2S_RCSR_WSIE_SHIFT (12U)
19079 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
19080 #define I2S_RCSR_FRF_MASK (0x10000U)
19081 #define I2S_RCSR_FRF_SHIFT (16U)
19086 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
19087 #define I2S_RCSR_FWF_MASK (0x20000U)
19088 #define I2S_RCSR_FWF_SHIFT (17U)
19093 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
19094 #define I2S_RCSR_FEF_MASK (0x40000U)
19095 #define I2S_RCSR_FEF_SHIFT (18U)
19100 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
19101 #define I2S_RCSR_SEF_MASK (0x80000U)
19102 #define I2S_RCSR_SEF_SHIFT (19U)
19107 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
19108 #define I2S_RCSR_WSF_MASK (0x100000U)
19109 #define I2S_RCSR_WSF_SHIFT (20U)
19114 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
19115 #define I2S_RCSR_SR_MASK (0x1000000U)
19116 #define I2S_RCSR_SR_SHIFT (24U)
19121 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
19122 #define I2S_RCSR_FR_MASK (0x2000000U)
19123 #define I2S_RCSR_FR_SHIFT (25U)
19128 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
19129 #define I2S_RCSR_BCE_MASK (0x10000000U)
19130 #define I2S_RCSR_BCE_SHIFT (28U)
19135 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
19136 #define I2S_RCSR_DBGE_MASK (0x20000000U)
19137 #define I2S_RCSR_DBGE_SHIFT (29U)
19142 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
19143 #define I2S_RCSR_STOPE_MASK (0x40000000U)
19144 #define I2S_RCSR_STOPE_SHIFT (30U)
19149 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
19150 #define I2S_RCSR_RE_MASK (0x80000000U)
19151 #define I2S_RCSR_RE_SHIFT (31U)
19156 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
19161 #define I2S_RCR1_RFW_MASK (0x1FU)
19162 #define I2S_RCR1_RFW_SHIFT (0U)
19165 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
19170 #define I2S_RCR2_DIV_MASK (0xFFU)
19171 #define I2S_RCR2_DIV_SHIFT (0U)
19174 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
19175 #define I2S_RCR2_BCD_MASK (0x1000000U)
19176 #define I2S_RCR2_BCD_SHIFT (24U)
19181 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
19182 #define I2S_RCR2_BCP_MASK (0x2000000U)
19183 #define I2S_RCR2_BCP_SHIFT (25U)
19188 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
19189 #define I2S_RCR2_MSEL_MASK (0xC000000U)
19190 #define I2S_RCR2_MSEL_SHIFT (26U)
19197 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
19198 #define I2S_RCR2_BCI_MASK (0x10000000U)
19199 #define I2S_RCR2_BCI_SHIFT (28U)
19204 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
19205 #define I2S_RCR2_BCS_MASK (0x20000000U)
19206 #define I2S_RCR2_BCS_SHIFT (29U)
19211 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
19212 #define I2S_RCR2_SYNC_MASK (0x40000000U)
19213 #define I2S_RCR2_SYNC_SHIFT (30U)
19218 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
19223 #define I2S_RCR3_WDFL_MASK (0x1FU)
19224 #define I2S_RCR3_WDFL_SHIFT (0U)
19227 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
19228 #define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
19229 #define I2S_RCR3_RCE_SHIFT (16U)
19232 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
19233 #define I2S_RCR3_CFR_MASK (0xF000000U)
19234 #define I2S_RCR3_CFR_SHIFT (24U)
19237 #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
19242 #define I2S_RCR4_FSD_MASK (0x1U)
19243 #define I2S_RCR4_FSD_SHIFT (0U)
19248 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
19249 #define I2S_RCR4_FSP_MASK (0x2U)
19250 #define I2S_RCR4_FSP_SHIFT (1U)
19255 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
19256 #define I2S_RCR4_ONDEM_MASK (0x4U)
19257 #define I2S_RCR4_ONDEM_SHIFT (2U)
19262 #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
19263 #define I2S_RCR4_FSE_MASK (0x8U)
19264 #define I2S_RCR4_FSE_SHIFT (3U)
19269 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
19270 #define I2S_RCR4_MF_MASK (0x10U)
19271 #define I2S_RCR4_MF_SHIFT (4U)
19276 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
19277 #define I2S_RCR4_SYWD_MASK (0x1F00U)
19278 #define I2S_RCR4_SYWD_SHIFT (8U)
19281 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
19282 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
19283 #define I2S_RCR4_FRSZ_SHIFT (16U)
19286 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
19287 #define I2S_RCR4_FPACK_MASK (0x3000000U)
19288 #define I2S_RCR4_FPACK_SHIFT (24U)
19295 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
19296 #define I2S_RCR4_FCOMB_MASK (0xC000000U)
19297 #define I2S_RCR4_FCOMB_SHIFT (26U)
19304 #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
19305 #define I2S_RCR4_FCONT_MASK (0x10000000U)
19306 #define I2S_RCR4_FCONT_SHIFT (28U)
19311 #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
19316 #define I2S_RCR5_FBT_MASK (0x1F00U)
19317 #define I2S_RCR5_FBT_SHIFT (8U)
19320 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
19321 #define I2S_RCR5_W0W_MASK (0x1F0000U)
19322 #define I2S_RCR5_W0W_SHIFT (16U)
19325 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
19326 #define I2S_RCR5_WNW_MASK (0x1F000000U)
19327 #define I2S_RCR5_WNW_SHIFT (24U)
19330 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
19335 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
19336 #define I2S_RDR_RDR_SHIFT (0U)
19339 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
19342 /* The count of I2S_RDR */
19343 #define I2S_RDR_COUNT (4U)
19344 
19347 #define I2S_RFR_RFP_MASK (0x3FU)
19348 #define I2S_RFR_RFP_SHIFT (0U)
19351 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
19352 #define I2S_RFR_RCP_MASK (0x8000U)
19353 #define I2S_RFR_RCP_SHIFT (15U)
19358 #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
19359 #define I2S_RFR_WFP_MASK (0x3F0000U)
19360 #define I2S_RFR_WFP_SHIFT (16U)
19363 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
19366 /* The count of I2S_RFR */
19367 #define I2S_RFR_COUNT (4U)
19368 
19371 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
19372 #define I2S_RMR_RWM_SHIFT (0U)
19377 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /* end of group I2S_Register_Masks */
19384 
19385 
19386 /* I2S - Peripheral instance base addresses */
19388 #define SAI1_BASE (0x40384000u)
19390 #define SAI1 ((I2S_Type *)SAI1_BASE)
19392 #define SAI2_BASE (0x40388000u)
19394 #define SAI2 ((I2S_Type *)SAI2_BASE)
19396 #define SAI3_BASE (0x4038C000u)
19398 #define SAI3 ((I2S_Type *)SAI3_BASE)
19400 #define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
19402 #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
19404 #define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
19405 #define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
19406  /* end of group I2S_Peripheral_Access_Layer */
19410 
19411 
19412 /* ----------------------------------------------------------------------------
19413  -- IOMUXC Peripheral Access Layer
19414  ---------------------------------------------------------------------------- */
19415 
19422 typedef struct {
19423  uint8_t RESERVED_0[20];
19424  __IO uint32_t SW_MUX_CTL_PAD[93];
19425  __IO uint32_t SW_PAD_CTL_PAD[93];
19426  __IO uint32_t SELECT_INPUT[114];
19427 } IOMUXC_Type;
19428 
19429 /* ----------------------------------------------------------------------------
19430  -- IOMUXC Register Masks
19431  ---------------------------------------------------------------------------- */
19432 
19440 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
19441 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
19452 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
19453 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
19454 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
19459 #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
19462 /* The count of IOMUXC_SW_MUX_CTL_PAD */
19463 #define IOMUXC_SW_MUX_CTL_PAD_COUNT (93U)
19464 
19467 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
19468 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
19473 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
19474 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)
19475 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)
19486 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
19487 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)
19488 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)
19495 #define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
19496 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)
19497 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)
19502 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
19503 #define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)
19504 #define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)
19509 #define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
19510 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)
19511 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)
19516 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
19517 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)
19518 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)
19525 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
19526 #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)
19527 #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)
19532 #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
19535 /* The count of IOMUXC_SW_PAD_CTL_PAD */
19536 #define IOMUXC_SW_PAD_CTL_PAD_COUNT (93U)
19537 
19540 #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
19541 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
19547 #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
19550 /* The count of IOMUXC_SELECT_INPUT */
19551 #define IOMUXC_SELECT_INPUT_COUNT (114U)
19552 
19553  /* end of group IOMUXC_Register_Masks */
19557 
19558 
19559 /* IOMUXC - Peripheral instance base addresses */
19561 #define IOMUXC_BASE (0x401F8000u)
19563 #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
19565 #define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
19567 #define IOMUXC_BASE_PTRS { IOMUXC }
19568  /* end of group IOMUXC_Peripheral_Access_Layer */
19572 
19573 
19574 /* ----------------------------------------------------------------------------
19575  -- IOMUXC_GPR Peripheral Access Layer
19576  ---------------------------------------------------------------------------- */
19577 
19584 typedef struct {
19585  uint32_t GPR0;
19586  __IO uint32_t GPR1;
19587  __IO uint32_t GPR2;
19588  __IO uint32_t GPR3;
19589  __IO uint32_t GPR4;
19590  __IO uint32_t GPR5;
19591  __IO uint32_t GPR6;
19592  __IO uint32_t GPR7;
19593  __IO uint32_t GPR8;
19594  uint32_t GPR9;
19595  __IO uint32_t GPR10;
19596  __IO uint32_t GPR11;
19597  __IO uint32_t GPR12;
19598  __IO uint32_t GPR13;
19599  __IO uint32_t GPR14;
19600  uint32_t GPR15;
19601  __IO uint32_t GPR16;
19602  __IO uint32_t GPR17;
19603  __IO uint32_t GPR18;
19604  __IO uint32_t GPR19;
19605  __IO uint32_t GPR20;
19606  __IO uint32_t GPR21;
19607  __IO uint32_t GPR22;
19608  __IO uint32_t GPR23;
19609  __IO uint32_t GPR24;
19610  __IO uint32_t GPR25;
19611 } IOMUXC_GPR_Type;
19612 
19613 /* ----------------------------------------------------------------------------
19614  -- IOMUXC_GPR Register Masks
19615  ---------------------------------------------------------------------------- */
19616 
19624 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
19625 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
19636 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
19637 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
19638 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
19649 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
19650 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
19651 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
19658 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
19659 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
19660 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
19667 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
19668 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
19669 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
19676 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
19677 #define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
19678 #define IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
19683 #define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
19684 #define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK (0x2000U)
19685 #define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT (13U)
19690 #define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK)
19691 #define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK (0x20000U)
19692 #define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT (17U)
19697 #define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
19698 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
19699 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
19704 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
19705 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
19706 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
19711 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
19712 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
19713 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
19718 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
19719 #define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
19720 #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
19725 #define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
19726 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
19727 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
19732 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
19737 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
19738 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
19743 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
19744 #define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U)
19745 #define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U)
19750 #define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK)
19751 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
19752 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
19757 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
19758 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
19759 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
20018 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
20019 #define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
20020 #define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
20025 #define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
20026 #define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
20027 #define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
20032 #define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
20033 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
20034 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
20039 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
20040 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
20041 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
20046 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
20047 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
20048 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
20053 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
20058 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
20059 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
20064 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
20069 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
20070 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
20075 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
20076 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
20077 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
20082 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
20083 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
20084 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
20089 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
20090 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
20091 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
20096 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
20097 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
20098 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
20103 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
20104 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
20105 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
20110 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
20111 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
20112 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
20117 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
20118 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
20119 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
20124 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
20125 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
20126 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
20131 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
20132 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
20133 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
20138 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
20139 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
20140 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
20145 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
20146 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
20147 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
20152 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
20153 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
20154 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
20159 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
20160 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
20161 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
20166 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
20167 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
20168 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
20173 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
20174 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
20175 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
20180 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
20181 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
20182 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
20187 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
20188 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
20189 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
20194 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
20195 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
20196 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
20201 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
20202 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
20203 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
20208 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
20209 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
20210 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
20215 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
20216 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
20217 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
20222 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
20223 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
20224 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
20229 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
20230 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
20231 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
20236 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
20241 #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
20242 #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
20247 #define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
20248 #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
20249 #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
20254 #define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
20255 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
20256 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
20261 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
20262 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
20263 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
20268 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
20269 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
20270 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
20278 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
20279 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
20280 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
20288 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
20293 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
20294 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
20299 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
20300 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
20301 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
20306 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
20307 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
20308 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
20313 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
20314 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
20315 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
20320 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
20321 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
20322 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
20327 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
20328 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
20329 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
20334 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
20335 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
20336 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
20341 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
20342 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
20343 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
20348 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
20349 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
20350 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
20355 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
20356 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
20357 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
20362 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
20363 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
20364 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
20369 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
20370 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
20371 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
20376 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
20377 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
20378 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
20383 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
20384 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
20385 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
20390 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
20391 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
20392 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
20397 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
20398 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
20399 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
20404 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
20405 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
20406 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
20411 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
20412 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
20413 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
20418 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
20419 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
20420 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
20425 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
20426 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
20427 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
20432 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
20433 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
20434 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
20439 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
20440 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
20441 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
20446 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
20447 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
20448 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
20453 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
20454 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
20455 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
20460 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
20465 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
20466 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
20471 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
20472 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
20473 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
20478 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
20479 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
20480 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
20485 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
20486 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
20487 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
20492 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
20493 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
20494 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
20499 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
20500 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
20501 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
20506 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
20507 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
20508 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
20513 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
20514 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
20515 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
20520 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
20521 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
20522 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
20527 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
20528 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
20529 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
20534 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
20535 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
20536 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
20541 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
20542 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
20543 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
20548 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
20549 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
20550 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
20555 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
20556 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
20557 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
20562 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
20563 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
20564 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
20569 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
20570 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
20571 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
20576 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
20577 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
20578 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
20583 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
20584 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
20585 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
20590 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
20591 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
20592 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
20597 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
20598 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
20599 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
20604 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
20605 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
20606 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
20611 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
20612 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
20613 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
20618 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
20619 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
20620 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
20625 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
20626 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
20627 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
20632 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
20633 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
20634 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
20639 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
20640 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
20641 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
20646 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
20647 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
20648 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
20653 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
20654 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
20655 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
20660 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
20661 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
20662 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
20667 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
20668 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
20669 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
20674 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
20675 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
20676 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
20681 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
20682 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
20683 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
20688 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
20693 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
20694 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
20699 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
20700 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
20701 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
20706 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
20707 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
20708 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
20713 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
20714 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
20715 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
20720 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
20721 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
20722 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
20727 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
20728 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
20729 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
20734 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
20735 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
20736 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
20741 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
20742 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
20743 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
20748 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
20749 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
20750 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
20755 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
20756 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
20757 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
20762 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
20763 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
20764 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
20769 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
20770 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
20771 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
20776 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
20777 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
20778 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
20783 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
20784 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
20785 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
20790 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
20791 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
20792 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
20797 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
20798 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
20799 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
20804 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
20805 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
20806 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
20811 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
20812 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
20813 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
20818 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
20819 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
20820 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
20825 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
20826 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
20827 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
20832 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
20833 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
20834 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
20839 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
20840 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
20841 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
20846 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
20847 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
20848 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
20853 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
20854 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
20855 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
20860 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
20861 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
20862 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
20867 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
20868 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
20869 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
20874 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
20875 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
20876 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
20881 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
20882 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
20883 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
20888 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
20889 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
20890 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
20895 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
20896 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
20897 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
20902 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
20903 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
20904 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
20909 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
20910 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
20911 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
20916 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
20921 #define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
20922 #define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
20927 #define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
20928 #define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
20929 #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
20934 #define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
20935 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
20936 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
20941 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
20942 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
20943 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
20948 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
20949 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
20950 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
20956 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
20957 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x7E00U)
20958 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
20959 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
20960 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
20961 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
20966 #define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
20967 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
20968 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
20973 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
20974 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
20975 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
20980 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
20981 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
20982 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
20987 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
20988 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
20989 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
20994 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
20995 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
20996 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
21001 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
21006 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
21007 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
21015 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
21016 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
21017 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
21025 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
21026 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
21027 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
21035 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
21036 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
21037 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
21045 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
21046 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
21047 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
21052 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
21053 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)
21054 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)
21059 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)
21060 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)
21061 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)
21066 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)
21067 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)
21068 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)
21073 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)
21074 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)
21075 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)
21080 #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)
21081 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)
21082 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)
21087 #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)
21092 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
21093 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
21098 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
21099 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
21100 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
21105 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
21106 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
21107 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
21112 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
21117 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
21118 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
21123 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
21124 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
21125 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
21130 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
21131 #define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
21132 #define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
21137 #define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
21138 #define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
21139 #define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
21144 #define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
21149 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
21150 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
21155 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
21156 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
21157 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
21162 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
21163 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
21164 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
21169 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
21170 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
21171 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
21176 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
21177 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
21178 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
21183 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
21184 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
21185 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
21190 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
21191 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
21192 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
21197 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
21198 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
21199 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
21204 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
21205 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
21206 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
21211 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
21212 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
21213 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
21218 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
21219 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
21220 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
21225 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
21226 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
21227 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
21232 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
21233 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)
21234 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)
21245 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
21246 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)
21247 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)
21258 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
21263 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)
21264 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)
21269 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
21270 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)
21271 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)
21276 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
21277 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
21278 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
21283 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
21284 #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U)
21285 #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U)
21286 #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)
21291 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFU)
21292 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
21295 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
21300 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
21301 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
21306 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
21307 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
21308 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
21311 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
21316 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
21317 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
21322 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
21323 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
21324 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
21327 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
21332 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
21333 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
21338 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
21339 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
21340 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
21343 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
21348 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
21349 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
21354 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
21355 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
21356 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
21359 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
21364 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
21365 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
21370 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
21371 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
21372 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
21375 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
21380 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
21381 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
21386 #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
21387 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
21388 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
21391 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
21396 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
21397 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
21402 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
21403 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
21404 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)
21407 #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
21412 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
21413 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
21418 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
21419 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
21420 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
21423 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) /* end of group IOMUXC_GPR_Register_Masks */
21430 
21431 
21432 /* IOMUXC_GPR - Peripheral instance base addresses */
21434 #define IOMUXC_GPR_BASE (0x400AC000u)
21436 #define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
21438 #define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
21440 #define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
21441  /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
21445 
21446 
21447 /* ----------------------------------------------------------------------------
21448  -- IOMUXC_SNVS Peripheral Access Layer
21449  ---------------------------------------------------------------------------- */
21450 
21457 typedef struct {
21458  __IO uint32_t SW_MUX_CTL_PAD_WAKEUP;
21459  __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ;
21460  __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ;
21461  __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE;
21462  __IO uint32_t SW_PAD_CTL_PAD_POR_B;
21463  __IO uint32_t SW_PAD_CTL_PAD_ONOFF;
21464  __IO uint32_t SW_PAD_CTL_PAD_WAKEUP;
21465  __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ;
21466  __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ;
21467 } IOMUXC_SNVS_Type;
21468 
21469 /* ----------------------------------------------------------------------------
21470  -- IOMUXC_SNVS Register Masks
21471  ---------------------------------------------------------------------------- */
21472 
21480 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
21481 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
21486 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
21487 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
21488 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
21493 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
21498 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
21499 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
21504 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
21505 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
21506 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
21511 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
21516 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
21517 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
21522 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
21523 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
21524 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
21529 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
21534 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
21535 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
21540 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
21541 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
21542 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
21553 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
21554 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
21555 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
21559 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
21560 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
21561 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
21566 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
21567 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
21568 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
21573 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
21574 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
21575 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
21580 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
21581 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
21582 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
21589 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
21590 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
21591 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
21596 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
21601 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
21602 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
21607 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
21608 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
21609 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
21620 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
21621 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
21622 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
21626 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
21627 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
21628 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
21633 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
21634 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
21635 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
21640 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
21641 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
21642 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
21647 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
21648 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
21649 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
21656 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
21657 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
21658 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
21663 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
21668 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
21669 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
21674 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
21675 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
21676 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
21687 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
21688 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
21689 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
21693 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
21694 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
21695 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
21700 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
21701 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
21702 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
21707 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
21708 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
21709 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
21714 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
21715 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
21716 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
21723 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
21724 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
21725 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
21730 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
21735 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
21736 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
21741 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
21742 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
21743 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
21754 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
21755 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
21756 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
21760 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
21761 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
21762 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
21767 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
21768 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
21769 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
21774 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
21775 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
21776 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
21781 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
21782 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
21783 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
21790 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
21791 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
21792 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
21797 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
21802 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
21803 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
21808 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
21809 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
21810 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
21821 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
21822 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
21823 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
21827 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
21828 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
21829 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
21834 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
21835 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
21836 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
21841 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
21842 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
21843 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
21848 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
21849 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
21850 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
21857 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
21858 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
21859 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
21864 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
21869 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
21870 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
21875 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
21876 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
21877 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
21888 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
21889 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
21890 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
21894 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
21895 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
21896 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
21901 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
21902 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
21903 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
21908 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
21909 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
21910 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
21915 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
21916 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
21917 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
21924 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
21925 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
21926 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
21931 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) /* end of group IOMUXC_SNVS_Register_Masks */
21938 
21939 
21940 /* IOMUXC_SNVS - Peripheral instance base addresses */
21942 #define IOMUXC_SNVS_BASE (0x400A8000u)
21944 #define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
21946 #define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
21948 #define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
21949  /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
21953 
21954 
21955 /* ----------------------------------------------------------------------------
21956  -- IOMUXC_SNVS_GPR Peripheral Access Layer
21957  ---------------------------------------------------------------------------- */
21958 
21965 typedef struct {
21966  uint32_t GPR0;
21967  uint32_t GPR1;
21968  uint32_t GPR2;
21969  __IO uint32_t GPR3;
21970 } IOMUXC_SNVS_GPR_Type;
21971 
21972 /* ----------------------------------------------------------------------------
21973  -- IOMUXC_SNVS_GPR Register Masks
21974  ---------------------------------------------------------------------------- */
21975 
21983 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
21984 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
21989 #define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
21990 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
21991 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
21994 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
21995 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
21996 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
22003 #define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
22004 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
22005 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
22010 #define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
22011 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
22012 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
22017 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
22018 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
22019 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
22024 #define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
22025 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
22026 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
22031 #define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) /* end of group IOMUXC_SNVS_GPR_Register_Masks */
22038 
22039 
22040 /* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
22042 #define IOMUXC_SNVS_GPR_BASE (0x400A4000u)
22044 #define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
22046 #define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
22048 #define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
22049  /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
22053 
22054 
22055 /* ----------------------------------------------------------------------------
22056  -- KPP Peripheral Access Layer
22057  ---------------------------------------------------------------------------- */
22058 
22065 typedef struct {
22066  __IO uint16_t KPCR;
22067  __IO uint16_t KPSR;
22068  __IO uint16_t KDDR;
22069  __IO uint16_t KPDR;
22070 } KPP_Type;
22071 
22072 /* ----------------------------------------------------------------------------
22073  -- KPP Register Masks
22074  ---------------------------------------------------------------------------- */
22075 
22083 #define KPP_KPCR_KRE_MASK (0xFFU)
22084 #define KPP_KPCR_KRE_SHIFT (0U)
22089 #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
22090 #define KPP_KPCR_KCO_MASK (0xFF00U)
22091 #define KPP_KPCR_KCO_SHIFT (8U)
22096 #define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
22101 #define KPP_KPSR_KPKD_MASK (0x1U)
22102 #define KPP_KPSR_KPKD_SHIFT (0U)
22107 #define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
22108 #define KPP_KPSR_KPKR_MASK (0x2U)
22109 #define KPP_KPSR_KPKR_SHIFT (1U)
22114 #define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
22115 #define KPP_KPSR_KDSC_MASK (0x4U)
22116 #define KPP_KPSR_KDSC_SHIFT (2U)
22121 #define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
22122 #define KPP_KPSR_KRSS_MASK (0x8U)
22123 #define KPP_KPSR_KRSS_SHIFT (3U)
22128 #define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
22129 #define KPP_KPSR_KDIE_MASK (0x100U)
22130 #define KPP_KPSR_KDIE_SHIFT (8U)
22135 #define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
22136 #define KPP_KPSR_KRIE_MASK (0x200U)
22137 #define KPP_KPSR_KRIE_SHIFT (9U)
22142 #define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
22147 #define KPP_KDDR_KRDD_MASK (0xFFU)
22148 #define KPP_KDDR_KRDD_SHIFT (0U)
22153 #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
22154 #define KPP_KDDR_KCDD_MASK (0xFF00U)
22155 #define KPP_KDDR_KCDD_SHIFT (8U)
22160 #define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
22165 #define KPP_KPDR_KRD_MASK (0xFFU)
22166 #define KPP_KPDR_KRD_SHIFT (0U)
22167 #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
22168 #define KPP_KPDR_KCD_MASK (0xFF00U)
22169 #define KPP_KPDR_KCD_SHIFT (8U)
22170 #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) /* end of group KPP_Register_Masks */
22177 
22178 
22179 /* KPP - Peripheral instance base addresses */
22181 #define KPP_BASE (0x401FC000u)
22183 #define KPP ((KPP_Type *)KPP_BASE)
22185 #define KPP_BASE_ADDRS { KPP_BASE }
22187 #define KPP_BASE_PTRS { KPP }
22189 #define KPP_IRQS { KPP_IRQn }
22190  /* end of group KPP_Peripheral_Access_Layer */
22194 
22195 
22196 /* ----------------------------------------------------------------------------
22197  -- LPI2C Peripheral Access Layer
22198  ---------------------------------------------------------------------------- */
22199 
22206 typedef struct {
22207  __I uint32_t VERID;
22208  __I uint32_t PARAM;
22209  uint8_t RESERVED_0[8];
22210  __IO uint32_t MCR;
22211  __IO uint32_t MSR;
22212  __IO uint32_t MIER;
22213  __IO uint32_t MDER;
22214  __IO uint32_t MCFGR0;
22215  __IO uint32_t MCFGR1;
22216  __IO uint32_t MCFGR2;
22217  __IO uint32_t MCFGR3;
22218  uint8_t RESERVED_1[16];
22219  __IO uint32_t MDMR;
22220  uint8_t RESERVED_2[4];
22221  __IO uint32_t MCCR0;
22222  uint8_t RESERVED_3[4];
22223  __IO uint32_t MCCR1;
22224  uint8_t RESERVED_4[4];
22225  __IO uint32_t MFCR;
22226  __I uint32_t MFSR;
22227  __O uint32_t MTDR;
22228  uint8_t RESERVED_5[12];
22229  __I uint32_t MRDR;
22230  uint8_t RESERVED_6[156];
22231  __IO uint32_t SCR;
22232  __IO uint32_t SSR;
22233  __IO uint32_t SIER;
22234  __IO uint32_t SDER;
22235  uint8_t RESERVED_7[4];
22236  __IO uint32_t SCFGR1;
22237  __IO uint32_t SCFGR2;
22238  uint8_t RESERVED_8[20];
22239  __IO uint32_t SAMR;
22240  uint8_t RESERVED_9[12];
22241  __I uint32_t SASR;
22242  __IO uint32_t STAR;
22243  uint8_t RESERVED_10[8];
22244  __O uint32_t STDR;
22245  uint8_t RESERVED_11[12];
22246  __I uint32_t SRDR;
22247 } LPI2C_Type;
22248 
22249 /* ----------------------------------------------------------------------------
22250  -- LPI2C Register Masks
22251  ---------------------------------------------------------------------------- */
22252 
22260 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
22261 #define LPI2C_VERID_FEATURE_SHIFT (0U)
22266 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
22267 #define LPI2C_VERID_MINOR_MASK (0xFF0000U)
22268 #define LPI2C_VERID_MINOR_SHIFT (16U)
22271 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
22272 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
22273 #define LPI2C_VERID_MAJOR_SHIFT (24U)
22276 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
22281 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
22282 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
22285 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
22286 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
22287 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
22290 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
22295 #define LPI2C_MCR_MEN_MASK (0x1U)
22296 #define LPI2C_MCR_MEN_SHIFT (0U)
22301 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
22302 #define LPI2C_MCR_RST_MASK (0x2U)
22303 #define LPI2C_MCR_RST_SHIFT (1U)
22308 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
22309 #define LPI2C_MCR_DOZEN_MASK (0x4U)
22310 #define LPI2C_MCR_DOZEN_SHIFT (2U)
22315 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
22316 #define LPI2C_MCR_DBGEN_MASK (0x8U)
22317 #define LPI2C_MCR_DBGEN_SHIFT (3U)
22322 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
22323 #define LPI2C_MCR_RTF_MASK (0x100U)
22324 #define LPI2C_MCR_RTF_SHIFT (8U)
22329 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
22330 #define LPI2C_MCR_RRF_MASK (0x200U)
22331 #define LPI2C_MCR_RRF_SHIFT (9U)
22336 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
22341 #define LPI2C_MSR_TDF_MASK (0x1U)
22342 #define LPI2C_MSR_TDF_SHIFT (0U)
22347 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
22348 #define LPI2C_MSR_RDF_MASK (0x2U)
22349 #define LPI2C_MSR_RDF_SHIFT (1U)
22354 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
22355 #define LPI2C_MSR_EPF_MASK (0x100U)
22356 #define LPI2C_MSR_EPF_SHIFT (8U)
22361 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
22362 #define LPI2C_MSR_SDF_MASK (0x200U)
22363 #define LPI2C_MSR_SDF_SHIFT (9U)
22368 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
22369 #define LPI2C_MSR_NDF_MASK (0x400U)
22370 #define LPI2C_MSR_NDF_SHIFT (10U)
22375 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
22376 #define LPI2C_MSR_ALF_MASK (0x800U)
22377 #define LPI2C_MSR_ALF_SHIFT (11U)
22382 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
22383 #define LPI2C_MSR_FEF_MASK (0x1000U)
22384 #define LPI2C_MSR_FEF_SHIFT (12U)
22389 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
22390 #define LPI2C_MSR_PLTF_MASK (0x2000U)
22391 #define LPI2C_MSR_PLTF_SHIFT (13U)
22396 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
22397 #define LPI2C_MSR_DMF_MASK (0x4000U)
22398 #define LPI2C_MSR_DMF_SHIFT (14U)
22403 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
22404 #define LPI2C_MSR_MBF_MASK (0x1000000U)
22405 #define LPI2C_MSR_MBF_SHIFT (24U)
22410 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
22411 #define LPI2C_MSR_BBF_MASK (0x2000000U)
22412 #define LPI2C_MSR_BBF_SHIFT (25U)
22417 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
22422 #define LPI2C_MIER_TDIE_MASK (0x1U)
22423 #define LPI2C_MIER_TDIE_SHIFT (0U)
22428 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
22429 #define LPI2C_MIER_RDIE_MASK (0x2U)
22430 #define LPI2C_MIER_RDIE_SHIFT (1U)
22435 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
22436 #define LPI2C_MIER_EPIE_MASK (0x100U)
22437 #define LPI2C_MIER_EPIE_SHIFT (8U)
22442 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
22443 #define LPI2C_MIER_SDIE_MASK (0x200U)
22444 #define LPI2C_MIER_SDIE_SHIFT (9U)
22449 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
22450 #define LPI2C_MIER_NDIE_MASK (0x400U)
22451 #define LPI2C_MIER_NDIE_SHIFT (10U)
22456 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
22457 #define LPI2C_MIER_ALIE_MASK (0x800U)
22458 #define LPI2C_MIER_ALIE_SHIFT (11U)
22463 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
22464 #define LPI2C_MIER_FEIE_MASK (0x1000U)
22465 #define LPI2C_MIER_FEIE_SHIFT (12U)
22470 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
22471 #define LPI2C_MIER_PLTIE_MASK (0x2000U)
22472 #define LPI2C_MIER_PLTIE_SHIFT (13U)
22477 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
22478 #define LPI2C_MIER_DMIE_MASK (0x4000U)
22479 #define LPI2C_MIER_DMIE_SHIFT (14U)
22484 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
22489 #define LPI2C_MDER_TDDE_MASK (0x1U)
22490 #define LPI2C_MDER_TDDE_SHIFT (0U)
22495 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
22496 #define LPI2C_MDER_RDDE_MASK (0x2U)
22497 #define LPI2C_MDER_RDDE_SHIFT (1U)
22502 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
22507 #define LPI2C_MCFGR0_HREN_MASK (0x1U)
22508 #define LPI2C_MCFGR0_HREN_SHIFT (0U)
22513 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
22514 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
22515 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
22520 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
22521 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
22522 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
22527 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
22528 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
22529 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
22534 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
22535 #define LPI2C_MCFGR0_RDMO_MASK (0x200U)
22536 #define LPI2C_MCFGR0_RDMO_SHIFT (9U)
22541 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
22546 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
22547 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
22558 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
22559 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
22560 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
22565 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
22566 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
22567 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
22572 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
22573 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
22574 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
22579 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
22580 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
22581 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
22592 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
22593 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
22594 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
22605 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
22610 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
22611 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
22614 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
22615 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
22616 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
22619 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
22620 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
22621 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
22624 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
22629 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
22630 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
22633 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
22638 #define LPI2C_MDMR_MATCH0_MASK (0xFFU)
22639 #define LPI2C_MDMR_MATCH0_SHIFT (0U)
22642 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
22643 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
22644 #define LPI2C_MDMR_MATCH1_SHIFT (16U)
22647 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
22652 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
22653 #define LPI2C_MCCR0_CLKLO_SHIFT (0U)
22656 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
22657 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
22658 #define LPI2C_MCCR0_CLKHI_SHIFT (8U)
22661 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
22662 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
22663 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
22666 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
22667 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
22668 #define LPI2C_MCCR0_DATAVD_SHIFT (24U)
22671 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
22676 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
22677 #define LPI2C_MCCR1_CLKLO_SHIFT (0U)
22680 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
22681 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
22682 #define LPI2C_MCCR1_CLKHI_SHIFT (8U)
22685 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
22686 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
22687 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
22690 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
22691 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
22692 #define LPI2C_MCCR1_DATAVD_SHIFT (24U)
22695 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
22700 #define LPI2C_MFCR_TXWATER_MASK (0x3U)
22701 #define LPI2C_MFCR_TXWATER_SHIFT (0U)
22704 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
22705 #define LPI2C_MFCR_RXWATER_MASK (0x30000U)
22706 #define LPI2C_MFCR_RXWATER_SHIFT (16U)
22709 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
22714 #define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
22715 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
22718 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
22719 #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
22720 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
22723 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
22728 #define LPI2C_MTDR_DATA_MASK (0xFFU)
22729 #define LPI2C_MTDR_DATA_SHIFT (0U)
22732 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
22733 #define LPI2C_MTDR_CMD_MASK (0x700U)
22734 #define LPI2C_MTDR_CMD_SHIFT (8U)
22745 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
22750 #define LPI2C_MRDR_DATA_MASK (0xFFU)
22751 #define LPI2C_MRDR_DATA_SHIFT (0U)
22754 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
22755 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
22756 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
22761 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
22766 #define LPI2C_SCR_SEN_MASK (0x1U)
22767 #define LPI2C_SCR_SEN_SHIFT (0U)
22772 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
22773 #define LPI2C_SCR_RST_MASK (0x2U)
22774 #define LPI2C_SCR_RST_SHIFT (1U)
22779 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
22780 #define LPI2C_SCR_FILTEN_MASK (0x10U)
22781 #define LPI2C_SCR_FILTEN_SHIFT (4U)
22786 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
22787 #define LPI2C_SCR_FILTDZ_MASK (0x20U)
22788 #define LPI2C_SCR_FILTDZ_SHIFT (5U)
22793 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
22794 #define LPI2C_SCR_RTF_MASK (0x100U)
22795 #define LPI2C_SCR_RTF_SHIFT (8U)
22800 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
22801 #define LPI2C_SCR_RRF_MASK (0x200U)
22802 #define LPI2C_SCR_RRF_SHIFT (9U)
22807 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
22812 #define LPI2C_SSR_TDF_MASK (0x1U)
22813 #define LPI2C_SSR_TDF_SHIFT (0U)
22818 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
22819 #define LPI2C_SSR_RDF_MASK (0x2U)
22820 #define LPI2C_SSR_RDF_SHIFT (1U)
22825 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
22826 #define LPI2C_SSR_AVF_MASK (0x4U)
22827 #define LPI2C_SSR_AVF_SHIFT (2U)
22832 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
22833 #define LPI2C_SSR_TAF_MASK (0x8U)
22834 #define LPI2C_SSR_TAF_SHIFT (3U)
22839 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
22840 #define LPI2C_SSR_RSF_MASK (0x100U)
22841 #define LPI2C_SSR_RSF_SHIFT (8U)
22846 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
22847 #define LPI2C_SSR_SDF_MASK (0x200U)
22848 #define LPI2C_SSR_SDF_SHIFT (9U)
22853 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
22854 #define LPI2C_SSR_BEF_MASK (0x400U)
22855 #define LPI2C_SSR_BEF_SHIFT (10U)
22860 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
22861 #define LPI2C_SSR_FEF_MASK (0x800U)
22862 #define LPI2C_SSR_FEF_SHIFT (11U)
22867 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
22868 #define LPI2C_SSR_AM0F_MASK (0x1000U)
22869 #define LPI2C_SSR_AM0F_SHIFT (12U)
22874 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
22875 #define LPI2C_SSR_AM1F_MASK (0x2000U)
22876 #define LPI2C_SSR_AM1F_SHIFT (13U)
22881 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
22882 #define LPI2C_SSR_GCF_MASK (0x4000U)
22883 #define LPI2C_SSR_GCF_SHIFT (14U)
22888 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
22889 #define LPI2C_SSR_SARF_MASK (0x8000U)
22890 #define LPI2C_SSR_SARF_SHIFT (15U)
22895 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
22896 #define LPI2C_SSR_SBF_MASK (0x1000000U)
22897 #define LPI2C_SSR_SBF_SHIFT (24U)
22902 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
22903 #define LPI2C_SSR_BBF_MASK (0x2000000U)
22904 #define LPI2C_SSR_BBF_SHIFT (25U)
22909 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
22914 #define LPI2C_SIER_TDIE_MASK (0x1U)
22915 #define LPI2C_SIER_TDIE_SHIFT (0U)
22920 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
22921 #define LPI2C_SIER_RDIE_MASK (0x2U)
22922 #define LPI2C_SIER_RDIE_SHIFT (1U)
22927 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
22928 #define LPI2C_SIER_AVIE_MASK (0x4U)
22929 #define LPI2C_SIER_AVIE_SHIFT (2U)
22934 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
22935 #define LPI2C_SIER_TAIE_MASK (0x8U)
22936 #define LPI2C_SIER_TAIE_SHIFT (3U)
22941 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
22942 #define LPI2C_SIER_RSIE_MASK (0x100U)
22943 #define LPI2C_SIER_RSIE_SHIFT (8U)
22948 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
22949 #define LPI2C_SIER_SDIE_MASK (0x200U)
22950 #define LPI2C_SIER_SDIE_SHIFT (9U)
22955 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
22956 #define LPI2C_SIER_BEIE_MASK (0x400U)
22957 #define LPI2C_SIER_BEIE_SHIFT (10U)
22962 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
22963 #define LPI2C_SIER_FEIE_MASK (0x800U)
22964 #define LPI2C_SIER_FEIE_SHIFT (11U)
22969 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
22970 #define LPI2C_SIER_AM0IE_MASK (0x1000U)
22971 #define LPI2C_SIER_AM0IE_SHIFT (12U)
22976 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
22977 #define LPI2C_SIER_AM1F_MASK (0x2000U)
22978 #define LPI2C_SIER_AM1F_SHIFT (13U)
22983 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
22984 #define LPI2C_SIER_GCIE_MASK (0x4000U)
22985 #define LPI2C_SIER_GCIE_SHIFT (14U)
22990 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
22991 #define LPI2C_SIER_SARIE_MASK (0x8000U)
22992 #define LPI2C_SIER_SARIE_SHIFT (15U)
22997 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
23002 #define LPI2C_SDER_TDDE_MASK (0x1U)
23003 #define LPI2C_SDER_TDDE_SHIFT (0U)
23008 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
23009 #define LPI2C_SDER_RDDE_MASK (0x2U)
23010 #define LPI2C_SDER_RDDE_SHIFT (1U)
23015 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
23016 #define LPI2C_SDER_AVDE_MASK (0x4U)
23017 #define LPI2C_SDER_AVDE_SHIFT (2U)
23022 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
23027 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
23028 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
23033 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
23034 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
23035 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
23040 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
23041 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
23042 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
23047 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
23048 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
23049 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
23054 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
23055 #define LPI2C_SCFGR1_GCEN_MASK (0x100U)
23056 #define LPI2C_SCFGR1_GCEN_SHIFT (8U)
23061 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
23062 #define LPI2C_SCFGR1_SAEN_MASK (0x200U)
23063 #define LPI2C_SCFGR1_SAEN_SHIFT (9U)
23068 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
23069 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
23070 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
23075 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
23076 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
23077 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
23084 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
23085 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
23086 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
23091 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
23092 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
23093 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
23098 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
23099 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
23100 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
23111 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
23116 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
23117 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
23120 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
23121 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
23122 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
23125 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
23126 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
23127 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
23130 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
23131 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
23132 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
23135 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
23140 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
23141 #define LPI2C_SAMR_ADDR0_SHIFT (1U)
23144 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
23145 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
23146 #define LPI2C_SAMR_ADDR1_SHIFT (17U)
23149 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
23154 #define LPI2C_SASR_RADDR_MASK (0x7FFU)
23155 #define LPI2C_SASR_RADDR_SHIFT (0U)
23158 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
23159 #define LPI2C_SASR_ANV_MASK (0x4000U)
23160 #define LPI2C_SASR_ANV_SHIFT (14U)
23165 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
23170 #define LPI2C_STAR_TXNACK_MASK (0x1U)
23171 #define LPI2C_STAR_TXNACK_SHIFT (0U)
23176 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
23181 #define LPI2C_STDR_DATA_MASK (0xFFU)
23182 #define LPI2C_STDR_DATA_SHIFT (0U)
23185 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
23190 #define LPI2C_SRDR_DATA_MASK (0xFFU)
23191 #define LPI2C_SRDR_DATA_SHIFT (0U)
23194 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
23195 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
23196 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
23201 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
23202 #define LPI2C_SRDR_SOF_MASK (0x8000U)
23203 #define LPI2C_SRDR_SOF_SHIFT (15U)
23208 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /* end of group LPI2C_Register_Masks */
23215 
23216 
23217 /* LPI2C - Peripheral instance base addresses */
23219 #define LPI2C1_BASE (0x403F0000u)
23221 #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
23223 #define LPI2C2_BASE (0x403F4000u)
23225 #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
23227 #define LPI2C3_BASE (0x403F8000u)
23229 #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
23231 #define LPI2C4_BASE (0x403FC000u)
23233 #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
23235 #define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
23237 #define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
23239 #define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
23240  /* end of group LPI2C_Peripheral_Access_Layer */
23244 
23245 
23246 /* ----------------------------------------------------------------------------
23247  -- LPSPI Peripheral Access Layer
23248  ---------------------------------------------------------------------------- */
23249 
23256 typedef struct {
23257  __I uint32_t VERID;
23258  __I uint32_t PARAM;
23259  uint8_t RESERVED_0[8];
23260  __IO uint32_t CR;
23261  __IO uint32_t SR;
23262  __IO uint32_t IER;
23263  __IO uint32_t DER;
23264  __IO uint32_t CFGR0;
23265  __IO uint32_t CFGR1;
23266  uint8_t RESERVED_1[8];
23267  __IO uint32_t DMR0;
23268  __IO uint32_t DMR1;
23269  uint8_t RESERVED_2[8];
23270  __IO uint32_t CCR;
23271  uint8_t RESERVED_3[20];
23272  __IO uint32_t FCR;
23273  __I uint32_t FSR;
23274  __IO uint32_t TCR;
23275  __O uint32_t TDR;
23276  uint8_t RESERVED_4[8];
23277  __I uint32_t RSR;
23278  __I uint32_t RDR;
23279 } LPSPI_Type;
23280 
23281 /* ----------------------------------------------------------------------------
23282  -- LPSPI Register Masks
23283  ---------------------------------------------------------------------------- */
23284 
23292 #define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
23293 #define LPSPI_VERID_FEATURE_SHIFT (0U)
23297 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
23298 #define LPSPI_VERID_MINOR_MASK (0xFF0000U)
23299 #define LPSPI_VERID_MINOR_SHIFT (16U)
23302 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
23303 #define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
23304 #define LPSPI_VERID_MAJOR_SHIFT (24U)
23307 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
23312 #define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
23313 #define LPSPI_PARAM_TXFIFO_SHIFT (0U)
23316 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
23317 #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
23318 #define LPSPI_PARAM_RXFIFO_SHIFT (8U)
23321 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
23322 #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
23323 #define LPSPI_PARAM_PCSNUM_SHIFT (16U)
23326 #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
23331 #define LPSPI_CR_MEN_MASK (0x1U)
23332 #define LPSPI_CR_MEN_SHIFT (0U)
23337 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
23338 #define LPSPI_CR_RST_MASK (0x2U)
23339 #define LPSPI_CR_RST_SHIFT (1U)
23344 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
23345 #define LPSPI_CR_DOZEN_MASK (0x4U)
23346 #define LPSPI_CR_DOZEN_SHIFT (2U)
23351 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
23352 #define LPSPI_CR_DBGEN_MASK (0x8U)
23353 #define LPSPI_CR_DBGEN_SHIFT (3U)
23358 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
23359 #define LPSPI_CR_RTF_MASK (0x100U)
23360 #define LPSPI_CR_RTF_SHIFT (8U)
23365 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
23366 #define LPSPI_CR_RRF_MASK (0x200U)
23367 #define LPSPI_CR_RRF_SHIFT (9U)
23372 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
23377 #define LPSPI_SR_TDF_MASK (0x1U)
23378 #define LPSPI_SR_TDF_SHIFT (0U)
23383 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
23384 #define LPSPI_SR_RDF_MASK (0x2U)
23385 #define LPSPI_SR_RDF_SHIFT (1U)
23390 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
23391 #define LPSPI_SR_WCF_MASK (0x100U)
23392 #define LPSPI_SR_WCF_SHIFT (8U)
23397 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
23398 #define LPSPI_SR_FCF_MASK (0x200U)
23399 #define LPSPI_SR_FCF_SHIFT (9U)
23404 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
23405 #define LPSPI_SR_TCF_MASK (0x400U)
23406 #define LPSPI_SR_TCF_SHIFT (10U)
23411 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
23412 #define LPSPI_SR_TEF_MASK (0x800U)
23413 #define LPSPI_SR_TEF_SHIFT (11U)
23418 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
23419 #define LPSPI_SR_REF_MASK (0x1000U)
23420 #define LPSPI_SR_REF_SHIFT (12U)
23425 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
23426 #define LPSPI_SR_DMF_MASK (0x2000U)
23427 #define LPSPI_SR_DMF_SHIFT (13U)
23432 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
23433 #define LPSPI_SR_MBF_MASK (0x1000000U)
23434 #define LPSPI_SR_MBF_SHIFT (24U)
23439 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
23444 #define LPSPI_IER_TDIE_MASK (0x1U)
23445 #define LPSPI_IER_TDIE_SHIFT (0U)
23450 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
23451 #define LPSPI_IER_RDIE_MASK (0x2U)
23452 #define LPSPI_IER_RDIE_SHIFT (1U)
23457 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
23458 #define LPSPI_IER_WCIE_MASK (0x100U)
23459 #define LPSPI_IER_WCIE_SHIFT (8U)
23464 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
23465 #define LPSPI_IER_FCIE_MASK (0x200U)
23466 #define LPSPI_IER_FCIE_SHIFT (9U)
23471 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
23472 #define LPSPI_IER_TCIE_MASK (0x400U)
23473 #define LPSPI_IER_TCIE_SHIFT (10U)
23478 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
23479 #define LPSPI_IER_TEIE_MASK (0x800U)
23480 #define LPSPI_IER_TEIE_SHIFT (11U)
23485 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
23486 #define LPSPI_IER_REIE_MASK (0x1000U)
23487 #define LPSPI_IER_REIE_SHIFT (12U)
23492 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
23493 #define LPSPI_IER_DMIE_MASK (0x2000U)
23494 #define LPSPI_IER_DMIE_SHIFT (13U)
23499 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
23504 #define LPSPI_DER_TDDE_MASK (0x1U)
23505 #define LPSPI_DER_TDDE_SHIFT (0U)
23510 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
23511 #define LPSPI_DER_RDDE_MASK (0x2U)
23512 #define LPSPI_DER_RDDE_SHIFT (1U)
23517 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
23522 #define LPSPI_CFGR0_HREN_MASK (0x1U)
23523 #define LPSPI_CFGR0_HREN_SHIFT (0U)
23528 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
23529 #define LPSPI_CFGR0_HRPOL_MASK (0x2U)
23530 #define LPSPI_CFGR0_HRPOL_SHIFT (1U)
23535 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
23536 #define LPSPI_CFGR0_HRSEL_MASK (0x4U)
23537 #define LPSPI_CFGR0_HRSEL_SHIFT (2U)
23542 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
23543 #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
23544 #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
23549 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
23550 #define LPSPI_CFGR0_RDMO_MASK (0x200U)
23551 #define LPSPI_CFGR0_RDMO_SHIFT (9U)
23556 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
23561 #define LPSPI_CFGR1_MASTER_MASK (0x1U)
23562 #define LPSPI_CFGR1_MASTER_SHIFT (0U)
23567 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
23568 #define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
23569 #define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
23574 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
23575 #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
23576 #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
23581 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
23582 #define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
23583 #define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
23588 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
23589 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
23590 #define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
23593 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
23594 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
23595 #define LPSPI_CFGR1_MATCFG_SHIFT (16U)
23608 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
23609 #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
23610 #define LPSPI_CFGR1_PINCFG_SHIFT (24U)
23617 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
23618 #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
23619 #define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
23624 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
23625 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
23626 #define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
23631 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
23636 #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
23637 #define LPSPI_DMR0_MATCH0_SHIFT (0U)
23640 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
23645 #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
23646 #define LPSPI_DMR1_MATCH1_SHIFT (0U)
23649 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
23654 #define LPSPI_CCR_SCKDIV_MASK (0xFFU)
23655 #define LPSPI_CCR_SCKDIV_SHIFT (0U)
23658 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
23659 #define LPSPI_CCR_DBT_MASK (0xFF00U)
23660 #define LPSPI_CCR_DBT_SHIFT (8U)
23663 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
23664 #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
23665 #define LPSPI_CCR_PCSSCK_SHIFT (16U)
23668 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
23669 #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
23670 #define LPSPI_CCR_SCKPCS_SHIFT (24U)
23673 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
23678 #define LPSPI_FCR_TXWATER_MASK (0xFU)
23679 #define LPSPI_FCR_TXWATER_SHIFT (0U)
23682 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
23683 #define LPSPI_FCR_RXWATER_MASK (0xF0000U)
23684 #define LPSPI_FCR_RXWATER_SHIFT (16U)
23687 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
23692 #define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
23693 #define LPSPI_FSR_TXCOUNT_SHIFT (0U)
23696 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
23697 #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
23698 #define LPSPI_FSR_RXCOUNT_SHIFT (16U)
23701 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
23706 #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
23707 #define LPSPI_TCR_FRAMESZ_SHIFT (0U)
23710 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
23711 #define LPSPI_TCR_WIDTH_MASK (0x30000U)
23712 #define LPSPI_TCR_WIDTH_SHIFT (16U)
23719 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
23720 #define LPSPI_TCR_TXMSK_MASK (0x40000U)
23721 #define LPSPI_TCR_TXMSK_SHIFT (18U)
23726 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
23727 #define LPSPI_TCR_RXMSK_MASK (0x80000U)
23728 #define LPSPI_TCR_RXMSK_SHIFT (19U)
23733 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
23734 #define LPSPI_TCR_CONTC_MASK (0x100000U)
23735 #define LPSPI_TCR_CONTC_SHIFT (20U)
23740 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
23741 #define LPSPI_TCR_CONT_MASK (0x200000U)
23742 #define LPSPI_TCR_CONT_SHIFT (21U)
23747 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
23748 #define LPSPI_TCR_BYSW_MASK (0x400000U)
23749 #define LPSPI_TCR_BYSW_SHIFT (22U)
23754 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
23755 #define LPSPI_TCR_LSBF_MASK (0x800000U)
23756 #define LPSPI_TCR_LSBF_SHIFT (23U)
23761 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
23762 #define LPSPI_TCR_PCS_MASK (0x3000000U)
23763 #define LPSPI_TCR_PCS_SHIFT (24U)
23770 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
23771 #define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
23772 #define LPSPI_TCR_PRESCALE_SHIFT (27U)
23783 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
23784 #define LPSPI_TCR_CPHA_MASK (0x40000000U)
23785 #define LPSPI_TCR_CPHA_SHIFT (30U)
23790 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
23791 #define LPSPI_TCR_CPOL_MASK (0x80000000U)
23792 #define LPSPI_TCR_CPOL_SHIFT (31U)
23797 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
23802 #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
23803 #define LPSPI_TDR_DATA_SHIFT (0U)
23806 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
23811 #define LPSPI_RSR_SOF_MASK (0x1U)
23812 #define LPSPI_RSR_SOF_SHIFT (0U)
23817 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
23818 #define LPSPI_RSR_RXEMPTY_MASK (0x2U)
23819 #define LPSPI_RSR_RXEMPTY_SHIFT (1U)
23824 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
23829 #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
23830 #define LPSPI_RDR_DATA_SHIFT (0U)
23833 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) /* end of group LPSPI_Register_Masks */
23840 
23841 
23842 /* LPSPI - Peripheral instance base addresses */
23844 #define LPSPI1_BASE (0x40394000u)
23846 #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
23848 #define LPSPI2_BASE (0x40398000u)
23850 #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
23852 #define LPSPI3_BASE (0x4039C000u)
23854 #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
23856 #define LPSPI4_BASE (0x403A0000u)
23858 #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
23860 #define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
23862 #define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
23864 #define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
23865  /* end of group LPSPI_Peripheral_Access_Layer */
23869 
23870 
23871 /* ----------------------------------------------------------------------------
23872  -- LPUART Peripheral Access Layer
23873  ---------------------------------------------------------------------------- */
23874 
23881 typedef struct {
23882  __I uint32_t VERID;
23883  __I uint32_t PARAM;
23884  __IO uint32_t GLOBAL;
23885  __IO uint32_t PINCFG;
23886  __IO uint32_t BAUD;
23887  __IO uint32_t STAT;
23888  __IO uint32_t CTRL;
23889  __IO uint32_t DATA;
23890  __IO uint32_t MATCH;
23891  __IO uint32_t MODIR;
23892  __IO uint32_t FIFO;
23893  __IO uint32_t WATER;
23894 } LPUART_Type;
23895 
23896 /* ----------------------------------------------------------------------------
23897  -- LPUART Register Masks
23898  ---------------------------------------------------------------------------- */
23899 
23907 #define LPUART_VERID_FEATURE_MASK (0xFFFFU)
23908 #define LPUART_VERID_FEATURE_SHIFT (0U)
23913 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
23914 #define LPUART_VERID_MINOR_MASK (0xFF0000U)
23915 #define LPUART_VERID_MINOR_SHIFT (16U)
23918 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
23919 #define LPUART_VERID_MAJOR_MASK (0xFF000000U)
23920 #define LPUART_VERID_MAJOR_SHIFT (24U)
23923 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
23928 #define LPUART_PARAM_TXFIFO_MASK (0xFFU)
23929 #define LPUART_PARAM_TXFIFO_SHIFT (0U)
23932 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
23933 #define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
23934 #define LPUART_PARAM_RXFIFO_SHIFT (8U)
23937 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
23942 #define LPUART_GLOBAL_RST_MASK (0x2U)
23943 #define LPUART_GLOBAL_RST_SHIFT (1U)
23948 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
23953 #define LPUART_PINCFG_TRGSEL_MASK (0x3U)
23954 #define LPUART_PINCFG_TRGSEL_SHIFT (0U)
23961 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
23966 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
23967 #define LPUART_BAUD_SBR_SHIFT (0U)
23970 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
23971 #define LPUART_BAUD_SBNS_MASK (0x2000U)
23972 #define LPUART_BAUD_SBNS_SHIFT (13U)
23977 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
23978 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
23979 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
23984 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
23985 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
23986 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
23991 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
23992 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
23993 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
23998 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
23999 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
24000 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
24005 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
24006 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
24007 #define LPUART_BAUD_MATCFG_SHIFT (18U)
24014 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
24015 #define LPUART_BAUD_RIDMAE_MASK (0x100000U)
24016 #define LPUART_BAUD_RIDMAE_SHIFT (20U)
24021 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
24022 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
24023 #define LPUART_BAUD_RDMAE_SHIFT (21U)
24028 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
24029 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
24030 #define LPUART_BAUD_TDMAE_SHIFT (23U)
24035 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
24036 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
24037 #define LPUART_BAUD_OSR_SHIFT (24U)
24072 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
24073 #define LPUART_BAUD_M10_MASK (0x20000000U)
24074 #define LPUART_BAUD_M10_SHIFT (29U)
24079 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
24080 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
24081 #define LPUART_BAUD_MAEN2_SHIFT (30U)
24086 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
24087 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
24088 #define LPUART_BAUD_MAEN1_SHIFT (31U)
24093 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
24098 #define LPUART_STAT_MA2F_MASK (0x4000U)
24099 #define LPUART_STAT_MA2F_SHIFT (14U)
24104 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
24105 #define LPUART_STAT_MA1F_MASK (0x8000U)
24106 #define LPUART_STAT_MA1F_SHIFT (15U)
24111 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
24112 #define LPUART_STAT_PF_MASK (0x10000U)
24113 #define LPUART_STAT_PF_SHIFT (16U)
24118 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
24119 #define LPUART_STAT_FE_MASK (0x20000U)
24120 #define LPUART_STAT_FE_SHIFT (17U)
24125 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
24126 #define LPUART_STAT_NF_MASK (0x40000U)
24127 #define LPUART_STAT_NF_SHIFT (18U)
24132 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
24133 #define LPUART_STAT_OR_MASK (0x80000U)
24134 #define LPUART_STAT_OR_SHIFT (19U)
24139 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
24140 #define LPUART_STAT_IDLE_MASK (0x100000U)
24141 #define LPUART_STAT_IDLE_SHIFT (20U)
24146 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
24147 #define LPUART_STAT_RDRF_MASK (0x200000U)
24148 #define LPUART_STAT_RDRF_SHIFT (21U)
24153 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
24154 #define LPUART_STAT_TC_MASK (0x400000U)
24155 #define LPUART_STAT_TC_SHIFT (22U)
24160 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
24161 #define LPUART_STAT_TDRE_MASK (0x800000U)
24162 #define LPUART_STAT_TDRE_SHIFT (23U)
24167 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
24168 #define LPUART_STAT_RAF_MASK (0x1000000U)
24169 #define LPUART_STAT_RAF_SHIFT (24U)
24174 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
24175 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
24176 #define LPUART_STAT_LBKDE_SHIFT (25U)
24181 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
24182 #define LPUART_STAT_BRK13_MASK (0x4000000U)
24183 #define LPUART_STAT_BRK13_SHIFT (26U)
24188 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
24189 #define LPUART_STAT_RWUID_MASK (0x8000000U)
24190 #define LPUART_STAT_RWUID_SHIFT (27U)
24197 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
24198 #define LPUART_STAT_RXINV_MASK (0x10000000U)
24199 #define LPUART_STAT_RXINV_SHIFT (28U)
24204 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
24205 #define LPUART_STAT_MSBF_MASK (0x20000000U)
24206 #define LPUART_STAT_MSBF_SHIFT (29U)
24214 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
24215 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
24216 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
24221 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
24222 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
24223 #define LPUART_STAT_LBKDIF_SHIFT (31U)
24228 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
24233 #define LPUART_CTRL_PT_MASK (0x1U)
24234 #define LPUART_CTRL_PT_SHIFT (0U)
24239 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
24240 #define LPUART_CTRL_PE_MASK (0x2U)
24241 #define LPUART_CTRL_PE_SHIFT (1U)
24246 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
24247 #define LPUART_CTRL_ILT_MASK (0x4U)
24248 #define LPUART_CTRL_ILT_SHIFT (2U)
24253 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
24254 #define LPUART_CTRL_WAKE_MASK (0x8U)
24255 #define LPUART_CTRL_WAKE_SHIFT (3U)
24260 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
24261 #define LPUART_CTRL_M_MASK (0x10U)
24262 #define LPUART_CTRL_M_SHIFT (4U)
24267 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
24268 #define LPUART_CTRL_RSRC_MASK (0x20U)
24269 #define LPUART_CTRL_RSRC_SHIFT (5U)
24274 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
24275 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
24276 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
24281 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
24282 #define LPUART_CTRL_LOOPS_MASK (0x80U)
24283 #define LPUART_CTRL_LOOPS_SHIFT (7U)
24288 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
24289 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
24290 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
24301 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
24302 #define LPUART_CTRL_M7_MASK (0x800U)
24303 #define LPUART_CTRL_M7_SHIFT (11U)
24308 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
24309 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
24310 #define LPUART_CTRL_MA2IE_SHIFT (14U)
24315 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
24316 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
24317 #define LPUART_CTRL_MA1IE_SHIFT (15U)
24322 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
24323 #define LPUART_CTRL_SBK_MASK (0x10000U)
24324 #define LPUART_CTRL_SBK_SHIFT (16U)
24329 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
24330 #define LPUART_CTRL_RWU_MASK (0x20000U)
24331 #define LPUART_CTRL_RWU_SHIFT (17U)
24336 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
24337 #define LPUART_CTRL_RE_MASK (0x40000U)
24338 #define LPUART_CTRL_RE_SHIFT (18U)
24343 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
24344 #define LPUART_CTRL_TE_MASK (0x80000U)
24345 #define LPUART_CTRL_TE_SHIFT (19U)
24350 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
24351 #define LPUART_CTRL_ILIE_MASK (0x100000U)
24352 #define LPUART_CTRL_ILIE_SHIFT (20U)
24357 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
24358 #define LPUART_CTRL_RIE_MASK (0x200000U)
24359 #define LPUART_CTRL_RIE_SHIFT (21U)
24364 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
24365 #define LPUART_CTRL_TCIE_MASK (0x400000U)
24366 #define LPUART_CTRL_TCIE_SHIFT (22U)
24371 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
24372 #define LPUART_CTRL_TIE_MASK (0x800000U)
24373 #define LPUART_CTRL_TIE_SHIFT (23U)
24378 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
24379 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
24380 #define LPUART_CTRL_PEIE_SHIFT (24U)
24385 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
24386 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
24387 #define LPUART_CTRL_FEIE_SHIFT (25U)
24392 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
24393 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
24394 #define LPUART_CTRL_NEIE_SHIFT (26U)
24399 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
24400 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
24401 #define LPUART_CTRL_ORIE_SHIFT (27U)
24406 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
24407 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
24408 #define LPUART_CTRL_TXINV_SHIFT (28U)
24413 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
24414 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
24415 #define LPUART_CTRL_TXDIR_SHIFT (29U)
24420 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
24421 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
24422 #define LPUART_CTRL_R9T8_SHIFT (30U)
24425 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
24426 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
24427 #define LPUART_CTRL_R8T9_SHIFT (31U)
24430 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
24435 #define LPUART_DATA_R0T0_MASK (0x1U)
24436 #define LPUART_DATA_R0T0_SHIFT (0U)
24439 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
24440 #define LPUART_DATA_R1T1_MASK (0x2U)
24441 #define LPUART_DATA_R1T1_SHIFT (1U)
24444 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
24445 #define LPUART_DATA_R2T2_MASK (0x4U)
24446 #define LPUART_DATA_R2T2_SHIFT (2U)
24449 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
24450 #define LPUART_DATA_R3T3_MASK (0x8U)
24451 #define LPUART_DATA_R3T3_SHIFT (3U)
24454 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
24455 #define LPUART_DATA_R4T4_MASK (0x10U)
24456 #define LPUART_DATA_R4T4_SHIFT (4U)
24459 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
24460 #define LPUART_DATA_R5T5_MASK (0x20U)
24461 #define LPUART_DATA_R5T5_SHIFT (5U)
24464 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
24465 #define LPUART_DATA_R6T6_MASK (0x40U)
24466 #define LPUART_DATA_R6T6_SHIFT (6U)
24469 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
24470 #define LPUART_DATA_R7T7_MASK (0x80U)
24471 #define LPUART_DATA_R7T7_SHIFT (7U)
24474 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
24475 #define LPUART_DATA_R8T8_MASK (0x100U)
24476 #define LPUART_DATA_R8T8_SHIFT (8U)
24479 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
24480 #define LPUART_DATA_R9T9_MASK (0x200U)
24481 #define LPUART_DATA_R9T9_SHIFT (9U)
24484 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
24485 #define LPUART_DATA_IDLINE_MASK (0x800U)
24486 #define LPUART_DATA_IDLINE_SHIFT (11U)
24491 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
24492 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
24493 #define LPUART_DATA_RXEMPT_SHIFT (12U)
24498 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
24499 #define LPUART_DATA_FRETSC_MASK (0x2000U)
24500 #define LPUART_DATA_FRETSC_SHIFT (13U)
24505 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
24506 #define LPUART_DATA_PARITYE_MASK (0x4000U)
24507 #define LPUART_DATA_PARITYE_SHIFT (14U)
24512 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
24513 #define LPUART_DATA_NOISY_MASK (0x8000U)
24514 #define LPUART_DATA_NOISY_SHIFT (15U)
24519 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
24524 #define LPUART_MATCH_MA1_MASK (0x3FFU)
24525 #define LPUART_MATCH_MA1_SHIFT (0U)
24528 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
24529 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
24530 #define LPUART_MATCH_MA2_SHIFT (16U)
24533 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
24538 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
24539 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
24547 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
24548 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
24549 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
24556 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
24557 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
24558 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
24563 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
24564 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
24565 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
24572 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
24573 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
24574 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
24579 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
24580 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
24581 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
24586 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
24587 #define LPUART_MODIR_RTSWATER_MASK (0x300U)
24588 #define LPUART_MODIR_RTSWATER_SHIFT (8U)
24591 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
24592 #define LPUART_MODIR_TNP_MASK (0x30000U)
24593 #define LPUART_MODIR_TNP_SHIFT (16U)
24600 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
24601 #define LPUART_MODIR_IREN_MASK (0x40000U)
24602 #define LPUART_MODIR_IREN_SHIFT (18U)
24607 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
24612 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
24613 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
24624 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
24625 #define LPUART_FIFO_RXFE_MASK (0x8U)
24626 #define LPUART_FIFO_RXFE_SHIFT (3U)
24631 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
24632 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
24633 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
24644 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
24645 #define LPUART_FIFO_TXFE_MASK (0x80U)
24646 #define LPUART_FIFO_TXFE_SHIFT (7U)
24651 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
24652 #define LPUART_FIFO_RXUFE_MASK (0x100U)
24653 #define LPUART_FIFO_RXUFE_SHIFT (8U)
24658 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
24659 #define LPUART_FIFO_TXOFE_MASK (0x200U)
24660 #define LPUART_FIFO_TXOFE_SHIFT (9U)
24665 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
24666 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
24667 #define LPUART_FIFO_RXIDEN_SHIFT (10U)
24678 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
24679 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
24680 #define LPUART_FIFO_RXFLUSH_SHIFT (14U)
24685 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
24686 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
24687 #define LPUART_FIFO_TXFLUSH_SHIFT (15U)
24692 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
24693 #define LPUART_FIFO_RXUF_MASK (0x10000U)
24694 #define LPUART_FIFO_RXUF_SHIFT (16U)
24699 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
24700 #define LPUART_FIFO_TXOF_MASK (0x20000U)
24701 #define LPUART_FIFO_TXOF_SHIFT (17U)
24706 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
24707 #define LPUART_FIFO_RXEMPT_MASK (0x400000U)
24708 #define LPUART_FIFO_RXEMPT_SHIFT (22U)
24713 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
24714 #define LPUART_FIFO_TXEMPT_MASK (0x800000U)
24715 #define LPUART_FIFO_TXEMPT_SHIFT (23U)
24720 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
24725 #define LPUART_WATER_TXWATER_MASK (0x3U)
24726 #define LPUART_WATER_TXWATER_SHIFT (0U)
24729 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
24730 #define LPUART_WATER_TXCOUNT_MASK (0x700U)
24731 #define LPUART_WATER_TXCOUNT_SHIFT (8U)
24734 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
24735 #define LPUART_WATER_RXWATER_MASK (0x30000U)
24736 #define LPUART_WATER_RXWATER_SHIFT (16U)
24739 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
24740 #define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
24741 #define LPUART_WATER_RXCOUNT_SHIFT (24U)
24744 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) /* end of group LPUART_Register_Masks */
24751 
24752 
24753 /* LPUART - Peripheral instance base addresses */
24755 #define LPUART1_BASE (0x40184000u)
24757 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
24759 #define LPUART2_BASE (0x40188000u)
24761 #define LPUART2 ((LPUART_Type *)LPUART2_BASE)
24763 #define LPUART3_BASE (0x4018C000u)
24765 #define LPUART3 ((LPUART_Type *)LPUART3_BASE)
24767 #define LPUART4_BASE (0x40190000u)
24769 #define LPUART4 ((LPUART_Type *)LPUART4_BASE)
24771 #define LPUART5_BASE (0x40194000u)
24773 #define LPUART5 ((LPUART_Type *)LPUART5_BASE)
24775 #define LPUART6_BASE (0x40198000u)
24777 #define LPUART6 ((LPUART_Type *)LPUART6_BASE)
24779 #define LPUART7_BASE (0x4019C000u)
24781 #define LPUART7 ((LPUART_Type *)LPUART7_BASE)
24783 #define LPUART8_BASE (0x401A0000u)
24785 #define LPUART8 ((LPUART_Type *)LPUART8_BASE)
24787 #define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
24789 #define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
24791 #define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
24792  /* end of group LPUART_Peripheral_Access_Layer */
24796 
24797 
24798 /* ----------------------------------------------------------------------------
24799  -- OCOTP Peripheral Access Layer
24800  ---------------------------------------------------------------------------- */
24801 
24808 typedef struct {
24809  __IO uint32_t CTRL;
24810  __IO uint32_t CTRL_SET;
24811  __IO uint32_t CTRL_CLR;
24812  __IO uint32_t CTRL_TOG;
24813  __IO uint32_t TIMING;
24814  uint8_t RESERVED_0[12];
24815  __IO uint32_t DATA;
24816  uint8_t RESERVED_1[12];
24817  __IO uint32_t READ_CTRL;
24818  uint8_t RESERVED_2[12];
24819  __IO uint32_t READ_FUSE_DATA;
24820  uint8_t RESERVED_3[12];
24821  __IO uint32_t SW_STICKY;
24822  uint8_t RESERVED_4[12];
24823  __IO uint32_t SCS;
24824  __IO uint32_t SCS_SET;
24825  __IO uint32_t SCS_CLR;
24826  __IO uint32_t SCS_TOG;
24827  uint8_t RESERVED_5[32];
24828  __I uint32_t VERSION;
24829  uint8_t RESERVED_6[108];
24830  __IO uint32_t TIMING2;
24831  uint8_t RESERVED_7[764];
24832  __IO uint32_t LOCK;
24833  uint8_t RESERVED_8[12];
24834  __IO uint32_t CFG0;
24835  uint8_t RESERVED_9[12];
24836  __IO uint32_t CFG1;
24837  uint8_t RESERVED_10[12];
24838  __IO uint32_t CFG2;
24839  uint8_t RESERVED_11[12];
24840  __IO uint32_t CFG3;
24841  uint8_t RESERVED_12[12];
24842  __IO uint32_t CFG4;
24843  uint8_t RESERVED_13[12];
24844  __IO uint32_t CFG5;
24845  uint8_t RESERVED_14[12];
24846  __IO uint32_t CFG6;
24847  uint8_t RESERVED_15[12];
24848  __IO uint32_t MEM0;
24849  uint8_t RESERVED_16[12];
24850  __IO uint32_t MEM1;
24851  uint8_t RESERVED_17[12];
24852  __IO uint32_t MEM2;
24853  uint8_t RESERVED_18[12];
24854  __IO uint32_t MEM3;
24855  uint8_t RESERVED_19[12];
24856  __IO uint32_t MEM4;
24857  uint8_t RESERVED_20[12];
24858  __IO uint32_t ANA0;
24859  uint8_t RESERVED_21[12];
24860  __IO uint32_t ANA1;
24861  uint8_t RESERVED_22[12];
24862  __IO uint32_t ANA2;
24863  uint8_t RESERVED_23[140];
24864  __IO uint32_t SRK0;
24865  uint8_t RESERVED_24[12];
24866  __IO uint32_t SRK1;
24867  uint8_t RESERVED_25[12];
24868  __IO uint32_t SRK2;
24869  uint8_t RESERVED_26[12];
24870  __IO uint32_t SRK3;
24871  uint8_t RESERVED_27[12];
24872  __IO uint32_t SRK4;
24873  uint8_t RESERVED_28[12];
24874  __IO uint32_t SRK5;
24875  uint8_t RESERVED_29[12];
24876  __IO uint32_t SRK6;
24877  uint8_t RESERVED_30[12];
24878  __IO uint32_t SRK7;
24879  uint8_t RESERVED_31[12];
24880  __IO uint32_t SJC_RESP0;
24881  uint8_t RESERVED_32[12];
24882  __IO uint32_t SJC_RESP1;
24883  uint8_t RESERVED_33[12];
24884  __IO uint32_t MAC0;
24885  uint8_t RESERVED_34[12];
24886  __IO uint32_t MAC1;
24887  uint8_t RESERVED_35[12];
24888  __IO uint32_t GP3;
24889  uint8_t RESERVED_36[28];
24890  __IO uint32_t GP1;
24891  uint8_t RESERVED_37[12];
24892  __IO uint32_t GP2;
24893  uint8_t RESERVED_38[12];
24894  __IO uint32_t SW_GP1;
24895  uint8_t RESERVED_39[12];
24896  __IO uint32_t SW_GP20;
24897  uint8_t RESERVED_40[12];
24898  __IO uint32_t SW_GP21;
24899  uint8_t RESERVED_41[12];
24900  __IO uint32_t SW_GP22;
24901  uint8_t RESERVED_42[12];
24902  __IO uint32_t SW_GP23;
24903  uint8_t RESERVED_43[12];
24904  __IO uint32_t MISC_CONF0;
24905  uint8_t RESERVED_44[12];
24906  __IO uint32_t MISC_CONF1;
24907  uint8_t RESERVED_45[12];
24908  __IO uint32_t SRK_REVOKE;
24909 } OCOTP_Type;
24910 
24911 /* ----------------------------------------------------------------------------
24912  -- OCOTP Register Masks
24913  ---------------------------------------------------------------------------- */
24914 
24922 #define OCOTP_CTRL_ADDR_MASK (0x3FU)
24923 #define OCOTP_CTRL_ADDR_SHIFT (0U)
24926 #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
24927 #define OCOTP_CTRL_BUSY_MASK (0x100U)
24928 #define OCOTP_CTRL_BUSY_SHIFT (8U)
24933 #define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
24934 #define OCOTP_CTRL_ERROR_MASK (0x200U)
24935 #define OCOTP_CTRL_ERROR_SHIFT (9U)
24940 #define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
24941 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
24942 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
24947 #define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
24948 #define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
24949 #define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
24954 #define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
24959 #define OCOTP_CTRL_SET_ADDR_MASK (0x3FU)
24960 #define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
24963 #define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
24964 #define OCOTP_CTRL_SET_BUSY_MASK (0x100U)
24965 #define OCOTP_CTRL_SET_BUSY_SHIFT (8U)
24968 #define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
24969 #define OCOTP_CTRL_SET_ERROR_MASK (0x200U)
24970 #define OCOTP_CTRL_SET_ERROR_SHIFT (9U)
24973 #define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
24974 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
24975 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
24978 #define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
24979 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
24980 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
24983 #define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
24988 #define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)
24989 #define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
24992 #define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
24993 #define OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
24994 #define OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
24997 #define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
24998 #define OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
24999 #define OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
25002 #define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
25003 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
25004 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
25007 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
25008 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
25009 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
25012 #define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
25017 #define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)
25018 #define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
25021 #define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
25022 #define OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
25023 #define OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
25026 #define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
25027 #define OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
25028 #define OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
25031 #define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
25032 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
25033 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
25036 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
25037 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
25038 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
25041 #define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
25046 #define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
25047 #define OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
25050 #define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
25051 #define OCOTP_TIMING_RELAX_MASK (0xF000U)
25052 #define OCOTP_TIMING_RELAX_SHIFT (12U)
25055 #define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
25056 #define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
25057 #define OCOTP_TIMING_STROBE_READ_SHIFT (16U)
25060 #define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
25061 #define OCOTP_TIMING_WAIT_MASK (0xFC00000U)
25062 #define OCOTP_TIMING_WAIT_SHIFT (22U)
25065 #define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
25070 #define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
25071 #define OCOTP_DATA_DATA_SHIFT (0U)
25074 #define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
25079 #define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
25080 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
25083 #define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
25088 #define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
25089 #define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
25092 #define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
25097 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
25098 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
25103 #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
25104 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
25105 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
25110 #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
25115 #define OCOTP_SCS_HAB_JDE_MASK (0x1U)
25116 #define OCOTP_SCS_HAB_JDE_SHIFT (0U)
25121 #define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
25122 #define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
25123 #define OCOTP_SCS_SPARE_SHIFT (1U)
25126 #define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
25127 #define OCOTP_SCS_LOCK_MASK (0x80000000U)
25128 #define OCOTP_SCS_LOCK_SHIFT (31U)
25134 #define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
25139 #define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
25140 #define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
25143 #define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
25144 #define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
25145 #define OCOTP_SCS_SET_SPARE_SHIFT (1U)
25148 #define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
25149 #define OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
25150 #define OCOTP_SCS_SET_LOCK_SHIFT (31U)
25153 #define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
25158 #define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
25159 #define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
25162 #define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
25163 #define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
25164 #define OCOTP_SCS_CLR_SPARE_SHIFT (1U)
25167 #define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
25168 #define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
25169 #define OCOTP_SCS_CLR_LOCK_SHIFT (31U)
25172 #define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
25177 #define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
25178 #define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
25181 #define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
25182 #define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
25183 #define OCOTP_SCS_TOG_SPARE_SHIFT (1U)
25186 #define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
25187 #define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
25188 #define OCOTP_SCS_TOG_LOCK_SHIFT (31U)
25191 #define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
25196 #define OCOTP_VERSION_STEP_MASK (0xFFFFU)
25197 #define OCOTP_VERSION_STEP_SHIFT (0U)
25200 #define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
25201 #define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
25202 #define OCOTP_VERSION_MINOR_SHIFT (16U)
25205 #define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
25206 #define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
25207 #define OCOTP_VERSION_MAJOR_SHIFT (24U)
25210 #define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
25215 #define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)
25216 #define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)
25219 #define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
25220 #define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)
25221 #define OCOTP_TIMING2_RELAX_READ_SHIFT (16U)
25224 #define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
25225 #define OCOTP_TIMING2_RELAX1_MASK (0x3FC00000U)
25226 #define OCOTP_TIMING2_RELAX1_SHIFT (22U)
25229 #define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK)
25234 #define OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
25235 #define OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
25238 #define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
25239 #define OCOTP_LOCK_SJC_RESP_MASK (0x40U)
25240 #define OCOTP_LOCK_SJC_RESP_SHIFT (6U)
25246 #define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
25247 #define OCOTP_LOCK_MAC_ADDR_MASK (0x300U)
25248 #define OCOTP_LOCK_MAC_ADDR_SHIFT (8U)
25251 #define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
25252 #define OCOTP_LOCK_GP1_MASK (0xC00U)
25253 #define OCOTP_LOCK_GP1_SHIFT (10U)
25256 #define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
25257 #define OCOTP_LOCK_GP2_MASK (0x3000U)
25258 #define OCOTP_LOCK_GP2_SHIFT (12U)
25261 #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
25262 #define OCOTP_LOCK_SW_GP1_MASK (0x10000U)
25263 #define OCOTP_LOCK_SW_GP1_SHIFT (16U)
25268 #define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
25269 #define OCOTP_LOCK_ANALOG_MASK (0xC0000U)
25270 #define OCOTP_LOCK_ANALOG_SHIFT (18U)
25273 #define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
25274 #define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)
25275 #define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)
25280 #define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
25281 #define OCOTP_LOCK_MISC_CONF_MASK (0x400000U)
25282 #define OCOTP_LOCK_MISC_CONF_SHIFT (22U)
25287 #define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
25288 #define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)
25289 #define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)
25294 #define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
25295 #define OCOTP_LOCK_GP3_MASK (0xC000000U)
25296 #define OCOTP_LOCK_GP3_SHIFT (26U)
25299 #define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
25300 #define OCOTP_LOCK_FIELD_RETURN_MASK (0x80000000U)
25301 #define OCOTP_LOCK_FIELD_RETURN_SHIFT (31U)
25306 #define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
25311 #define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)
25312 #define OCOTP_CFG0_BITS_SHIFT (0U)
25315 #define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
25320 #define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)
25321 #define OCOTP_CFG1_BITS_SHIFT (0U)
25324 #define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
25329 #define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)
25330 #define OCOTP_CFG2_BITS_SHIFT (0U)
25333 #define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
25338 #define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)
25339 #define OCOTP_CFG3_BITS_SHIFT (0U)
25342 #define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
25347 #define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)
25348 #define OCOTP_CFG4_BITS_SHIFT (0U)
25351 #define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
25356 #define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)
25357 #define OCOTP_CFG5_BITS_SHIFT (0U)
25360 #define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
25365 #define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)
25366 #define OCOTP_CFG6_BITS_SHIFT (0U)
25369 #define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
25374 #define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)
25375 #define OCOTP_MEM0_BITS_SHIFT (0U)
25378 #define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
25383 #define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)
25384 #define OCOTP_MEM1_BITS_SHIFT (0U)
25387 #define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
25392 #define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)
25393 #define OCOTP_MEM2_BITS_SHIFT (0U)
25396 #define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
25401 #define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)
25402 #define OCOTP_MEM3_BITS_SHIFT (0U)
25405 #define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
25410 #define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)
25411 #define OCOTP_MEM4_BITS_SHIFT (0U)
25414 #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
25419 #define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
25420 #define OCOTP_ANA0_BITS_SHIFT (0U)
25423 #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
25428 #define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
25429 #define OCOTP_ANA1_BITS_SHIFT (0U)
25432 #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
25437 #define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)
25438 #define OCOTP_ANA2_BITS_SHIFT (0U)
25441 #define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
25446 #define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
25447 #define OCOTP_SRK0_BITS_SHIFT (0U)
25450 #define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
25455 #define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
25456 #define OCOTP_SRK1_BITS_SHIFT (0U)
25459 #define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
25464 #define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
25465 #define OCOTP_SRK2_BITS_SHIFT (0U)
25468 #define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
25473 #define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
25474 #define OCOTP_SRK3_BITS_SHIFT (0U)
25477 #define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
25482 #define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
25483 #define OCOTP_SRK4_BITS_SHIFT (0U)
25486 #define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
25491 #define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
25492 #define OCOTP_SRK5_BITS_SHIFT (0U)
25495 #define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
25500 #define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
25501 #define OCOTP_SRK6_BITS_SHIFT (0U)
25504 #define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
25509 #define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
25510 #define OCOTP_SRK7_BITS_SHIFT (0U)
25513 #define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
25518 #define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
25519 #define OCOTP_SJC_RESP0_BITS_SHIFT (0U)
25522 #define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
25527 #define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
25528 #define OCOTP_SJC_RESP1_BITS_SHIFT (0U)
25531 #define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
25536 #define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)
25537 #define OCOTP_MAC0_BITS_SHIFT (0U)
25540 #define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
25545 #define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)
25546 #define OCOTP_MAC1_BITS_SHIFT (0U)
25549 #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
25554 #define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU)
25555 #define OCOTP_GP3_BITS_SHIFT (0U)
25558 #define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)
25563 #define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)
25564 #define OCOTP_GP1_BITS_SHIFT (0U)
25567 #define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
25572 #define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)
25573 #define OCOTP_GP2_BITS_SHIFT (0U)
25576 #define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
25581 #define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)
25582 #define OCOTP_SW_GP1_BITS_SHIFT (0U)
25585 #define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
25590 #define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)
25591 #define OCOTP_SW_GP20_BITS_SHIFT (0U)
25594 #define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
25599 #define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)
25600 #define OCOTP_SW_GP21_BITS_SHIFT (0U)
25603 #define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
25608 #define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)
25609 #define OCOTP_SW_GP22_BITS_SHIFT (0U)
25612 #define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
25617 #define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)
25618 #define OCOTP_SW_GP23_BITS_SHIFT (0U)
25621 #define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
25626 #define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)
25627 #define OCOTP_MISC_CONF0_BITS_SHIFT (0U)
25630 #define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
25635 #define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)
25636 #define OCOTP_MISC_CONF1_BITS_SHIFT (0U)
25639 #define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
25644 #define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
25645 #define OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
25648 #define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) /* end of group OCOTP_Register_Masks */
25655 
25656 
25657 /* OCOTP - Peripheral instance base addresses */
25659 #define OCOTP_BASE (0x401F4000u)
25661 #define OCOTP ((OCOTP_Type *)OCOTP_BASE)
25663 #define OCOTP_BASE_ADDRS { OCOTP_BASE }
25665 #define OCOTP_BASE_PTRS { OCOTP }
25666  /* end of group OCOTP_Peripheral_Access_Layer */
25670 
25671 
25672 /* ----------------------------------------------------------------------------
25673  -- PGC Peripheral Access Layer
25674  ---------------------------------------------------------------------------- */
25675 
25682 typedef struct {
25683  uint8_t RESERVED_0[544];
25684  __IO uint32_t MEGA_CTRL;
25685  __IO uint32_t MEGA_PUPSCR;
25686  __IO uint32_t MEGA_PDNSCR;
25687  __IO uint32_t MEGA_SR;
25688  uint8_t RESERVED_1[112];
25689  __IO uint32_t CPU_CTRL;
25690  __IO uint32_t CPU_PUPSCR;
25691  __IO uint32_t CPU_PDNSCR;
25692  __IO uint32_t CPU_SR;
25693 } PGC_Type;
25694 
25695 /* ----------------------------------------------------------------------------
25696  -- PGC Register Masks
25697  ---------------------------------------------------------------------------- */
25698 
25706 #define PGC_MEGA_CTRL_PCR_MASK (0x1U)
25707 #define PGC_MEGA_CTRL_PCR_SHIFT (0U)
25712 #define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
25717 #define PGC_MEGA_PUPSCR_SW_MASK (0x3FU)
25718 #define PGC_MEGA_PUPSCR_SW_SHIFT (0U)
25719 #define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
25720 #define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)
25721 #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)
25722 #define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
25727 #define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)
25728 #define PGC_MEGA_PDNSCR_ISO_SHIFT (0U)
25729 #define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
25730 #define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)
25731 #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)
25732 #define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
25737 #define PGC_MEGA_SR_PSR_MASK (0x1U)
25738 #define PGC_MEGA_SR_PSR_SHIFT (0U)
25743 #define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
25748 #define PGC_CPU_CTRL_PCR_MASK (0x1U)
25749 #define PGC_CPU_CTRL_PCR_SHIFT (0U)
25754 #define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
25759 #define PGC_CPU_PUPSCR_SW_MASK (0x3FU)
25760 #define PGC_CPU_PUPSCR_SW_SHIFT (0U)
25761 #define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
25762 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)
25763 #define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)
25764 #define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
25769 #define PGC_CPU_PDNSCR_ISO_MASK (0x3FU)
25770 #define PGC_CPU_PDNSCR_ISO_SHIFT (0U)
25771 #define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
25772 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)
25773 #define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)
25774 #define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
25779 #define PGC_CPU_SR_PSR_MASK (0x1U)
25780 #define PGC_CPU_SR_PSR_SHIFT (0U)
25785 #define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) /* end of group PGC_Register_Masks */
25792 
25793 
25794 /* PGC - Peripheral instance base addresses */
25796 #define PGC_BASE (0x400F4000u)
25798 #define PGC ((PGC_Type *)PGC_BASE)
25800 #define PGC_BASE_ADDRS { PGC_BASE }
25802 #define PGC_BASE_PTRS { PGC }
25803  /* end of group PGC_Peripheral_Access_Layer */
25807 
25808 
25809 /* ----------------------------------------------------------------------------
25810  -- PIT Peripheral Access Layer
25811  ---------------------------------------------------------------------------- */
25812 
25819 typedef struct {
25820  __IO uint32_t MCR;
25821  uint8_t RESERVED_0[220];
25822  __I uint32_t LTMR64H;
25823  __I uint32_t LTMR64L;
25824  uint8_t RESERVED_1[24];
25825  struct { /* offset: 0x100, array step: 0x10 */
25826  __IO uint32_t LDVAL;
25827  __I uint32_t CVAL;
25828  __IO uint32_t TCTRL;
25829  __IO uint32_t TFLG;
25830  } CHANNEL[4];
25831 } PIT_Type;
25832 
25833 /* ----------------------------------------------------------------------------
25834  -- PIT Register Masks
25835  ---------------------------------------------------------------------------- */
25836 
25844 #define PIT_MCR_FRZ_MASK (0x1U)
25845 #define PIT_MCR_FRZ_SHIFT (0U)
25850 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
25851 #define PIT_MCR_MDIS_MASK (0x2U)
25852 #define PIT_MCR_MDIS_SHIFT (1U)
25857 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
25862 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
25863 #define PIT_LTMR64H_LTH_SHIFT (0U)
25866 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
25871 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
25872 #define PIT_LTMR64L_LTL_SHIFT (0U)
25875 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
25880 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
25881 #define PIT_LDVAL_TSV_SHIFT (0U)
25884 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
25887 /* The count of PIT_LDVAL */
25888 #define PIT_LDVAL_COUNT (4U)
25889 
25892 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
25893 #define PIT_CVAL_TVL_SHIFT (0U)
25896 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
25899 /* The count of PIT_CVAL */
25900 #define PIT_CVAL_COUNT (4U)
25901 
25904 #define PIT_TCTRL_TEN_MASK (0x1U)
25905 #define PIT_TCTRL_TEN_SHIFT (0U)
25910 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
25911 #define PIT_TCTRL_TIE_MASK (0x2U)
25912 #define PIT_TCTRL_TIE_SHIFT (1U)
25917 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
25918 #define PIT_TCTRL_CHN_MASK (0x4U)
25919 #define PIT_TCTRL_CHN_SHIFT (2U)
25924 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
25927 /* The count of PIT_TCTRL */
25928 #define PIT_TCTRL_COUNT (4U)
25929 
25932 #define PIT_TFLG_TIF_MASK (0x1U)
25933 #define PIT_TFLG_TIF_SHIFT (0U)
25938 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
25941 /* The count of PIT_TFLG */
25942 #define PIT_TFLG_COUNT (4U)
25943 
25944  /* end of group PIT_Register_Masks */
25948 
25949 
25950 /* PIT - Peripheral instance base addresses */
25952 #define PIT_BASE (0x40084000u)
25954 #define PIT ((PIT_Type *)PIT_BASE)
25956 #define PIT_BASE_ADDRS { PIT_BASE }
25958 #define PIT_BASE_PTRS { PIT }
25960 #define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
25961  /* end of group PIT_Peripheral_Access_Layer */
25965 
25966 
25967 /* ----------------------------------------------------------------------------
25968  -- PMU Peripheral Access Layer
25969  ---------------------------------------------------------------------------- */
25970 
25977 typedef struct {
25978  uint8_t RESERVED_0[272];
25979  __IO uint32_t REG_1P1;
25980  __IO uint32_t REG_1P1_SET;
25981  __IO uint32_t REG_1P1_CLR;
25982  __IO uint32_t REG_1P1_TOG;
25983  __IO uint32_t REG_3P0;
25984  __IO uint32_t REG_3P0_SET;
25985  __IO uint32_t REG_3P0_CLR;
25986  __IO uint32_t REG_3P0_TOG;
25987  __IO uint32_t REG_2P5;
25988  __IO uint32_t REG_2P5_SET;
25989  __IO uint32_t REG_2P5_CLR;
25990  __IO uint32_t REG_2P5_TOG;
25991  __IO uint32_t REG_CORE;
25992  __IO uint32_t REG_CORE_SET;
25993  __IO uint32_t REG_CORE_CLR;
25994  __IO uint32_t REG_CORE_TOG;
25995  __IO uint32_t MISC0;
25996  __IO uint32_t MISC0_SET;
25997  __IO uint32_t MISC0_CLR;
25998  __IO uint32_t MISC0_TOG;
25999  __IO uint32_t MISC1;
26000  __IO uint32_t MISC1_SET;
26001  __IO uint32_t MISC1_CLR;
26002  __IO uint32_t MISC1_TOG;
26003  __IO uint32_t MISC2;
26004  __IO uint32_t MISC2_SET;
26005  __IO uint32_t MISC2_CLR;
26006  __IO uint32_t MISC2_TOG;
26007 } PMU_Type;
26008 
26009 /* ----------------------------------------------------------------------------
26010  -- PMU Register Masks
26011  ---------------------------------------------------------------------------- */
26012 
26020 #define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
26021 #define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
26022 #define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
26023 #define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
26024 #define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
26025 #define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
26026 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
26027 #define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
26028 #define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
26029 #define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
26030 #define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
26031 #define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
26032 #define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
26033 #define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
26034 #define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
26035 #define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
26036 #define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
26042 #define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
26043 #define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
26044 #define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
26045 #define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
26046 #define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
26047 #define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
26048 #define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
26049 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
26050 #define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
26051 #define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
26052 #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
26053 #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
26058 #define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
26063 #define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
26064 #define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
26065 #define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
26066 #define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
26067 #define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
26068 #define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
26069 #define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
26070 #define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
26071 #define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
26072 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
26073 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
26074 #define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
26075 #define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
26076 #define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
26077 #define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
26078 #define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
26079 #define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
26085 #define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
26086 #define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
26087 #define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
26088 #define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
26089 #define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
26090 #define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
26091 #define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
26092 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
26093 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
26094 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
26095 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
26096 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
26101 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
26106 #define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
26107 #define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
26108 #define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
26109 #define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
26110 #define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
26111 #define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
26112 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
26113 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
26114 #define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
26115 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
26116 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
26117 #define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
26118 #define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
26119 #define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
26120 #define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
26121 #define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
26122 #define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
26128 #define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
26129 #define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
26130 #define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
26131 #define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
26132 #define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
26133 #define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
26134 #define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
26135 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
26136 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
26137 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
26138 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
26139 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
26144 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
26149 #define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
26150 #define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
26151 #define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
26152 #define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
26153 #define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
26154 #define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
26155 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
26156 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
26157 #define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
26158 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
26159 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
26160 #define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
26161 #define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
26162 #define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
26163 #define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
26164 #define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
26165 #define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
26171 #define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
26172 #define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
26173 #define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
26174 #define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
26175 #define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
26176 #define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
26177 #define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
26178 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
26179 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
26180 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
26181 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
26182 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
26187 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
26192 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
26193 #define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
26194 #define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
26195 #define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
26196 #define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
26197 #define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
26198 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
26199 #define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
26200 #define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
26201 #define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
26202 #define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
26203 #define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
26204 #define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
26205 #define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
26210 #define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
26211 #define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
26212 #define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
26218 #define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
26219 #define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
26220 #define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
26221 #define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
26222 #define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
26223 #define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
26224 #define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
26229 #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
26230 #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
26231 #define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
26232 #define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
26233 #define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
26234 #define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
26235 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
26236 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
26237 #define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
26238 #define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
26239 #define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
26240 #define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
26241 #define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
26242 #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
26247 #define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
26248 #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
26249 #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
26255 #define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
26256 #define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
26257 #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
26258 #define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
26259 #define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
26260 #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
26261 #define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
26266 #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
26267 #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
26268 #define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
26269 #define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
26270 #define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
26271 #define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
26272 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
26273 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
26274 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
26275 #define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
26276 #define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
26277 #define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
26278 #define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
26279 #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
26284 #define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
26285 #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
26286 #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
26292 #define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
26293 #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
26294 #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
26295 #define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
26296 #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
26297 #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
26298 #define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
26303 #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
26304 #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
26305 #define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
26306 #define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
26307 #define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
26308 #define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
26309 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
26310 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
26311 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
26312 #define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
26313 #define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
26314 #define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
26315 #define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
26316 #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
26321 #define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
26322 #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
26323 #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
26329 #define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
26330 #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
26331 #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
26332 #define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
26333 #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
26334 #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
26335 #define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
26340 #define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
26341 #define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
26342 #define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
26343 #define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
26344 #define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
26345 #define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
26346 #define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
26347 #define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
26348 #define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
26349 #define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
26350 #define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
26351 #define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
26352 #define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
26353 #define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
26354 #define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
26355 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
26356 #define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
26362 #define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
26363 #define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
26364 #define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
26365 #define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
26366 #define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
26367 #define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
26368 #define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
26369 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
26370 #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
26371 #define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
26376 #define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
26377 #define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
26378 #define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
26379 #define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
26380 #define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
26381 #define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
26382 #define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
26383 #define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
26384 #define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
26385 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
26386 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
26387 #define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
26388 #define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
26389 #define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
26390 #define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
26391 #define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
26392 #define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
26398 #define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
26399 #define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
26400 #define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
26401 #define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
26402 #define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
26403 #define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
26404 #define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
26405 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
26406 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
26407 #define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
26412 #define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
26413 #define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
26414 #define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
26415 #define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
26416 #define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
26417 #define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
26418 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
26419 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
26420 #define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
26421 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
26422 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
26423 #define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
26424 #define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
26425 #define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
26426 #define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
26427 #define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
26428 #define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
26434 #define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
26435 #define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
26436 #define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
26437 #define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
26438 #define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
26439 #define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
26440 #define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
26441 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
26442 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
26443 #define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
26448 #define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
26449 #define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
26450 #define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
26451 #define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
26452 #define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
26453 #define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
26454 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
26455 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
26456 #define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
26457 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
26458 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
26459 #define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
26460 #define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
26461 #define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
26462 #define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
26463 #define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
26464 #define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
26470 #define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
26471 #define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
26472 #define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
26473 #define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
26474 #define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
26475 #define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
26476 #define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
26477 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
26478 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
26479 #define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
26484 #define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
26485 #define PMU_REG_CORE_REG0_TARG_SHIFT (0U)
26495 #define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
26496 #define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
26497 #define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
26518 #define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
26519 #define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
26520 #define PMU_REG_CORE_REG1_TARG_SHIFT (9U)
26532 #define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
26533 #define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
26534 #define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
26555 #define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
26556 #define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
26557 #define PMU_REG_CORE_REG2_TARG_SHIFT (18U)
26567 #define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
26568 #define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
26569 #define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
26590 #define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
26591 #define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
26592 #define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
26599 #define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
26600 #define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
26601 #define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
26602 #define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
26607 #define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
26608 #define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
26618 #define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
26619 #define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
26620 #define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
26641 #define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
26642 #define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
26643 #define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
26655 #define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
26656 #define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
26657 #define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
26678 #define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
26679 #define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
26680 #define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
26690 #define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
26691 #define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
26692 #define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
26713 #define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
26714 #define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
26715 #define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
26722 #define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
26723 #define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
26724 #define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
26725 #define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
26730 #define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
26731 #define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
26741 #define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
26742 #define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
26743 #define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
26764 #define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
26765 #define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
26766 #define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
26778 #define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
26779 #define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
26780 #define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
26801 #define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
26802 #define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
26803 #define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
26813 #define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
26814 #define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
26815 #define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
26836 #define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
26837 #define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
26838 #define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
26845 #define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
26846 #define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
26847 #define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
26848 #define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
26853 #define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
26854 #define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
26864 #define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
26865 #define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
26866 #define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
26887 #define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
26888 #define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
26889 #define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
26901 #define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
26902 #define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
26903 #define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
26924 #define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
26925 #define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
26926 #define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
26936 #define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
26937 #define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
26938 #define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
26959 #define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
26960 #define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
26961 #define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
26968 #define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
26969 #define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
26970 #define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
26971 #define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
26976 #define PMU_MISC0_REFTOP_PWD_MASK (0x1U)
26977 #define PMU_MISC0_REFTOP_PWD_SHIFT (0U)
26978 #define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
26979 #define PMU_MISC0_REFTOP_PWDVBGUP_MASK (0x2U)
26980 #define PMU_MISC0_REFTOP_PWDVBGUP_SHIFT (1U)
26981 #define PMU_MISC0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_REFTOP_PWDVBGUP_MASK)
26982 #define PMU_MISC0_REFTOP_LOWPOWER_MASK (0x4U)
26983 #define PMU_MISC0_REFTOP_LOWPOWER_SHIFT (2U)
26984 #define PMU_MISC0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_REFTOP_LOWPOWER_MASK)
26985 #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
26986 #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
26991 #define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
26992 #define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
26993 #define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
27004 #define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
27005 #define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
27006 #define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
27007 #define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
27008 #define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
27009 #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
27016 #define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
27017 #define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
27018 #define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
27023 #define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
27024 #define PMU_MISC0_OSC_I_MASK (0x6000U)
27025 #define PMU_MISC0_OSC_I_SHIFT (13U)
27032 #define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
27033 #define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
27034 #define PMU_MISC0_OSC_XTALOK_SHIFT (15U)
27035 #define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
27036 #define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
27037 #define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
27038 #define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
27039 #define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
27040 #define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
27045 #define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
27046 #define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
27047 #define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
27058 #define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
27059 #define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
27060 #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
27065 #define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
27066 #define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
27067 #define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
27068 #define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
27073 #define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
27074 #define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
27075 #define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
27076 #define PMU_MISC0_SET_REFTOP_PWDVBGUP_MASK (0x2U)
27077 #define PMU_MISC0_SET_REFTOP_PWDVBGUP_SHIFT (1U)
27078 #define PMU_MISC0_SET_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_PWDVBGUP_MASK)
27079 #define PMU_MISC0_SET_REFTOP_LOWPOWER_MASK (0x4U)
27080 #define PMU_MISC0_SET_REFTOP_LOWPOWER_SHIFT (2U)
27081 #define PMU_MISC0_SET_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_SET_REFTOP_LOWPOWER_MASK)
27082 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
27083 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
27088 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
27089 #define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
27090 #define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
27101 #define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
27102 #define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
27103 #define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
27104 #define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
27105 #define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
27106 #define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
27113 #define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
27114 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
27115 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
27120 #define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
27121 #define PMU_MISC0_SET_OSC_I_MASK (0x6000U)
27122 #define PMU_MISC0_SET_OSC_I_SHIFT (13U)
27129 #define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
27130 #define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
27131 #define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
27132 #define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
27133 #define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
27134 #define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
27135 #define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
27136 #define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
27137 #define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
27142 #define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
27143 #define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
27144 #define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
27155 #define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
27156 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
27157 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
27162 #define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
27163 #define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
27164 #define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
27165 #define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
27170 #define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
27171 #define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
27172 #define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
27173 #define PMU_MISC0_CLR_REFTOP_PWDVBGUP_MASK (0x2U)
27174 #define PMU_MISC0_CLR_REFTOP_PWDVBGUP_SHIFT (1U)
27175 #define PMU_MISC0_CLR_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWDVBGUP_MASK)
27176 #define PMU_MISC0_CLR_REFTOP_LOWPOWER_MASK (0x4U)
27177 #define PMU_MISC0_CLR_REFTOP_LOWPOWER_SHIFT (2U)
27178 #define PMU_MISC0_CLR_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_CLR_REFTOP_LOWPOWER_MASK)
27179 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
27180 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
27185 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
27186 #define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
27187 #define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
27198 #define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
27199 #define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
27200 #define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
27201 #define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
27202 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
27203 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
27210 #define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
27211 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
27212 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
27217 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
27218 #define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
27219 #define PMU_MISC0_CLR_OSC_I_SHIFT (13U)
27226 #define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
27227 #define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
27228 #define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
27229 #define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
27230 #define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
27231 #define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
27232 #define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
27233 #define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
27234 #define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
27239 #define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
27240 #define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
27241 #define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
27252 #define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
27253 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
27254 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
27259 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
27260 #define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
27261 #define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
27262 #define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
27267 #define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
27268 #define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
27269 #define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
27270 #define PMU_MISC0_TOG_REFTOP_PWDVBGUP_MASK (0x2U)
27271 #define PMU_MISC0_TOG_REFTOP_PWDVBGUP_SHIFT (1U)
27272 #define PMU_MISC0_TOG_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWDVBGUP_MASK)
27273 #define PMU_MISC0_TOG_REFTOP_LOWPOWER_MASK (0x4U)
27274 #define PMU_MISC0_TOG_REFTOP_LOWPOWER_SHIFT (2U)
27275 #define PMU_MISC0_TOG_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_TOG_REFTOP_LOWPOWER_MASK)
27276 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
27277 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
27282 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
27283 #define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
27284 #define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
27295 #define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
27296 #define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
27297 #define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
27298 #define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
27299 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
27300 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
27307 #define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
27308 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
27309 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
27314 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
27315 #define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
27316 #define PMU_MISC0_TOG_OSC_I_SHIFT (13U)
27323 #define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
27324 #define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
27325 #define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
27326 #define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
27327 #define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
27328 #define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
27329 #define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
27330 #define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
27331 #define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
27336 #define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
27337 #define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
27338 #define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
27349 #define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
27350 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
27351 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
27356 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
27357 #define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
27358 #define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
27359 #define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
27364 #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
27365 #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
27366 #define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
27367 #define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
27368 #define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
27369 #define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
27370 #define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
27371 #define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
27372 #define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
27373 #define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
27374 #define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
27375 #define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
27376 #define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
27377 #define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
27378 #define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
27379 #define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
27380 #define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
27381 #define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
27382 #define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
27383 #define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
27384 #define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
27389 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
27390 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
27391 #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
27392 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
27393 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
27394 #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
27395 #define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
27396 #define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
27397 #define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
27398 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
27399 #define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
27400 #define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
27401 #define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
27402 #define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
27403 #define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
27404 #define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
27405 #define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
27406 #define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
27407 #define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
27408 #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
27409 #define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
27414 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
27415 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
27416 #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
27417 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
27418 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
27419 #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
27420 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
27421 #define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
27422 #define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
27423 #define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
27424 #define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
27425 #define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
27426 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
27427 #define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
27428 #define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
27429 #define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
27430 #define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
27431 #define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
27432 #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
27433 #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
27434 #define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
27439 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
27440 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
27441 #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
27442 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
27443 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
27444 #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
27445 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
27446 #define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
27447 #define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
27448 #define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
27449 #define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
27450 #define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
27451 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
27452 #define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
27453 #define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
27454 #define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
27455 #define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
27456 #define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
27457 #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
27458 #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
27459 #define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
27464 #define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
27465 #define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
27470 #define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
27471 #define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
27472 #define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
27476 #define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
27477 #define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
27478 #define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
27479 #define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
27480 #define PMU_MISC2_PLL3_disable_MASK (0x80U)
27481 #define PMU_MISC2_PLL3_disable_SHIFT (7U)
27482 #define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
27483 #define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
27484 #define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
27489 #define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
27490 #define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
27491 #define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
27495 #define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
27496 #define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
27497 #define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
27498 #define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
27499 #define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
27500 #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
27505 #define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
27506 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
27507 #define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
27512 #define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
27513 #define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
27514 #define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
27515 #define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
27516 #define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
27517 #define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
27518 #define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
27519 #define PMU_MISC2_REG2_OK_MASK (0x400000U)
27520 #define PMU_MISC2_REG2_OK_SHIFT (22U)
27521 #define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
27522 #define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
27523 #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
27528 #define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
27529 #define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
27530 #define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
27537 #define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
27538 #define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
27539 #define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
27546 #define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
27547 #define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
27548 #define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
27555 #define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
27560 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
27561 #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
27566 #define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
27567 #define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
27568 #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
27572 #define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
27573 #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
27574 #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
27575 #define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
27576 #define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
27577 #define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
27578 #define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
27579 #define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
27580 #define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
27585 #define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
27586 #define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
27587 #define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
27591 #define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
27592 #define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
27593 #define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
27594 #define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
27595 #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
27596 #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
27601 #define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
27602 #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
27603 #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
27608 #define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
27609 #define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
27610 #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
27611 #define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
27612 #define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
27613 #define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
27614 #define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
27615 #define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
27616 #define PMU_MISC2_SET_REG2_OK_SHIFT (22U)
27617 #define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
27618 #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
27619 #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
27624 #define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
27625 #define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
27626 #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
27633 #define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
27634 #define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
27635 #define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
27642 #define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
27643 #define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
27644 #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
27651 #define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
27656 #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
27657 #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
27662 #define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
27663 #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
27664 #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
27668 #define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
27669 #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
27670 #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
27671 #define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
27672 #define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
27673 #define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
27674 #define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
27675 #define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
27676 #define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
27681 #define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
27682 #define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
27683 #define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
27687 #define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
27688 #define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
27689 #define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
27690 #define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
27691 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
27692 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
27697 #define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
27698 #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
27699 #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
27704 #define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
27705 #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
27706 #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
27707 #define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
27708 #define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
27709 #define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
27710 #define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
27711 #define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
27712 #define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
27713 #define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
27714 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
27715 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
27720 #define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
27721 #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
27722 #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
27729 #define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
27730 #define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
27731 #define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
27738 #define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
27739 #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
27740 #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
27747 #define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
27752 #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
27753 #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
27758 #define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
27759 #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
27760 #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
27764 #define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
27765 #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
27766 #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
27767 #define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
27768 #define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
27769 #define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
27770 #define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
27771 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
27772 #define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
27777 #define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
27778 #define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
27779 #define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
27783 #define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
27784 #define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
27785 #define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
27786 #define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
27787 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
27788 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
27793 #define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
27794 #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
27795 #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
27800 #define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
27801 #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
27802 #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
27803 #define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
27804 #define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
27805 #define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
27806 #define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
27807 #define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
27808 #define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
27809 #define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
27810 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
27811 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
27816 #define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
27817 #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
27818 #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
27825 #define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
27826 #define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
27827 #define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
27834 #define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
27835 #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
27836 #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
27843 #define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) /* end of group PMU_Register_Masks */
27850 
27851 
27852 /* PMU - Peripheral instance base addresses */
27854 #define PMU_BASE (0x400D8000u)
27856 #define PMU ((PMU_Type *)PMU_BASE)
27858 #define PMU_BASE_ADDRS { PMU_BASE }
27860 #define PMU_BASE_PTRS { PMU }
27861  /* end of group PMU_Peripheral_Access_Layer */
27865 
27866 
27867 /* ----------------------------------------------------------------------------
27868  -- PWM Peripheral Access Layer
27869  ---------------------------------------------------------------------------- */
27870 
27877 typedef struct {
27878  struct { /* offset: 0x0, array step: 0x60 */
27879  __I uint16_t CNT;
27880  __IO uint16_t INIT;
27881  __IO uint16_t CTRL2;
27882  __IO uint16_t CTRL;
27883  uint8_t RESERVED_0[2];
27884  __IO uint16_t VAL0;
27885  __IO uint16_t FRACVAL1;
27886  __IO uint16_t VAL1;
27887  __IO uint16_t FRACVAL2;
27888  __IO uint16_t VAL2;
27889  __IO uint16_t FRACVAL3;
27890  __IO uint16_t VAL3;
27891  __IO uint16_t FRACVAL4;
27892  __IO uint16_t VAL4;
27893  __IO uint16_t FRACVAL5;
27894  __IO uint16_t VAL5;
27895  __IO uint16_t FRCTRL;
27896  __IO uint16_t OCTRL;
27897  __IO uint16_t STS;
27898  __IO uint16_t INTEN;
27899  __IO uint16_t DMAEN;
27900  __IO uint16_t TCTRL;
27901  __IO uint16_t DISMAP[2];
27902  __IO uint16_t DTCNT0;
27903  __IO uint16_t DTCNT1;
27904  __IO uint16_t CAPTCTRLA;
27905  __IO uint16_t CAPTCOMPA;
27906  __IO uint16_t CAPTCTRLB;
27907  __IO uint16_t CAPTCOMPB;
27908  __IO uint16_t CAPTCTRLX;
27909  __IO uint16_t CAPTCOMPX;
27910  __I uint16_t CVAL0;
27911  __I uint16_t CVAL0CYC;
27912  __I uint16_t CVAL1;
27913  __I uint16_t CVAL1CYC;
27914  __I uint16_t CVAL2;
27915  __I uint16_t CVAL2CYC;
27916  __I uint16_t CVAL3;
27917  __I uint16_t CVAL3CYC;
27918  __I uint16_t CVAL4;
27919  __I uint16_t CVAL4CYC;
27920  __I uint16_t CVAL5;
27921  __I uint16_t CVAL5CYC;
27922  __IO uint16_t PHASEDLY;
27923  uint8_t RESERVED_1[6];
27924  } SM[4];
27925  __IO uint16_t OUTEN;
27926  __IO uint16_t MASK;
27927  __IO uint16_t SWCOUT;
27928  __IO uint16_t DTSRCSEL;
27929  __IO uint16_t MCTRL;
27930  __IO uint16_t MCTRL2;
27931  __IO uint16_t FCTRL;
27932  __IO uint16_t FSTS;
27933  __IO uint16_t FFILT;
27934  __IO uint16_t FTST;
27935  __IO uint16_t FCTRL2;
27936 } PWM_Type;
27937 
27938 /* ----------------------------------------------------------------------------
27939  -- PWM Register Masks
27940  ---------------------------------------------------------------------------- */
27941 
27949 #define PWM_CNT_CNT_MASK (0xFFFFU)
27950 #define PWM_CNT_CNT_SHIFT (0U)
27953 #define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
27956 /* The count of PWM_CNT */
27957 #define PWM_CNT_COUNT (4U)
27958 
27961 #define PWM_INIT_INIT_MASK (0xFFFFU)
27962 #define PWM_INIT_INIT_SHIFT (0U)
27965 #define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
27968 /* The count of PWM_INIT */
27969 #define PWM_INIT_COUNT (4U)
27970 
27973 #define PWM_CTRL2_CLK_SEL_MASK (0x3U)
27974 #define PWM_CTRL2_CLK_SEL_SHIFT (0U)
27982 #define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
27983 #define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
27984 #define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
27990 #define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
27991 #define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
27992 #define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
28006 #define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
28007 #define PWM_CTRL2_FORCE_MASK (0x40U)
28008 #define PWM_CTRL2_FORCE_SHIFT (6U)
28011 #define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
28012 #define PWM_CTRL2_FRCEN_MASK (0x80U)
28013 #define PWM_CTRL2_FRCEN_SHIFT (7U)
28018 #define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
28019 #define PWM_CTRL2_INIT_SEL_MASK (0x300U)
28020 #define PWM_CTRL2_INIT_SEL_SHIFT (8U)
28030 #define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
28031 #define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
28032 #define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
28035 #define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
28036 #define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
28037 #define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
28040 #define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
28041 #define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
28042 #define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
28045 #define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
28046 #define PWM_CTRL2_INDEP_MASK (0x2000U)
28047 #define PWM_CTRL2_INDEP_SHIFT (13U)
28052 #define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
28053 #define PWM_CTRL2_WAITEN_MASK (0x4000U)
28054 #define PWM_CTRL2_WAITEN_SHIFT (14U)
28057 #define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
28058 #define PWM_CTRL2_DBGEN_MASK (0x8000U)
28059 #define PWM_CTRL2_DBGEN_SHIFT (15U)
28062 #define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
28065 /* The count of PWM_CTRL2 */
28066 #define PWM_CTRL2_COUNT (4U)
28067 
28070 #define PWM_CTRL_DBLEN_MASK (0x1U)
28071 #define PWM_CTRL_DBLEN_SHIFT (0U)
28076 #define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
28077 #define PWM_CTRL_DBLX_MASK (0x2U)
28078 #define PWM_CTRL_DBLX_SHIFT (1U)
28083 #define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
28084 #define PWM_CTRL_LDMOD_MASK (0x4U)
28085 #define PWM_CTRL_LDMOD_SHIFT (2U)
28091 #define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
28092 #define PWM_CTRL_SPLIT_MASK (0x8U)
28093 #define PWM_CTRL_SPLIT_SHIFT (3U)
28098 #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
28099 #define PWM_CTRL_PRSC_MASK (0x70U)
28100 #define PWM_CTRL_PRSC_SHIFT (4U)
28111 #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
28112 #define PWM_CTRL_COMPMODE_MASK (0x80U)
28113 #define PWM_CTRL_COMPMODE_SHIFT (7U)
28124 #define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
28125 #define PWM_CTRL_DT_MASK (0x300U)
28126 #define PWM_CTRL_DT_SHIFT (8U)
28129 #define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
28130 #define PWM_CTRL_FULL_MASK (0x400U)
28131 #define PWM_CTRL_FULL_SHIFT (10U)
28136 #define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
28137 #define PWM_CTRL_HALF_MASK (0x800U)
28138 #define PWM_CTRL_HALF_SHIFT (11U)
28143 #define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
28144 #define PWM_CTRL_LDFQ_MASK (0xF000U)
28145 #define PWM_CTRL_LDFQ_SHIFT (12U)
28164 #define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
28167 /* The count of PWM_CTRL */
28168 #define PWM_CTRL_COUNT (4U)
28169 
28172 #define PWM_VAL0_VAL0_MASK (0xFFFFU)
28173 #define PWM_VAL0_VAL0_SHIFT (0U)
28176 #define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
28179 /* The count of PWM_VAL0 */
28180 #define PWM_VAL0_COUNT (4U)
28181 
28184 #define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
28185 #define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
28188 #define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
28191 /* The count of PWM_FRACVAL1 */
28192 #define PWM_FRACVAL1_COUNT (4U)
28193 
28196 #define PWM_VAL1_VAL1_MASK (0xFFFFU)
28197 #define PWM_VAL1_VAL1_SHIFT (0U)
28200 #define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
28203 /* The count of PWM_VAL1 */
28204 #define PWM_VAL1_COUNT (4U)
28205 
28208 #define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
28209 #define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
28212 #define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
28215 /* The count of PWM_FRACVAL2 */
28216 #define PWM_FRACVAL2_COUNT (4U)
28217 
28220 #define PWM_VAL2_VAL2_MASK (0xFFFFU)
28221 #define PWM_VAL2_VAL2_SHIFT (0U)
28224 #define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
28227 /* The count of PWM_VAL2 */
28228 #define PWM_VAL2_COUNT (4U)
28229 
28232 #define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
28233 #define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
28236 #define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
28239 /* The count of PWM_FRACVAL3 */
28240 #define PWM_FRACVAL3_COUNT (4U)
28241 
28244 #define PWM_VAL3_VAL3_MASK (0xFFFFU)
28245 #define PWM_VAL3_VAL3_SHIFT (0U)
28248 #define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
28251 /* The count of PWM_VAL3 */
28252 #define PWM_VAL3_COUNT (4U)
28253 
28256 #define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
28257 #define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
28260 #define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
28263 /* The count of PWM_FRACVAL4 */
28264 #define PWM_FRACVAL4_COUNT (4U)
28265 
28268 #define PWM_VAL4_VAL4_MASK (0xFFFFU)
28269 #define PWM_VAL4_VAL4_SHIFT (0U)
28272 #define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
28275 /* The count of PWM_VAL4 */
28276 #define PWM_VAL4_COUNT (4U)
28277 
28280 #define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
28281 #define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
28284 #define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
28287 /* The count of PWM_FRACVAL5 */
28288 #define PWM_FRACVAL5_COUNT (4U)
28289 
28292 #define PWM_VAL5_VAL5_MASK (0xFFFFU)
28293 #define PWM_VAL5_VAL5_SHIFT (0U)
28296 #define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
28299 /* The count of PWM_VAL5 */
28300 #define PWM_VAL5_COUNT (4U)
28301 
28304 #define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
28305 #define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
28310 #define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
28311 #define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
28312 #define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
28317 #define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
28318 #define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
28319 #define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
28324 #define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
28325 #define PWM_FRCTRL_FRAC_PU_MASK (0x100U)
28326 #define PWM_FRCTRL_FRAC_PU_SHIFT (8U)
28331 #define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
28332 #define PWM_FRCTRL_TEST_MASK (0x8000U)
28333 #define PWM_FRCTRL_TEST_SHIFT (15U)
28336 #define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
28339 /* The count of PWM_FRCTRL */
28340 #define PWM_FRCTRL_COUNT (4U)
28341 
28344 #define PWM_OCTRL_PWMXFS_MASK (0x3U)
28345 #define PWM_OCTRL_PWMXFS_SHIFT (0U)
28351 #define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
28352 #define PWM_OCTRL_PWMBFS_MASK (0xCU)
28353 #define PWM_OCTRL_PWMBFS_SHIFT (2U)
28359 #define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
28360 #define PWM_OCTRL_PWMAFS_MASK (0x30U)
28361 #define PWM_OCTRL_PWMAFS_SHIFT (4U)
28367 #define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
28368 #define PWM_OCTRL_POLX_MASK (0x100U)
28369 #define PWM_OCTRL_POLX_SHIFT (8U)
28374 #define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
28375 #define PWM_OCTRL_POLB_MASK (0x200U)
28376 #define PWM_OCTRL_POLB_SHIFT (9U)
28381 #define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
28382 #define PWM_OCTRL_POLA_MASK (0x400U)
28383 #define PWM_OCTRL_POLA_SHIFT (10U)
28388 #define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
28389 #define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
28390 #define PWM_OCTRL_PWMX_IN_SHIFT (13U)
28393 #define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
28394 #define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
28395 #define PWM_OCTRL_PWMB_IN_SHIFT (14U)
28398 #define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
28399 #define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
28400 #define PWM_OCTRL_PWMA_IN_SHIFT (15U)
28403 #define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
28406 /* The count of PWM_OCTRL */
28407 #define PWM_OCTRL_COUNT (4U)
28408 
28411 #define PWM_STS_CMPF_MASK (0x3FU)
28412 #define PWM_STS_CMPF_SHIFT (0U)
28417 #define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
28418 #define PWM_STS_CFX0_MASK (0x40U)
28419 #define PWM_STS_CFX0_SHIFT (6U)
28422 #define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
28423 #define PWM_STS_CFX1_MASK (0x80U)
28424 #define PWM_STS_CFX1_SHIFT (7U)
28427 #define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
28428 #define PWM_STS_CFB0_MASK (0x100U)
28429 #define PWM_STS_CFB0_SHIFT (8U)
28432 #define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
28433 #define PWM_STS_CFB1_MASK (0x200U)
28434 #define PWM_STS_CFB1_SHIFT (9U)
28437 #define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
28438 #define PWM_STS_CFA0_MASK (0x400U)
28439 #define PWM_STS_CFA0_SHIFT (10U)
28442 #define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
28443 #define PWM_STS_CFA1_MASK (0x800U)
28444 #define PWM_STS_CFA1_SHIFT (11U)
28447 #define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
28448 #define PWM_STS_RF_MASK (0x1000U)
28449 #define PWM_STS_RF_SHIFT (12U)
28454 #define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
28455 #define PWM_STS_REF_MASK (0x2000U)
28456 #define PWM_STS_REF_SHIFT (13U)
28461 #define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
28462 #define PWM_STS_RUF_MASK (0x4000U)
28463 #define PWM_STS_RUF_SHIFT (14U)
28468 #define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
28471 /* The count of PWM_STS */
28472 #define PWM_STS_COUNT (4U)
28473 
28476 #define PWM_INTEN_CMPIE_MASK (0x3FU)
28477 #define PWM_INTEN_CMPIE_SHIFT (0U)
28482 #define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
28483 #define PWM_INTEN_CX0IE_MASK (0x40U)
28484 #define PWM_INTEN_CX0IE_SHIFT (6U)
28489 #define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
28490 #define PWM_INTEN_CX1IE_MASK (0x80U)
28491 #define PWM_INTEN_CX1IE_SHIFT (7U)
28496 #define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
28497 #define PWM_INTEN_CB0IE_MASK (0x100U)
28498 #define PWM_INTEN_CB0IE_SHIFT (8U)
28503 #define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
28504 #define PWM_INTEN_CB1IE_MASK (0x200U)
28505 #define PWM_INTEN_CB1IE_SHIFT (9U)
28510 #define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
28511 #define PWM_INTEN_CA0IE_MASK (0x400U)
28512 #define PWM_INTEN_CA0IE_SHIFT (10U)
28517 #define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
28518 #define PWM_INTEN_CA1IE_MASK (0x800U)
28519 #define PWM_INTEN_CA1IE_SHIFT (11U)
28524 #define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
28525 #define PWM_INTEN_RIE_MASK (0x1000U)
28526 #define PWM_INTEN_RIE_SHIFT (12U)
28531 #define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
28532 #define PWM_INTEN_REIE_MASK (0x2000U)
28533 #define PWM_INTEN_REIE_SHIFT (13U)
28538 #define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
28541 /* The count of PWM_INTEN */
28542 #define PWM_INTEN_COUNT (4U)
28543 
28546 #define PWM_DMAEN_CX0DE_MASK (0x1U)
28547 #define PWM_DMAEN_CX0DE_SHIFT (0U)
28550 #define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
28551 #define PWM_DMAEN_CX1DE_MASK (0x2U)
28552 #define PWM_DMAEN_CX1DE_SHIFT (1U)
28555 #define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
28556 #define PWM_DMAEN_CB0DE_MASK (0x4U)
28557 #define PWM_DMAEN_CB0DE_SHIFT (2U)
28560 #define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
28561 #define PWM_DMAEN_CB1DE_MASK (0x8U)
28562 #define PWM_DMAEN_CB1DE_SHIFT (3U)
28565 #define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
28566 #define PWM_DMAEN_CA0DE_MASK (0x10U)
28567 #define PWM_DMAEN_CA0DE_SHIFT (4U)
28570 #define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
28571 #define PWM_DMAEN_CA1DE_MASK (0x20U)
28572 #define PWM_DMAEN_CA1DE_SHIFT (5U)
28575 #define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
28576 #define PWM_DMAEN_CAPTDE_MASK (0xC0U)
28577 #define PWM_DMAEN_CAPTDE_SHIFT (6U)
28586 #define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
28587 #define PWM_DMAEN_FAND_MASK (0x100U)
28588 #define PWM_DMAEN_FAND_SHIFT (8U)
28593 #define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
28594 #define PWM_DMAEN_VALDE_MASK (0x200U)
28595 #define PWM_DMAEN_VALDE_SHIFT (9U)
28600 #define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
28603 /* The count of PWM_DMAEN */
28604 #define PWM_DMAEN_COUNT (4U)
28605 
28608 #define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
28609 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
28618 #define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
28619 #define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
28620 #define PWM_TCTRL_TRGFRQ_SHIFT (12U)
28626 #define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
28627 #define PWM_TCTRL_PWBOT1_MASK (0x4000U)
28628 #define PWM_TCTRL_PWBOT1_SHIFT (14U)
28633 #define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
28634 #define PWM_TCTRL_PWAOT0_MASK (0x8000U)
28635 #define PWM_TCTRL_PWAOT0_SHIFT (15U)
28640 #define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
28643 /* The count of PWM_TCTRL */
28644 #define PWM_TCTRL_COUNT (4U)
28645 
28648 #define PWM_DISMAP_DIS0A_MASK (0xFU)
28649 #define PWM_DISMAP_DIS0A_SHIFT (0U)
28652 #define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
28653 #define PWM_DISMAP_DIS1A_MASK (0xFU)
28654 #define PWM_DISMAP_DIS1A_SHIFT (0U)
28657 #define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
28658 #define PWM_DISMAP_DIS0B_MASK (0xF0U)
28659 #define PWM_DISMAP_DIS0B_SHIFT (4U)
28662 #define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
28663 #define PWM_DISMAP_DIS1B_MASK (0xF0U)
28664 #define PWM_DISMAP_DIS1B_SHIFT (4U)
28667 #define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
28668 #define PWM_DISMAP_DIS0X_MASK (0xF00U)
28669 #define PWM_DISMAP_DIS0X_SHIFT (8U)
28672 #define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
28673 #define PWM_DISMAP_DIS1X_MASK (0xF00U)
28674 #define PWM_DISMAP_DIS1X_SHIFT (8U)
28677 #define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
28680 /* The count of PWM_DISMAP */
28681 #define PWM_DISMAP_COUNT (4U)
28682 
28683 /* The count of PWM_DISMAP */
28684 #define PWM_DISMAP_COUNT2 (2U)
28685 
28688 #define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
28689 #define PWM_DTCNT0_DTCNT0_SHIFT (0U)
28692 #define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
28695 /* The count of PWM_DTCNT0 */
28696 #define PWM_DTCNT0_COUNT (4U)
28697 
28700 #define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
28701 #define PWM_DTCNT1_DTCNT1_SHIFT (0U)
28704 #define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
28707 /* The count of PWM_DTCNT1 */
28708 #define PWM_DTCNT1_COUNT (4U)
28709 
28712 #define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
28713 #define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
28718 #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
28719 #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
28720 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
28725 #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
28726 #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
28727 #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
28734 #define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
28735 #define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
28736 #define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
28743 #define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
28744 #define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
28745 #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
28750 #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
28751 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
28752 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
28757 #define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
28758 #define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
28759 #define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
28762 #define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
28763 #define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
28764 #define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
28767 #define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
28768 #define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
28769 #define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
28772 #define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
28775 /* The count of PWM_CAPTCTRLA */
28776 #define PWM_CAPTCTRLA_COUNT (4U)
28777 
28780 #define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
28781 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
28784 #define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
28785 #define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
28786 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
28789 #define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
28792 /* The count of PWM_CAPTCOMPA */
28793 #define PWM_CAPTCOMPA_COUNT (4U)
28794 
28797 #define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
28798 #define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
28803 #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
28804 #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
28805 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
28810 #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
28811 #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
28812 #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
28819 #define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
28820 #define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
28821 #define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
28828 #define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
28829 #define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
28830 #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
28835 #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
28836 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
28837 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
28842 #define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
28843 #define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
28844 #define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
28847 #define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
28848 #define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
28849 #define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
28852 #define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
28853 #define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
28854 #define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
28857 #define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
28860 /* The count of PWM_CAPTCTRLB */
28861 #define PWM_CAPTCTRLB_COUNT (4U)
28862 
28865 #define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
28866 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
28869 #define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
28870 #define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
28871 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
28874 #define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
28877 /* The count of PWM_CAPTCOMPB */
28878 #define PWM_CAPTCOMPB_COUNT (4U)
28879 
28882 #define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
28883 #define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
28888 #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
28889 #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
28890 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
28895 #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
28896 #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
28897 #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
28904 #define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
28905 #define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
28906 #define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
28913 #define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
28914 #define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
28915 #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
28920 #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
28921 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
28922 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
28927 #define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
28928 #define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
28929 #define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
28932 #define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
28933 #define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
28934 #define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
28937 #define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
28938 #define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
28939 #define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
28942 #define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
28945 /* The count of PWM_CAPTCTRLX */
28946 #define PWM_CAPTCTRLX_COUNT (4U)
28947 
28950 #define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
28951 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
28954 #define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
28955 #define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
28956 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
28959 #define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
28962 /* The count of PWM_CAPTCOMPX */
28963 #define PWM_CAPTCOMPX_COUNT (4U)
28964 
28967 #define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
28968 #define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
28971 #define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
28974 /* The count of PWM_CVAL0 */
28975 #define PWM_CVAL0_COUNT (4U)
28976 
28979 #define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
28980 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
28983 #define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
28986 /* The count of PWM_CVAL0CYC */
28987 #define PWM_CVAL0CYC_COUNT (4U)
28988 
28991 #define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
28992 #define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
28995 #define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
28998 /* The count of PWM_CVAL1 */
28999 #define PWM_CVAL1_COUNT (4U)
29000 
29003 #define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
29004 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
29007 #define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
29010 /* The count of PWM_CVAL1CYC */
29011 #define PWM_CVAL1CYC_COUNT (4U)
29012 
29015 #define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
29016 #define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
29019 #define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
29022 /* The count of PWM_CVAL2 */
29023 #define PWM_CVAL2_COUNT (4U)
29024 
29027 #define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
29028 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
29031 #define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
29034 /* The count of PWM_CVAL2CYC */
29035 #define PWM_CVAL2CYC_COUNT (4U)
29036 
29039 #define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
29040 #define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
29043 #define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
29046 /* The count of PWM_CVAL3 */
29047 #define PWM_CVAL3_COUNT (4U)
29048 
29051 #define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
29052 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
29055 #define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
29058 /* The count of PWM_CVAL3CYC */
29059 #define PWM_CVAL3CYC_COUNT (4U)
29060 
29063 #define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
29064 #define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
29067 #define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
29070 /* The count of PWM_CVAL4 */
29071 #define PWM_CVAL4_COUNT (4U)
29072 
29075 #define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
29076 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
29079 #define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
29082 /* The count of PWM_CVAL4CYC */
29083 #define PWM_CVAL4CYC_COUNT (4U)
29084 
29087 #define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
29088 #define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
29091 #define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
29094 /* The count of PWM_CVAL5 */
29095 #define PWM_CVAL5_COUNT (4U)
29096 
29099 #define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
29100 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
29103 #define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
29106 /* The count of PWM_CVAL5CYC */
29107 #define PWM_CVAL5CYC_COUNT (4U)
29108 
29111 #define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU)
29112 #define PWM_PHASEDLY_PHASEDLY_SHIFT (0U)
29115 #define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK)
29118 /* The count of PWM_PHASEDLY */
29119 #define PWM_PHASEDLY_COUNT (4U)
29120 
29123 #define PWM_OUTEN_PWMX_EN_MASK (0xFU)
29124 #define PWM_OUTEN_PWMX_EN_SHIFT (0U)
29129 #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
29130 #define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
29131 #define PWM_OUTEN_PWMB_EN_SHIFT (4U)
29136 #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
29137 #define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
29138 #define PWM_OUTEN_PWMA_EN_SHIFT (8U)
29143 #define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
29148 #define PWM_MASK_MASKX_MASK (0xFU)
29149 #define PWM_MASK_MASKX_SHIFT (0U)
29154 #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
29155 #define PWM_MASK_MASKB_MASK (0xF0U)
29156 #define PWM_MASK_MASKB_SHIFT (4U)
29161 #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
29162 #define PWM_MASK_MASKA_MASK (0xF00U)
29163 #define PWM_MASK_MASKA_SHIFT (8U)
29168 #define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
29169 #define PWM_MASK_UPDATE_MASK_MASK (0xF000U)
29170 #define PWM_MASK_UPDATE_MASK_SHIFT (12U)
29175 #define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
29180 #define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
29181 #define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
29186 #define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
29187 #define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
29188 #define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
29193 #define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
29194 #define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
29195 #define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
29200 #define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
29201 #define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
29202 #define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
29207 #define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
29208 #define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
29209 #define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
29214 #define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
29215 #define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
29216 #define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
29221 #define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
29222 #define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
29223 #define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
29228 #define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
29229 #define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
29230 #define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
29235 #define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
29240 #define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
29241 #define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
29248 #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
29249 #define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
29250 #define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
29257 #define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
29258 #define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
29259 #define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
29266 #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
29267 #define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
29268 #define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
29275 #define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
29276 #define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
29277 #define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
29284 #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
29285 #define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
29286 #define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
29293 #define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
29294 #define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
29295 #define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
29302 #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
29303 #define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
29304 #define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
29311 #define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
29316 #define PWM_MCTRL_LDOK_MASK (0xFU)
29317 #define PWM_MCTRL_LDOK_SHIFT (0U)
29322 #define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
29323 #define PWM_MCTRL_CLDOK_MASK (0xF0U)
29324 #define PWM_MCTRL_CLDOK_SHIFT (4U)
29327 #define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
29328 #define PWM_MCTRL_RUN_MASK (0xF00U)
29329 #define PWM_MCTRL_RUN_SHIFT (8U)
29334 #define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
29335 #define PWM_MCTRL_IPOL_MASK (0xF000U)
29336 #define PWM_MCTRL_IPOL_SHIFT (12U)
29341 #define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
29346 #define PWM_MCTRL2_MONPLL_MASK (0x3U)
29347 #define PWM_MCTRL2_MONPLL_SHIFT (0U)
29356 #define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
29361 #define PWM_FCTRL_FIE_MASK (0xFU)
29362 #define PWM_FCTRL_FIE_SHIFT (0U)
29367 #define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
29368 #define PWM_FCTRL_FSAFE_MASK (0xF0U)
29369 #define PWM_FCTRL_FSAFE_SHIFT (4U)
29381 #define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
29382 #define PWM_FCTRL_FAUTO_MASK (0xF00U)
29383 #define PWM_FCTRL_FAUTO_SHIFT (8U)
29394 #define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
29395 #define PWM_FCTRL_FLVL_MASK (0xF000U)
29396 #define PWM_FCTRL_FLVL_SHIFT (12U)
29401 #define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
29406 #define PWM_FSTS_FFLAG_MASK (0xFU)
29407 #define PWM_FSTS_FFLAG_SHIFT (0U)
29412 #define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
29413 #define PWM_FSTS_FFULL_MASK (0xF0U)
29414 #define PWM_FSTS_FFULL_SHIFT (4U)
29419 #define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
29420 #define PWM_FSTS_FFPIN_MASK (0xF00U)
29421 #define PWM_FSTS_FFPIN_SHIFT (8U)
29424 #define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
29425 #define PWM_FSTS_FHALF_MASK (0xF000U)
29426 #define PWM_FSTS_FHALF_SHIFT (12U)
29431 #define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
29436 #define PWM_FFILT_FILT_PER_MASK (0xFFU)
29437 #define PWM_FFILT_FILT_PER_SHIFT (0U)
29440 #define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
29441 #define PWM_FFILT_FILT_CNT_MASK (0x700U)
29442 #define PWM_FFILT_FILT_CNT_SHIFT (8U)
29445 #define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
29446 #define PWM_FFILT_GSTR_MASK (0x8000U)
29447 #define PWM_FFILT_GSTR_SHIFT (15U)
29452 #define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
29457 #define PWM_FTST_FTEST_MASK (0x1U)
29458 #define PWM_FTST_FTEST_SHIFT (0U)
29463 #define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
29468 #define PWM_FCTRL2_NOCOMB_MASK (0xFU)
29469 #define PWM_FCTRL2_NOCOMB_SHIFT (0U)
29476 #define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) /* end of group PWM_Register_Masks */
29483 
29484 
29485 /* PWM - Peripheral instance base addresses */
29487 #define PWM1_BASE (0x403DC000u)
29489 #define PWM1 ((PWM_Type *)PWM1_BASE)
29491 #define PWM2_BASE (0x403E0000u)
29493 #define PWM2 ((PWM_Type *)PWM2_BASE)
29495 #define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE }
29497 #define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2 }
29499 #define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }
29500 #define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }
29501 #define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn } }
29502 #define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn }
29503 #define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn }
29504  /* end of group PWM_Peripheral_Access_Layer */
29508 
29509 
29510 /* ----------------------------------------------------------------------------
29511  -- RTWDOG Peripheral Access Layer
29512  ---------------------------------------------------------------------------- */
29513 
29520 typedef struct {
29521  __IO uint32_t CS;
29522  __IO uint32_t CNT;
29523  __IO uint32_t TOVAL;
29524  __IO uint32_t WIN;
29525 } RTWDOG_Type;
29526 
29527 /* ----------------------------------------------------------------------------
29528  -- RTWDOG Register Masks
29529  ---------------------------------------------------------------------------- */
29530 
29538 #define RTWDOG_CS_STOP_MASK (0x1U)
29539 #define RTWDOG_CS_STOP_SHIFT (0U)
29544 #define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
29545 #define RTWDOG_CS_WAIT_MASK (0x2U)
29546 #define RTWDOG_CS_WAIT_SHIFT (1U)
29551 #define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
29552 #define RTWDOG_CS_DBG_MASK (0x4U)
29553 #define RTWDOG_CS_DBG_SHIFT (2U)
29558 #define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
29559 #define RTWDOG_CS_TST_MASK (0x18U)
29560 #define RTWDOG_CS_TST_SHIFT (3U)
29568 #define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
29569 #define RTWDOG_CS_UPDATE_MASK (0x20U)
29570 #define RTWDOG_CS_UPDATE_SHIFT (5U)
29575 #define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
29576 #define RTWDOG_CS_INT_MASK (0x40U)
29577 #define RTWDOG_CS_INT_SHIFT (6U)
29582 #define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
29583 #define RTWDOG_CS_EN_MASK (0x80U)
29584 #define RTWDOG_CS_EN_SHIFT (7U)
29589 #define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
29590 #define RTWDOG_CS_CLK_MASK (0x300U)
29591 #define RTWDOG_CS_CLK_SHIFT (8U)
29594 #define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
29595 #define RTWDOG_CS_RCS_MASK (0x400U)
29596 #define RTWDOG_CS_RCS_SHIFT (10U)
29601 #define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
29602 #define RTWDOG_CS_ULK_MASK (0x800U)
29603 #define RTWDOG_CS_ULK_SHIFT (11U)
29608 #define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
29609 #define RTWDOG_CS_PRES_MASK (0x1000U)
29610 #define RTWDOG_CS_PRES_SHIFT (12U)
29615 #define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
29616 #define RTWDOG_CS_CMD32EN_MASK (0x2000U)
29617 #define RTWDOG_CS_CMD32EN_SHIFT (13U)
29622 #define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
29623 #define RTWDOG_CS_FLG_MASK (0x4000U)
29624 #define RTWDOG_CS_FLG_SHIFT (14U)
29629 #define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
29630 #define RTWDOG_CS_WIN_MASK (0x8000U)
29631 #define RTWDOG_CS_WIN_SHIFT (15U)
29636 #define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
29641 #define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
29642 #define RTWDOG_CNT_CNTLOW_SHIFT (0U)
29645 #define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
29646 #define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
29647 #define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
29650 #define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
29655 #define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
29656 #define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
29659 #define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
29660 #define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
29661 #define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
29664 #define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
29669 #define RTWDOG_WIN_WINLOW_MASK (0xFFU)
29670 #define RTWDOG_WIN_WINLOW_SHIFT (0U)
29673 #define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
29674 #define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
29675 #define RTWDOG_WIN_WINHIGH_SHIFT (8U)
29678 #define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) /* end of group RTWDOG_Register_Masks */
29685 
29686 
29687 /* RTWDOG - Peripheral instance base addresses */
29689 #define RTWDOG_BASE (0x400BC000u)
29691 #define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)
29693 #define RTWDOG_BASE_ADDRS { RTWDOG_BASE }
29695 #define RTWDOG_BASE_PTRS { RTWDOG }
29697 #define RTWDOG_IRQS { RTWDOG_IRQn }
29698 /* Extra definition */
29699 #define RTWDOG_UPDATE_KEY (0xD928C520U)
29700 #define RTWDOG_REFRESH_KEY (0xB480A602U)
29701 
29702  /* end of group RTWDOG_Peripheral_Access_Layer */
29706 
29707 
29708 /* ----------------------------------------------------------------------------
29709  -- SEMC Peripheral Access Layer
29710  ---------------------------------------------------------------------------- */
29711 
29718 typedef struct {
29719  __IO uint32_t MCR;
29720  __IO uint32_t IOCR;
29721  __IO uint32_t BMCR0;
29722  __IO uint32_t BMCR1;
29723  __IO uint32_t BR[9];
29724  uint8_t RESERVED_0[4];
29725  __IO uint32_t INTEN;
29726  __IO uint32_t INTR;
29727  __IO uint32_t SDRAMCR0;
29728  __IO uint32_t SDRAMCR1;
29729  __IO uint32_t SDRAMCR2;
29730  __IO uint32_t SDRAMCR3;
29731  __IO uint32_t NANDCR0;
29732  __IO uint32_t NANDCR1;
29733  __IO uint32_t NANDCR2;
29734  __IO uint32_t NANDCR3;
29735  __IO uint32_t NORCR0;
29736  __IO uint32_t NORCR1;
29737  __IO uint32_t NORCR2;
29738  uint32_t NORCR3;
29739  __IO uint32_t SRAMCR0;
29740  __IO uint32_t SRAMCR1;
29741  __IO uint32_t SRAMCR2;
29742  uint32_t SRAMCR3;
29743  __IO uint32_t DBICR0;
29744  __IO uint32_t DBICR1;
29745  uint8_t RESERVED_1[8];
29746  __IO uint32_t IPCR0;
29747  __IO uint32_t IPCR1;
29748  __IO uint32_t IPCR2;
29749  __IO uint32_t IPCMD;
29750  __IO uint32_t IPTXDAT;
29751  uint8_t RESERVED_2[12];
29752  __I uint32_t IPRXDAT;
29753  uint8_t RESERVED_3[12];
29754  __I uint32_t STS0;
29755  uint32_t STS1;
29756  __I uint32_t STS2;
29757  uint32_t STS3;
29758  uint32_t STS4;
29759  uint32_t STS5;
29760  uint32_t STS6;
29761  uint32_t STS7;
29762  uint32_t STS8;
29763  uint32_t STS9;
29764  uint32_t STS10;
29765  uint32_t STS11;
29766  __I uint32_t STS12;
29767  uint32_t STS13;
29768  uint32_t STS14;
29769  uint32_t STS15;
29770 } SEMC_Type;
29771 
29772 /* ----------------------------------------------------------------------------
29773  -- SEMC Register Masks
29774  ---------------------------------------------------------------------------- */
29775 
29783 #define SEMC_MCR_SWRST_MASK (0x1U)
29784 #define SEMC_MCR_SWRST_SHIFT (0U)
29787 #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
29788 #define SEMC_MCR_MDIS_MASK (0x2U)
29789 #define SEMC_MCR_MDIS_SHIFT (1U)
29794 #define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
29795 #define SEMC_MCR_DQSMD_MASK (0x4U)
29796 #define SEMC_MCR_DQSMD_SHIFT (2U)
29801 #define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
29802 #define SEMC_MCR_WPOL0_MASK (0x40U)
29803 #define SEMC_MCR_WPOL0_SHIFT (6U)
29808 #define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
29809 #define SEMC_MCR_WPOL1_MASK (0x80U)
29810 #define SEMC_MCR_WPOL1_SHIFT (7U)
29815 #define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
29816 #define SEMC_MCR_CTO_MASK (0xFF0000U)
29817 #define SEMC_MCR_CTO_SHIFT (16U)
29820 #define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
29821 #define SEMC_MCR_BTO_MASK (0x1F000000U)
29822 #define SEMC_MCR_BTO_SHIFT (24U)
29828 #define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
29833 #define SEMC_IOCR_MUX_A8_MASK (0x7U)
29834 #define SEMC_IOCR_MUX_A8_SHIFT (0U)
29845 #define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
29846 #define SEMC_IOCR_MUX_CSX0_MASK (0x38U)
29847 #define SEMC_IOCR_MUX_CSX0_SHIFT (3U)
29858 #define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
29859 #define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
29860 #define SEMC_IOCR_MUX_CSX1_SHIFT (6U)
29871 #define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
29872 #define SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
29873 #define SEMC_IOCR_MUX_CSX2_SHIFT (9U)
29884 #define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
29885 #define SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
29886 #define SEMC_IOCR_MUX_CSX3_SHIFT (12U)
29897 #define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
29898 #define SEMC_IOCR_MUX_RDY_MASK (0x38000U)
29899 #define SEMC_IOCR_MUX_RDY_SHIFT (15U)
29910 #define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
29915 #define SEMC_BMCR0_WQOS_MASK (0xFU)
29916 #define SEMC_BMCR0_WQOS_SHIFT (0U)
29921 #define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
29922 #define SEMC_BMCR0_WAGE_MASK (0xF0U)
29923 #define SEMC_BMCR0_WAGE_SHIFT (4U)
29927 #define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
29928 #define SEMC_BMCR0_WSH_MASK (0xFF00U)
29929 #define SEMC_BMCR0_WSH_SHIFT (8U)
29933 #define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
29934 #define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
29935 #define SEMC_BMCR0_WRWS_SHIFT (16U)
29939 #define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
29944 #define SEMC_BMCR1_WQOS_MASK (0xFU)
29945 #define SEMC_BMCR1_WQOS_SHIFT (0U)
29950 #define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
29951 #define SEMC_BMCR1_WAGE_MASK (0xF0U)
29952 #define SEMC_BMCR1_WAGE_SHIFT (4U)
29956 #define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
29957 #define SEMC_BMCR1_WPH_MASK (0xFF00U)
29958 #define SEMC_BMCR1_WPH_SHIFT (8U)
29961 #define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
29962 #define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
29963 #define SEMC_BMCR1_WRWS_SHIFT (16U)
29967 #define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
29968 #define SEMC_BMCR1_WBR_MASK (0xFF000000U)
29969 #define SEMC_BMCR1_WBR_SHIFT (24U)
29972 #define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
29977 #define SEMC_BR_VLD_MASK (0x1U)
29978 #define SEMC_BR_VLD_SHIFT (0U)
29981 #define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
29982 #define SEMC_BR_MS_MASK (0x3EU)
29983 #define SEMC_BR_MS_SHIFT (1U)
30007 #define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
30008 #define SEMC_BR_BA_MASK (0xFFFFF000U)
30009 #define SEMC_BR_BA_SHIFT (12U)
30012 #define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
30015 /* The count of SEMC_BR */
30016 #define SEMC_BR_COUNT (9U)
30017 
30020 #define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
30021 #define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
30026 #define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
30027 #define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
30028 #define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
30033 #define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
30034 #define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
30035 #define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
30040 #define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
30041 #define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
30042 #define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
30047 #define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
30048 #define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
30049 #define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
30054 #define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
30055 #define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
30056 #define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
30061 #define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
30066 #define SEMC_INTR_IPCMDDONE_MASK (0x1U)
30067 #define SEMC_INTR_IPCMDDONE_SHIFT (0U)
30070 #define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
30071 #define SEMC_INTR_IPCMDERR_MASK (0x2U)
30072 #define SEMC_INTR_IPCMDERR_SHIFT (1U)
30075 #define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
30076 #define SEMC_INTR_AXICMDERR_MASK (0x4U)
30077 #define SEMC_INTR_AXICMDERR_SHIFT (2U)
30080 #define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
30081 #define SEMC_INTR_AXIBUSERR_MASK (0x8U)
30082 #define SEMC_INTR_AXIBUSERR_SHIFT (3U)
30085 #define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
30086 #define SEMC_INTR_NDPAGEEND_MASK (0x10U)
30087 #define SEMC_INTR_NDPAGEEND_SHIFT (4U)
30090 #define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
30091 #define SEMC_INTR_NDNOPEND_MASK (0x20U)
30092 #define SEMC_INTR_NDNOPEND_SHIFT (5U)
30095 #define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
30100 #define SEMC_SDRAMCR0_PS_MASK (0x1U)
30101 #define SEMC_SDRAMCR0_PS_SHIFT (0U)
30106 #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
30107 #define SEMC_SDRAMCR0_BL_MASK (0x70U)
30108 #define SEMC_SDRAMCR0_BL_SHIFT (4U)
30119 #define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
30120 #define SEMC_SDRAMCR0_COL_MASK (0x300U)
30121 #define SEMC_SDRAMCR0_COL_SHIFT (8U)
30128 #define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
30129 #define SEMC_SDRAMCR0_CL_MASK (0xC00U)
30130 #define SEMC_SDRAMCR0_CL_SHIFT (10U)
30137 #define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
30142 #define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
30143 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
30146 #define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
30147 #define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
30148 #define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
30151 #define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
30152 #define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
30153 #define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
30156 #define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
30157 #define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
30158 #define SEMC_SDRAMCR1_WRC_SHIFT (13U)
30161 #define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
30162 #define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
30163 #define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
30166 #define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
30167 #define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
30168 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
30171 #define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
30176 #define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
30177 #define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
30180 #define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
30181 #define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
30182 #define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
30185 #define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
30186 #define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
30187 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
30190 #define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
30191 #define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
30192 #define SEMC_SDRAMCR2_ITO_SHIFT (24U)
30197 #define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
30202 #define SEMC_SDRAMCR3_REN_MASK (0x1U)
30203 #define SEMC_SDRAMCR3_REN_SHIFT (0U)
30206 #define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
30207 #define SEMC_SDRAMCR3_REBL_MASK (0xEU)
30208 #define SEMC_SDRAMCR3_REBL_SHIFT (1U)
30219 #define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
30220 #define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
30221 #define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
30226 #define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
30227 #define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
30228 #define SEMC_SDRAMCR3_RT_SHIFT (16U)
30233 #define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
30234 #define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
30235 #define SEMC_SDRAMCR3_UT_SHIFT (24U)
30240 #define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
30245 #define SEMC_NANDCR0_PS_MASK (0x1U)
30246 #define SEMC_NANDCR0_PS_SHIFT (0U)
30251 #define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
30252 #define SEMC_NANDCR0_BL_MASK (0x70U)
30253 #define SEMC_NANDCR0_BL_SHIFT (4U)
30264 #define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
30265 #define SEMC_NANDCR0_EDO_MASK (0x80U)
30266 #define SEMC_NANDCR0_EDO_SHIFT (7U)
30271 #define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
30272 #define SEMC_NANDCR0_COL_MASK (0x700U)
30273 #define SEMC_NANDCR0_COL_SHIFT (8U)
30284 #define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
30289 #define SEMC_NANDCR1_CES_MASK (0xFU)
30290 #define SEMC_NANDCR1_CES_SHIFT (0U)
30293 #define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
30294 #define SEMC_NANDCR1_CEH_MASK (0xF0U)
30295 #define SEMC_NANDCR1_CEH_SHIFT (4U)
30298 #define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
30299 #define SEMC_NANDCR1_WEL_MASK (0xF00U)
30300 #define SEMC_NANDCR1_WEL_SHIFT (8U)
30303 #define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
30304 #define SEMC_NANDCR1_WEH_MASK (0xF000U)
30305 #define SEMC_NANDCR1_WEH_SHIFT (12U)
30308 #define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
30309 #define SEMC_NANDCR1_REL_MASK (0xF0000U)
30310 #define SEMC_NANDCR1_REL_SHIFT (16U)
30313 #define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
30314 #define SEMC_NANDCR1_REH_MASK (0xF00000U)
30315 #define SEMC_NANDCR1_REH_SHIFT (20U)
30318 #define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
30319 #define SEMC_NANDCR1_TA_MASK (0xF000000U)
30320 #define SEMC_NANDCR1_TA_SHIFT (24U)
30323 #define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
30324 #define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
30325 #define SEMC_NANDCR1_CEITV_SHIFT (28U)
30328 #define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
30333 #define SEMC_NANDCR2_TWHR_MASK (0x3FU)
30334 #define SEMC_NANDCR2_TWHR_SHIFT (0U)
30337 #define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
30338 #define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
30339 #define SEMC_NANDCR2_TRHW_SHIFT (6U)
30342 #define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
30343 #define SEMC_NANDCR2_TADL_MASK (0x3F000U)
30344 #define SEMC_NANDCR2_TADL_SHIFT (12U)
30347 #define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
30348 #define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
30349 #define SEMC_NANDCR2_TRR_SHIFT (18U)
30352 #define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
30353 #define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
30354 #define SEMC_NANDCR2_TWB_SHIFT (24U)
30357 #define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
30362 #define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
30363 #define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
30366 #define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
30367 #define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
30368 #define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
30371 #define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
30372 #define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
30373 #define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
30376 #define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
30381 #define SEMC_NORCR0_PS_MASK (0x1U)
30382 #define SEMC_NORCR0_PS_SHIFT (0U)
30387 #define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
30388 #define SEMC_NORCR0_BL_MASK (0x70U)
30389 #define SEMC_NORCR0_BL_SHIFT (4U)
30400 #define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
30401 #define SEMC_NORCR0_AM_MASK (0x300U)
30402 #define SEMC_NORCR0_AM_SHIFT (8U)
30409 #define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
30410 #define SEMC_NORCR0_ADVP_MASK (0x400U)
30411 #define SEMC_NORCR0_ADVP_SHIFT (10U)
30416 #define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
30417 #define SEMC_NORCR0_COL_MASK (0xF000U)
30418 #define SEMC_NORCR0_COL_SHIFT (12U)
30437 #define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
30442 #define SEMC_NORCR1_CES_MASK (0xFU)
30443 #define SEMC_NORCR1_CES_SHIFT (0U)
30446 #define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
30447 #define SEMC_NORCR1_CEH_MASK (0xF0U)
30448 #define SEMC_NORCR1_CEH_SHIFT (4U)
30451 #define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
30452 #define SEMC_NORCR1_AS_MASK (0xF00U)
30453 #define SEMC_NORCR1_AS_SHIFT (8U)
30456 #define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
30457 #define SEMC_NORCR1_AH_MASK (0xF000U)
30458 #define SEMC_NORCR1_AH_SHIFT (12U)
30461 #define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
30462 #define SEMC_NORCR1_WEL_MASK (0xF0000U)
30463 #define SEMC_NORCR1_WEL_SHIFT (16U)
30466 #define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
30467 #define SEMC_NORCR1_WEH_MASK (0xF00000U)
30468 #define SEMC_NORCR1_WEH_SHIFT (20U)
30471 #define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
30472 #define SEMC_NORCR1_REL_MASK (0xF000000U)
30473 #define SEMC_NORCR1_REL_SHIFT (24U)
30476 #define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
30477 #define SEMC_NORCR1_REH_MASK (0xF0000000U)
30478 #define SEMC_NORCR1_REH_SHIFT (28U)
30481 #define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
30486 #define SEMC_NORCR2_WDS_MASK (0xFU)
30487 #define SEMC_NORCR2_WDS_SHIFT (0U)
30490 #define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)
30491 #define SEMC_NORCR2_WDH_MASK (0xF0U)
30492 #define SEMC_NORCR2_WDH_SHIFT (4U)
30495 #define SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)
30496 #define SEMC_NORCR2_TA_MASK (0xF00U)
30497 #define SEMC_NORCR2_TA_SHIFT (8U)
30500 #define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
30501 #define SEMC_NORCR2_AWDH_MASK (0xF000U)
30502 #define SEMC_NORCR2_AWDH_SHIFT (12U)
30505 #define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
30506 #define SEMC_NORCR2_LC_MASK (0xF0000U)
30507 #define SEMC_NORCR2_LC_SHIFT (16U)
30510 #define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
30511 #define SEMC_NORCR2_RD_MASK (0xF00000U)
30512 #define SEMC_NORCR2_RD_SHIFT (20U)
30515 #define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
30516 #define SEMC_NORCR2_CEITV_MASK (0xF000000U)
30517 #define SEMC_NORCR2_CEITV_SHIFT (24U)
30520 #define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
30525 #define SEMC_SRAMCR0_PS_MASK (0x1U)
30526 #define SEMC_SRAMCR0_PS_SHIFT (0U)
30531 #define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
30532 #define SEMC_SRAMCR0_BL_MASK (0x70U)
30533 #define SEMC_SRAMCR0_BL_SHIFT (4U)
30544 #define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
30545 #define SEMC_SRAMCR0_AM_MASK (0x300U)
30546 #define SEMC_SRAMCR0_AM_SHIFT (8U)
30553 #define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
30554 #define SEMC_SRAMCR0_ADVP_MASK (0x400U)
30555 #define SEMC_SRAMCR0_ADVP_SHIFT (10U)
30560 #define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
30561 #define SEMC_SRAMCR0_COL_MASK (0xF000U)
30562 #define SEMC_SRAMCR0_COL_SHIFT (12U)
30581 #define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
30586 #define SEMC_SRAMCR1_CES_MASK (0xFU)
30587 #define SEMC_SRAMCR1_CES_SHIFT (0U)
30590 #define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
30591 #define SEMC_SRAMCR1_CEH_MASK (0xF0U)
30592 #define SEMC_SRAMCR1_CEH_SHIFT (4U)
30595 #define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
30596 #define SEMC_SRAMCR1_AS_MASK (0xF00U)
30597 #define SEMC_SRAMCR1_AS_SHIFT (8U)
30600 #define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
30601 #define SEMC_SRAMCR1_AH_MASK (0xF000U)
30602 #define SEMC_SRAMCR1_AH_SHIFT (12U)
30605 #define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
30606 #define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
30607 #define SEMC_SRAMCR1_WEL_SHIFT (16U)
30610 #define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
30611 #define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
30612 #define SEMC_SRAMCR1_WEH_SHIFT (20U)
30615 #define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
30616 #define SEMC_SRAMCR1_REL_MASK (0xF000000U)
30617 #define SEMC_SRAMCR1_REL_SHIFT (24U)
30620 #define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
30621 #define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
30622 #define SEMC_SRAMCR1_REH_SHIFT (28U)
30625 #define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
30630 #define SEMC_SRAMCR2_WDS_MASK (0xFU)
30631 #define SEMC_SRAMCR2_WDS_SHIFT (0U)
30634 #define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
30635 #define SEMC_SRAMCR2_WDH_MASK (0xF0U)
30636 #define SEMC_SRAMCR2_WDH_SHIFT (4U)
30639 #define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
30640 #define SEMC_SRAMCR2_TA_MASK (0xF00U)
30641 #define SEMC_SRAMCR2_TA_SHIFT (8U)
30644 #define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
30645 #define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
30646 #define SEMC_SRAMCR2_AWDH_SHIFT (12U)
30649 #define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
30650 #define SEMC_SRAMCR2_LC_MASK (0xF0000U)
30651 #define SEMC_SRAMCR2_LC_SHIFT (16U)
30654 #define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
30655 #define SEMC_SRAMCR2_RD_MASK (0xF00000U)
30656 #define SEMC_SRAMCR2_RD_SHIFT (20U)
30659 #define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
30660 #define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
30661 #define SEMC_SRAMCR2_CEITV_SHIFT (24U)
30664 #define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
30669 #define SEMC_DBICR0_PS_MASK (0x1U)
30670 #define SEMC_DBICR0_PS_SHIFT (0U)
30675 #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
30676 #define SEMC_DBICR0_BL_MASK (0x70U)
30677 #define SEMC_DBICR0_BL_SHIFT (4U)
30688 #define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
30689 #define SEMC_DBICR0_COL_MASK (0xF000U)
30690 #define SEMC_DBICR0_COL_SHIFT (12U)
30709 #define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
30714 #define SEMC_DBICR1_CES_MASK (0xFU)
30715 #define SEMC_DBICR1_CES_SHIFT (0U)
30718 #define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
30719 #define SEMC_DBICR1_CEH_MASK (0xF0U)
30720 #define SEMC_DBICR1_CEH_SHIFT (4U)
30723 #define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
30724 #define SEMC_DBICR1_WEL_MASK (0xF00U)
30725 #define SEMC_DBICR1_WEL_SHIFT (8U)
30728 #define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
30729 #define SEMC_DBICR1_WEH_MASK (0xF000U)
30730 #define SEMC_DBICR1_WEH_SHIFT (12U)
30733 #define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
30734 #define SEMC_DBICR1_REL_MASK (0xF0000U)
30735 #define SEMC_DBICR1_REL_SHIFT (16U)
30738 #define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
30739 #define SEMC_DBICR1_REH_MASK (0xF00000U)
30740 #define SEMC_DBICR1_REH_SHIFT (20U)
30743 #define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
30744 #define SEMC_DBICR1_CEITV_MASK (0xF000000U)
30745 #define SEMC_DBICR1_CEITV_SHIFT (24U)
30748 #define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
30753 #define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
30754 #define SEMC_IPCR0_SA_SHIFT (0U)
30757 #define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
30762 #define SEMC_IPCR1_DATSZ_MASK (0x7U)
30763 #define SEMC_IPCR1_DATSZ_SHIFT (0U)
30774 #define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
30779 #define SEMC_IPCR2_BM0_MASK (0x1U)
30780 #define SEMC_IPCR2_BM0_SHIFT (0U)
30785 #define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
30786 #define SEMC_IPCR2_BM1_MASK (0x2U)
30787 #define SEMC_IPCR2_BM1_SHIFT (1U)
30792 #define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
30793 #define SEMC_IPCR2_BM2_MASK (0x4U)
30794 #define SEMC_IPCR2_BM2_SHIFT (2U)
30799 #define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
30800 #define SEMC_IPCR2_BM3_MASK (0x8U)
30801 #define SEMC_IPCR2_BM3_SHIFT (3U)
30806 #define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
30811 #define SEMC_IPCMD_CMD_MASK (0xFFFFU)
30812 #define SEMC_IPCMD_CMD_SHIFT (0U)
30813 #define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
30814 #define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
30815 #define SEMC_IPCMD_KEY_SHIFT (16U)
30818 #define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
30823 #define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
30824 #define SEMC_IPTXDAT_DAT_SHIFT (0U)
30827 #define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
30832 #define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
30833 #define SEMC_IPRXDAT_DAT_SHIFT (0U)
30836 #define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
30841 #define SEMC_STS0_IDLE_MASK (0x1U)
30842 #define SEMC_STS0_IDLE_SHIFT (0U)
30845 #define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
30846 #define SEMC_STS0_NARDY_MASK (0x2U)
30847 #define SEMC_STS0_NARDY_SHIFT (1U)
30852 #define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
30857 #define SEMC_STS2_NDWRPEND_MASK (0x8U)
30858 #define SEMC_STS2_NDWRPEND_SHIFT (3U)
30863 #define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
30868 #define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
30869 #define SEMC_STS12_NDADDR_SHIFT (0U)
30872 #define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) /* end of group SEMC_Register_Masks */
30879 
30880 
30881 /* SEMC - Peripheral instance base addresses */
30883 #define SEMC_BASE (0x402F0000u)
30885 #define SEMC ((SEMC_Type *)SEMC_BASE)
30887 #define SEMC_BASE_ADDRS { SEMC_BASE }
30889 #define SEMC_BASE_PTRS { SEMC }
30891 #define SEMC_IRQS { SEMC_IRQn }
30892  /* end of group SEMC_Peripheral_Access_Layer */
30896 
30897 
30898 /* ----------------------------------------------------------------------------
30899  -- SNVS Peripheral Access Layer
30900  ---------------------------------------------------------------------------- */
30901 
30908 typedef struct {
30909  __IO uint32_t HPLR;
30910  __IO uint32_t HPCOMR;
30911  __IO uint32_t HPCR;
30912  __IO uint32_t HPSICR;
30913  __IO uint32_t HPSVCR;
30914  __IO uint32_t HPSR;
30915  __IO uint32_t HPSVSR;
30916  __IO uint32_t HPHACIVR;
30917  __I uint32_t HPHACR;
30918  __IO uint32_t HPRTCMR;
30919  __IO uint32_t HPRTCLR;
30920  __IO uint32_t HPTAMR;
30921  __IO uint32_t HPTALR;
30922  __IO uint32_t LPLR;
30923  __IO uint32_t LPCR;
30924  __IO uint32_t LPMKCR;
30925  __IO uint32_t LPSVCR;
30926  uint8_t RESERVED_0[4];
30927  __IO uint32_t LPTDCR;
30928  __IO uint32_t LPSR;
30929  __IO uint32_t LPSRTCMR;
30930  __IO uint32_t LPSRTCLR;
30931  __IO uint32_t LPTAR;
30932  __IO uint32_t LPSMCMR;
30933  __IO uint32_t LPSMCLR;
30934  __IO uint32_t LPPGDR;
30935  __IO uint32_t LPGPR0_LEGACY_ALIAS;
30936  __IO uint32_t LPZMKR[8];
30937  uint8_t RESERVED_1[4];
30938  __IO uint32_t LPGPR_ALIAS[4];
30939  uint8_t RESERVED_2[96];
30940  __IO uint32_t LPGPR[8];
30941  uint8_t RESERVED_3[2776];
30942  __I uint32_t HPVIDR1;
30943  __I uint32_t HPVIDR2;
30944 } SNVS_Type;
30945 
30946 /* ----------------------------------------------------------------------------
30947  -- SNVS Register Masks
30948  ---------------------------------------------------------------------------- */
30949 
30957 #define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
30958 #define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
30963 #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
30964 #define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
30965 #define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
30970 #define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
30971 #define SNVS_HPLR_SRTC_SL_MASK (0x4U)
30972 #define SNVS_HPLR_SRTC_SL_SHIFT (2U)
30977 #define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
30978 #define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
30979 #define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
30984 #define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
30985 #define SNVS_HPLR_MC_SL_MASK (0x10U)
30986 #define SNVS_HPLR_MC_SL_SHIFT (4U)
30991 #define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
30992 #define SNVS_HPLR_GPR_SL_MASK (0x20U)
30993 #define SNVS_HPLR_GPR_SL_SHIFT (5U)
30998 #define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
30999 #define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
31000 #define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
31005 #define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
31006 #define SNVS_HPLR_LPTDCR_SL_MASK (0x100U)
31007 #define SNVS_HPLR_LPTDCR_SL_SHIFT (8U)
31012 #define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)
31013 #define SNVS_HPLR_MKS_SL_MASK (0x200U)
31014 #define SNVS_HPLR_MKS_SL_SHIFT (9U)
31019 #define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
31020 #define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
31021 #define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
31026 #define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
31027 #define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
31028 #define SNVS_HPLR_HPSICR_L_SHIFT (17U)
31033 #define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
31034 #define SNVS_HPLR_HAC_L_MASK (0x40000U)
31035 #define SNVS_HPLR_HAC_L_SHIFT (18U)
31040 #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
31045 #define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
31046 #define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
31047 #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
31048 #define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
31049 #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
31054 #define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
31055 #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
31056 #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
31061 #define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
31062 #define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
31063 #define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
31068 #define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
31069 #define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
31070 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
31075 #define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
31076 #define SNVS_HPCOMR_SW_SV_MASK (0x100U)
31077 #define SNVS_HPCOMR_SW_SV_SHIFT (8U)
31078 #define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
31079 #define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
31080 #define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
31081 #define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
31082 #define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
31083 #define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
31084 #define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
31085 #define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
31086 #define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
31091 #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
31092 #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
31093 #define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
31098 #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
31099 #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
31100 #define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
31105 #define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
31106 #define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
31107 #define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
31112 #define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
31113 #define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
31114 #define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
31119 #define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
31120 #define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
31121 #define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
31122 #define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
31123 #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
31124 #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
31125 #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
31130 #define SNVS_HPCR_RTC_EN_MASK (0x1U)
31131 #define SNVS_HPCR_RTC_EN_SHIFT (0U)
31136 #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
31137 #define SNVS_HPCR_HPTA_EN_MASK (0x2U)
31138 #define SNVS_HPCR_HPTA_EN_SHIFT (1U)
31143 #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
31144 #define SNVS_HPCR_DIS_PI_MASK (0x4U)
31145 #define SNVS_HPCR_DIS_PI_SHIFT (2U)
31150 #define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
31151 #define SNVS_HPCR_PI_EN_MASK (0x8U)
31152 #define SNVS_HPCR_PI_EN_SHIFT (3U)
31157 #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
31158 #define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
31159 #define SNVS_HPCR_PI_FREQ_SHIFT (4U)
31178 #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
31179 #define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
31180 #define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
31185 #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
31186 #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
31187 #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
31198 #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
31199 #define SNVS_HPCR_HP_TS_MASK (0x10000U)
31200 #define SNVS_HPCR_HP_TS_SHIFT (16U)
31205 #define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
31206 #define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
31207 #define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
31208 #define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
31209 #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
31210 #define SNVS_HPCR_BTN_MASK_SHIFT (27U)
31211 #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
31216 #define SNVS_HPSICR_SV0_EN_MASK (0x1U)
31217 #define SNVS_HPSICR_SV0_EN_SHIFT (0U)
31222 #define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
31223 #define SNVS_HPSICR_SV1_EN_MASK (0x2U)
31224 #define SNVS_HPSICR_SV1_EN_SHIFT (1U)
31229 #define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
31230 #define SNVS_HPSICR_SV2_EN_MASK (0x4U)
31231 #define SNVS_HPSICR_SV2_EN_SHIFT (2U)
31236 #define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
31237 #define SNVS_HPSICR_SV3_EN_MASK (0x8U)
31238 #define SNVS_HPSICR_SV3_EN_SHIFT (3U)
31243 #define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
31244 #define SNVS_HPSICR_SV4_EN_MASK (0x10U)
31245 #define SNVS_HPSICR_SV4_EN_SHIFT (4U)
31250 #define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
31251 #define SNVS_HPSICR_SV5_EN_MASK (0x20U)
31252 #define SNVS_HPSICR_SV5_EN_SHIFT (5U)
31257 #define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
31258 #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
31259 #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
31264 #define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
31269 #define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
31270 #define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
31275 #define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
31276 #define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
31277 #define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
31282 #define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
31283 #define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
31284 #define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
31289 #define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
31290 #define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
31291 #define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
31296 #define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
31297 #define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
31298 #define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
31303 #define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
31304 #define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
31305 #define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
31311 #define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
31312 #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
31313 #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
31319 #define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
31324 #define SNVS_HPSR_HPTA_MASK (0x1U)
31325 #define SNVS_HPSR_HPTA_SHIFT (0U)
31330 #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
31331 #define SNVS_HPSR_PI_MASK (0x2U)
31332 #define SNVS_HPSR_PI_SHIFT (1U)
31337 #define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
31338 #define SNVS_HPSR_LPDIS_MASK (0x10U)
31339 #define SNVS_HPSR_LPDIS_SHIFT (4U)
31340 #define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
31341 #define SNVS_HPSR_BTN_MASK (0x40U)
31342 #define SNVS_HPSR_BTN_SHIFT (6U)
31343 #define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
31344 #define SNVS_HPSR_BI_MASK (0x80U)
31345 #define SNVS_HPSR_BI_SHIFT (7U)
31346 #define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
31347 #define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
31348 #define SNVS_HPSR_SSM_STATE_SHIFT (8U)
31359 #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
31360 #define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U)
31361 #define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U)
31368 #define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
31369 #define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U)
31370 #define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U)
31371 #define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
31372 #define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
31373 #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
31374 #define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
31375 #define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
31376 #define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
31381 #define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
31382 #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
31383 #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
31388 #define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
31393 #define SNVS_HPSVSR_SV0_MASK (0x1U)
31394 #define SNVS_HPSVSR_SV0_SHIFT (0U)
31399 #define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
31400 #define SNVS_HPSVSR_SV1_MASK (0x2U)
31401 #define SNVS_HPSVSR_SV1_SHIFT (1U)
31406 #define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
31407 #define SNVS_HPSVSR_SV2_MASK (0x4U)
31408 #define SNVS_HPSVSR_SV2_SHIFT (2U)
31413 #define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
31414 #define SNVS_HPSVSR_SV3_MASK (0x8U)
31415 #define SNVS_HPSVSR_SV3_SHIFT (3U)
31420 #define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
31421 #define SNVS_HPSVSR_SV4_MASK (0x10U)
31422 #define SNVS_HPSVSR_SV4_SHIFT (4U)
31427 #define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
31428 #define SNVS_HPSVSR_SV5_MASK (0x20U)
31429 #define SNVS_HPSVSR_SV5_SHIFT (5U)
31434 #define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
31435 #define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
31436 #define SNVS_HPSVSR_SW_SV_SHIFT (13U)
31437 #define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
31438 #define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
31439 #define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
31440 #define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
31441 #define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
31442 #define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
31443 #define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
31444 #define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
31445 #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
31446 #define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
31447 #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
31448 #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
31453 #define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
31454 #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
31455 #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
31456 #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
31461 #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
31462 #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
31463 #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
31468 #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
31469 #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
31470 #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
31475 #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
31476 #define SNVS_HPRTCMR_RTC_SHIFT (0U)
31477 #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
31482 #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
31483 #define SNVS_HPRTCLR_RTC_SHIFT (0U)
31484 #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
31489 #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
31490 #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
31491 #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
31496 #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
31497 #define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
31498 #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
31503 #define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
31504 #define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
31509 #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
31510 #define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
31511 #define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
31516 #define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
31517 #define SNVS_LPLR_SRTC_HL_MASK (0x4U)
31518 #define SNVS_LPLR_SRTC_HL_SHIFT (2U)
31523 #define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
31524 #define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
31525 #define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
31530 #define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
31531 #define SNVS_LPLR_MC_HL_MASK (0x10U)
31532 #define SNVS_LPLR_MC_HL_SHIFT (4U)
31537 #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
31538 #define SNVS_LPLR_GPR_HL_MASK (0x20U)
31539 #define SNVS_LPLR_GPR_HL_SHIFT (5U)
31544 #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
31545 #define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
31546 #define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
31551 #define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
31552 #define SNVS_LPLR_LPTDCR_HL_MASK (0x100U)
31553 #define SNVS_LPLR_LPTDCR_HL_SHIFT (8U)
31558 #define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)
31559 #define SNVS_LPLR_MKS_HL_MASK (0x200U)
31560 #define SNVS_LPLR_MKS_HL_SHIFT (9U)
31565 #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
31570 #define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
31571 #define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
31576 #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
31577 #define SNVS_LPCR_LPTA_EN_MASK (0x2U)
31578 #define SNVS_LPCR_LPTA_EN_SHIFT (1U)
31583 #define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
31584 #define SNVS_LPCR_MC_ENV_MASK (0x4U)
31585 #define SNVS_LPCR_MC_ENV_SHIFT (2U)
31590 #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
31591 #define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
31592 #define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
31593 #define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
31594 #define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
31595 #define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
31600 #define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
31601 #define SNVS_LPCR_DP_EN_MASK (0x20U)
31602 #define SNVS_LPCR_DP_EN_SHIFT (5U)
31607 #define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
31608 #define SNVS_LPCR_TOP_MASK (0x40U)
31609 #define SNVS_LPCR_TOP_SHIFT (6U)
31614 #define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
31615 #define SNVS_LPCR_LVD_EN_MASK (0x80U)
31616 #define SNVS_LPCR_LVD_EN_SHIFT (7U)
31617 #define SNVS_LPCR_LVD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
31618 #define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
31619 #define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
31624 #define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
31625 #define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
31626 #define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
31637 #define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
31638 #define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
31639 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
31640 #define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
31641 #define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
31642 #define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
31643 #define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
31644 #define SNVS_LPCR_ON_TIME_MASK (0x300000U)
31645 #define SNVS_LPCR_ON_TIME_SHIFT (20U)
31646 #define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
31647 #define SNVS_LPCR_PK_EN_MASK (0x400000U)
31648 #define SNVS_LPCR_PK_EN_SHIFT (22U)
31649 #define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
31650 #define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
31651 #define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
31652 #define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
31653 #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
31654 #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
31655 #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
31660 #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
31661 #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
31667 #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
31668 #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
31669 #define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
31674 #define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
31675 #define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
31676 #define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
31681 #define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
31682 #define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
31683 #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
31688 #define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
31689 #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
31690 #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
31691 #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
31696 #define SNVS_LPSVCR_SV0_EN_MASK (0x1U)
31697 #define SNVS_LPSVCR_SV0_EN_SHIFT (0U)
31702 #define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
31703 #define SNVS_LPSVCR_SV1_EN_MASK (0x2U)
31704 #define SNVS_LPSVCR_SV1_EN_SHIFT (1U)
31709 #define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
31710 #define SNVS_LPSVCR_SV2_EN_MASK (0x4U)
31711 #define SNVS_LPSVCR_SV2_EN_SHIFT (2U)
31716 #define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
31717 #define SNVS_LPSVCR_SV3_EN_MASK (0x8U)
31718 #define SNVS_LPSVCR_SV3_EN_SHIFT (3U)
31723 #define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
31724 #define SNVS_LPSVCR_SV4_EN_MASK (0x10U)
31725 #define SNVS_LPSVCR_SV4_EN_SHIFT (4U)
31730 #define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
31731 #define SNVS_LPSVCR_SV5_EN_MASK (0x20U)
31732 #define SNVS_LPSVCR_SV5_EN_SHIFT (5U)
31737 #define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
31742 #define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
31743 #define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
31748 #define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
31749 #define SNVS_LPTDCR_MCR_EN_MASK (0x4U)
31750 #define SNVS_LPTDCR_MCR_EN_SHIFT (2U)
31755 #define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
31756 #define SNVS_LPTDCR_ET1_EN_MASK (0x200U)
31757 #define SNVS_LPTDCR_ET1_EN_SHIFT (9U)
31762 #define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
31763 #define SNVS_LPTDCR_ET1P_MASK (0x800U)
31764 #define SNVS_LPTDCR_ET1P_SHIFT (11U)
31769 #define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
31770 #define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
31771 #define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
31772 #define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
31773 #define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
31774 #define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
31775 #define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
31776 #define SNVS_LPTDCR_OSCB_MASK (0x10000000U)
31777 #define SNVS_LPTDCR_OSCB_SHIFT (28U)
31782 #define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
31787 #define SNVS_LPSR_LPTA_MASK (0x1U)
31788 #define SNVS_LPSR_LPTA_SHIFT (0U)
31793 #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
31794 #define SNVS_LPSR_SRTCR_MASK (0x2U)
31795 #define SNVS_LPSR_SRTCR_SHIFT (1U)
31800 #define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
31801 #define SNVS_LPSR_MCR_MASK (0x4U)
31802 #define SNVS_LPSR_MCR_SHIFT (2U)
31807 #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
31808 #define SNVS_LPSR_PGD_MASK (0x8U)
31809 #define SNVS_LPSR_PGD_SHIFT (3U)
31810 #define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
31811 #define SNVS_LPSR_ET1D_MASK (0x200U)
31812 #define SNVS_LPSR_ET1D_SHIFT (9U)
31817 #define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
31818 #define SNVS_LPSR_ESVD_MASK (0x10000U)
31819 #define SNVS_LPSR_ESVD_SHIFT (16U)
31824 #define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
31825 #define SNVS_LPSR_EO_MASK (0x20000U)
31826 #define SNVS_LPSR_EO_SHIFT (17U)
31831 #define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
31832 #define SNVS_LPSR_SPOF_MASK (0x40000U)
31833 #define SNVS_LPSR_SPOF_SHIFT (18U)
31838 #define SNVS_LPSR_SPOF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
31839 #define SNVS_LPSR_SPON_MASK (0x80000U)
31840 #define SNVS_LPSR_SPON_SHIFT (19U)
31845 #define SNVS_LPSR_SPON(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPON_SHIFT)) & SNVS_LPSR_SPON_MASK)
31846 #define SNVS_LPSR_LPNS_MASK (0x40000000U)
31847 #define SNVS_LPSR_LPNS_SHIFT (30U)
31852 #define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
31853 #define SNVS_LPSR_LPS_MASK (0x80000000U)
31854 #define SNVS_LPSR_LPS_SHIFT (31U)
31859 #define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
31864 #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
31865 #define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
31866 #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
31871 #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
31872 #define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
31873 #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
31878 #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
31879 #define SNVS_LPTAR_LPTA_SHIFT (0U)
31880 #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
31885 #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
31886 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
31887 #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
31888 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
31889 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
31890 #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
31895 #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
31896 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
31897 #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
31902 #define SNVS_LPLVDR_LVD_MASK (0xFFFFFFFFU)
31903 #define SNVS_LPLVDR_LVD_SHIFT (0U)
31904 #define SNVS_LPLVDR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
31909 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
31910 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
31911 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
31916 #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
31917 #define SNVS_LPZMKR_ZMK_SHIFT (0U)
31918 #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
31921 /* The count of SNVS_LPZMKR */
31922 #define SNVS_LPZMKR_COUNT (8U)
31923 
31926 #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
31927 #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
31928 #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
31931 /* The count of SNVS_LPGPR_ALIAS */
31932 #define SNVS_LPGPR_ALIAS_COUNT (4U)
31933 
31936 #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
31937 #define SNVS_LPGPR_GPR_SHIFT (0U)
31938 #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
31941 /* The count of SNVS_LPGPR */
31942 #define SNVS_LPGPR_COUNT (8U)
31943 
31946 #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
31947 #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
31948 #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
31949 #define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
31950 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
31951 #define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
31952 #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
31953 #define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
31954 #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
31959 #define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
31960 #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
31961 #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
31962 #define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
31963 #define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
31964 #define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
31965 #define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
31966 #define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
31967 #define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
31968 #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
31969 #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
31970 #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) /* end of group SNVS_Register_Masks */
31977 
31978 
31979 /* SNVS - Peripheral instance base addresses */
31981 #define SNVS_BASE (0x400D4000u)
31983 #define SNVS ((SNVS_Type *)SNVS_BASE)
31985 #define SNVS_BASE_ADDRS { SNVS_BASE }
31987 #define SNVS_BASE_PTRS { SNVS }
31989 #define SNVS_IRQS { SNVS_LP_HP_WRAPPER_IRQn }
31990 #define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }
31991 #define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }
31992  /* end of group SNVS_Peripheral_Access_Layer */
31996 
31997 
31998 /* ----------------------------------------------------------------------------
31999  -- SPDIF Peripheral Access Layer
32000  ---------------------------------------------------------------------------- */
32001 
32008 typedef struct {
32009  __IO uint32_t SCR;
32010  __IO uint32_t SRCD;
32011  __IO uint32_t SRPC;
32012  __IO uint32_t SIE;
32013  union { /* offset: 0x10 */
32014  __O uint32_t SIC;
32015  __I uint32_t SIS;
32016  };
32017  __I uint32_t SRL;
32018  __I uint32_t SRR;
32019  __I uint32_t SRCSH;
32020  __I uint32_t SRCSL;
32021  __I uint32_t SRU;
32022  __I uint32_t SRQ;
32023  __O uint32_t STL;
32024  __O uint32_t STR;
32025  __IO uint32_t STCSCH;
32026  __IO uint32_t STCSCL;
32027  uint8_t RESERVED_0[8];
32028  __I uint32_t SRFM;
32029  uint8_t RESERVED_1[8];
32030  __IO uint32_t STC;
32031 } SPDIF_Type;
32032 
32033 /* ----------------------------------------------------------------------------
32034  -- SPDIF Register Masks
32035  ---------------------------------------------------------------------------- */
32036 
32044 #define SPDIF_SCR_USRC_SEL_MASK (0x3U)
32045 #define SPDIF_SCR_USRC_SEL_SHIFT (0U)
32052 #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
32053 #define SPDIF_SCR_TXSEL_MASK (0x1CU)
32054 #define SPDIF_SCR_TXSEL_SHIFT (2U)
32060 #define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
32061 #define SPDIF_SCR_VALCTRL_MASK (0x20U)
32062 #define SPDIF_SCR_VALCTRL_SHIFT (5U)
32067 #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
32068 #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
32069 #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
32070 #define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
32071 #define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
32072 #define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
32073 #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
32074 #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
32075 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
32082 #define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
32083 #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
32084 #define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
32085 #define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
32086 #define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
32087 #define SPDIF_SCR_LOW_POWER_SHIFT (13U)
32088 #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
32089 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
32090 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
32097 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
32098 #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
32099 #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
32104 #define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
32105 #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
32106 #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
32111 #define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
32112 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
32113 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
32120 #define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
32121 #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
32122 #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
32127 #define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
32128 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
32129 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
32134 #define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
32135 #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
32136 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
32141 #define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
32146 #define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
32147 #define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
32152 #define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
32157 #define SPDIF_SRPC_GAINSEL_MASK (0x38U)
32158 #define SPDIF_SRPC_GAINSEL_SHIFT (3U)
32168 #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
32169 #define SPDIF_SRPC_LOCK_MASK (0x40U)
32170 #define SPDIF_SRPC_LOCK_SHIFT (6U)
32171 #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
32172 #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
32173 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
32182 #define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
32187 #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
32188 #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
32189 #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
32190 #define SPDIF_SIE_TXEM_MASK (0x2U)
32191 #define SPDIF_SIE_TXEM_SHIFT (1U)
32192 #define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
32193 #define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
32194 #define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
32195 #define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
32196 #define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
32197 #define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
32198 #define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
32199 #define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
32200 #define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
32201 #define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
32202 #define SPDIF_SIE_UQERR_MASK (0x20U)
32203 #define SPDIF_SIE_UQERR_SHIFT (5U)
32204 #define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
32205 #define SPDIF_SIE_UQSYNC_MASK (0x40U)
32206 #define SPDIF_SIE_UQSYNC_SHIFT (6U)
32207 #define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
32208 #define SPDIF_SIE_QRXOV_MASK (0x80U)
32209 #define SPDIF_SIE_QRXOV_SHIFT (7U)
32210 #define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
32211 #define SPDIF_SIE_QRXFUL_MASK (0x100U)
32212 #define SPDIF_SIE_QRXFUL_SHIFT (8U)
32213 #define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
32214 #define SPDIF_SIE_URXOV_MASK (0x200U)
32215 #define SPDIF_SIE_URXOV_SHIFT (9U)
32216 #define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
32217 #define SPDIF_SIE_URXFUL_MASK (0x400U)
32218 #define SPDIF_SIE_URXFUL_SHIFT (10U)
32219 #define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
32220 #define SPDIF_SIE_BITERR_MASK (0x4000U)
32221 #define SPDIF_SIE_BITERR_SHIFT (14U)
32222 #define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
32223 #define SPDIF_SIE_SYMERR_MASK (0x8000U)
32224 #define SPDIF_SIE_SYMERR_SHIFT (15U)
32225 #define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
32226 #define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
32227 #define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
32228 #define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
32229 #define SPDIF_SIE_CNEW_MASK (0x20000U)
32230 #define SPDIF_SIE_CNEW_SHIFT (17U)
32231 #define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
32232 #define SPDIF_SIE_TXRESYN_MASK (0x40000U)
32233 #define SPDIF_SIE_TXRESYN_SHIFT (18U)
32234 #define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
32235 #define SPDIF_SIE_TXUNOV_MASK (0x80000U)
32236 #define SPDIF_SIE_TXUNOV_SHIFT (19U)
32237 #define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
32238 #define SPDIF_SIE_LOCK_MASK (0x100000U)
32239 #define SPDIF_SIE_LOCK_SHIFT (20U)
32240 #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
32245 #define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
32246 #define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
32247 #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
32248 #define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
32249 #define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
32250 #define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
32251 #define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
32252 #define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
32253 #define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
32254 #define SPDIF_SIC_UQERR_MASK (0x20U)
32255 #define SPDIF_SIC_UQERR_SHIFT (5U)
32256 #define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
32257 #define SPDIF_SIC_UQSYNC_MASK (0x40U)
32258 #define SPDIF_SIC_UQSYNC_SHIFT (6U)
32259 #define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
32260 #define SPDIF_SIC_QRXOV_MASK (0x80U)
32261 #define SPDIF_SIC_QRXOV_SHIFT (7U)
32262 #define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
32263 #define SPDIF_SIC_URXOV_MASK (0x200U)
32264 #define SPDIF_SIC_URXOV_SHIFT (9U)
32265 #define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
32266 #define SPDIF_SIC_BITERR_MASK (0x4000U)
32267 #define SPDIF_SIC_BITERR_SHIFT (14U)
32268 #define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
32269 #define SPDIF_SIC_SYMERR_MASK (0x8000U)
32270 #define SPDIF_SIC_SYMERR_SHIFT (15U)
32271 #define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
32272 #define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
32273 #define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
32274 #define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
32275 #define SPDIF_SIC_CNEW_MASK (0x20000U)
32276 #define SPDIF_SIC_CNEW_SHIFT (17U)
32277 #define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
32278 #define SPDIF_SIC_TXRESYN_MASK (0x40000U)
32279 #define SPDIF_SIC_TXRESYN_SHIFT (18U)
32280 #define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
32281 #define SPDIF_SIC_TXUNOV_MASK (0x80000U)
32282 #define SPDIF_SIC_TXUNOV_SHIFT (19U)
32283 #define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
32284 #define SPDIF_SIC_LOCK_MASK (0x100000U)
32285 #define SPDIF_SIC_LOCK_SHIFT (20U)
32286 #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
32291 #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
32292 #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
32293 #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
32294 #define SPDIF_SIS_TXEM_MASK (0x2U)
32295 #define SPDIF_SIS_TXEM_SHIFT (1U)
32296 #define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
32297 #define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
32298 #define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
32299 #define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
32300 #define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
32301 #define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
32302 #define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
32303 #define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
32304 #define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
32305 #define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
32306 #define SPDIF_SIS_UQERR_MASK (0x20U)
32307 #define SPDIF_SIS_UQERR_SHIFT (5U)
32308 #define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
32309 #define SPDIF_SIS_UQSYNC_MASK (0x40U)
32310 #define SPDIF_SIS_UQSYNC_SHIFT (6U)
32311 #define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
32312 #define SPDIF_SIS_QRXOV_MASK (0x80U)
32313 #define SPDIF_SIS_QRXOV_SHIFT (7U)
32314 #define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
32315 #define SPDIF_SIS_QRXFUL_MASK (0x100U)
32316 #define SPDIF_SIS_QRXFUL_SHIFT (8U)
32317 #define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
32318 #define SPDIF_SIS_URXOV_MASK (0x200U)
32319 #define SPDIF_SIS_URXOV_SHIFT (9U)
32320 #define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
32321 #define SPDIF_SIS_URXFUL_MASK (0x400U)
32322 #define SPDIF_SIS_URXFUL_SHIFT (10U)
32323 #define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
32324 #define SPDIF_SIS_BITERR_MASK (0x4000U)
32325 #define SPDIF_SIS_BITERR_SHIFT (14U)
32326 #define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
32327 #define SPDIF_SIS_SYMERR_MASK (0x8000U)
32328 #define SPDIF_SIS_SYMERR_SHIFT (15U)
32329 #define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
32330 #define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
32331 #define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
32332 #define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
32333 #define SPDIF_SIS_CNEW_MASK (0x20000U)
32334 #define SPDIF_SIS_CNEW_SHIFT (17U)
32335 #define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
32336 #define SPDIF_SIS_TXRESYN_MASK (0x40000U)
32337 #define SPDIF_SIS_TXRESYN_SHIFT (18U)
32338 #define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
32339 #define SPDIF_SIS_TXUNOV_MASK (0x80000U)
32340 #define SPDIF_SIS_TXUNOV_SHIFT (19U)
32341 #define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
32342 #define SPDIF_SIS_LOCK_MASK (0x100000U)
32343 #define SPDIF_SIS_LOCK_SHIFT (20U)
32344 #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
32349 #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
32350 #define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
32351 #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
32356 #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
32357 #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
32358 #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
32363 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
32364 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
32365 #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
32370 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
32371 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
32372 #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
32377 #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
32378 #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
32379 #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
32384 #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
32385 #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
32386 #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
32391 #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
32392 #define SPDIF_STL_TXDATALEFT_SHIFT (0U)
32393 #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
32398 #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
32399 #define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
32400 #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
32405 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
32406 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
32407 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
32412 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
32413 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
32414 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
32419 #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
32420 #define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
32421 #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
32426 #define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
32427 #define SPDIF_STC_TXCLK_DF_SHIFT (0U)
32433 #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
32434 #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
32435 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
32440 #define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
32441 #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
32442 #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
32452 #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
32453 #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
32454 #define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
32460 #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) /* end of group SPDIF_Register_Masks */
32467 
32468 
32469 /* SPDIF - Peripheral instance base addresses */
32471 #define SPDIF_BASE (0x40380000u)
32473 #define SPDIF ((SPDIF_Type *)SPDIF_BASE)
32475 #define SPDIF_BASE_ADDRS { SPDIF_BASE }
32477 #define SPDIF_BASE_PTRS { SPDIF }
32479 #define SPDIF_IRQS { SPDIF_IRQn }
32480  /* end of group SPDIF_Peripheral_Access_Layer */
32484 
32485 
32486 /* ----------------------------------------------------------------------------
32487  -- SRC Peripheral Access Layer
32488  ---------------------------------------------------------------------------- */
32489 
32496 typedef struct {
32497  __IO uint32_t SCR;
32498  __I uint32_t SBMR1;
32499  __IO uint32_t SRSR;
32500  uint8_t RESERVED_0[16];
32501  __I uint32_t SBMR2;
32502  __IO uint32_t GPR[10];
32503 } SRC_Type;
32504 
32505 /* ----------------------------------------------------------------------------
32506  -- SRC Register Masks
32507  ---------------------------------------------------------------------------- */
32508 
32516 #define SRC_SCR_LOCKUP_RST_MASK (0x10U)
32517 #define SRC_SCR_LOCKUP_RST_SHIFT (4U)
32522 #define SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK)
32523 #define SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
32524 #define SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
32529 #define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
32530 #define SRC_SCR_CORE0_RST_MASK (0x2000U)
32531 #define SRC_SCR_CORE0_RST_SHIFT (13U)
32536 #define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
32537 #define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
32538 #define SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
32543 #define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
32544 #define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
32545 #define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
32550 #define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
32551 #define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
32552 #define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
32557 #define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
32562 #define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
32563 #define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
32564 #define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
32565 #define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
32566 #define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
32567 #define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
32568 #define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
32569 #define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
32570 #define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
32571 #define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
32572 #define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
32573 #define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
32578 #define SRC_SRSR_IPP_RESET_B_MASK (0x1U)
32579 #define SRC_SRSR_IPP_RESET_B_SHIFT (0U)
32584 #define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
32585 #define SRC_SRSR_LOCKUP_MASK (0x2U)
32586 #define SRC_SRSR_LOCKUP_SHIFT (1U)
32591 #define SRC_SRSR_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SHIFT)) & SRC_SRSR_LOCKUP_MASK)
32592 #define SRC_SRSR_CSU_RESET_B_MASK (0x4U)
32593 #define SRC_SRSR_CSU_RESET_B_SHIFT (2U)
32598 #define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
32599 #define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
32600 #define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
32605 #define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
32606 #define SRC_SRSR_WDOG_RST_B_MASK (0x10U)
32607 #define SRC_SRSR_WDOG_RST_B_SHIFT (4U)
32612 #define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
32613 #define SRC_SRSR_JTAG_RST_B_MASK (0x20U)
32614 #define SRC_SRSR_JTAG_RST_B_SHIFT (5U)
32619 #define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
32620 #define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
32621 #define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
32626 #define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
32627 #define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
32628 #define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
32633 #define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
32634 #define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
32635 #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
32640 #define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
32645 #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
32646 #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
32647 #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
32648 #define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
32649 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
32650 #define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
32651 #define SRC_SBMR2_BMOD_MASK (0x3000000U)
32652 #define SRC_SBMR2_BMOD_SHIFT (24U)
32653 #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
32658 #define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
32659 #define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
32660 #define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
32661 #define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
32662 #define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
32663 #define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
32664 #define SRC_GPR_PERSIST_REDUNDANT_BOOT_MASK (0xC000000U)
32665 #define SRC_GPR_PERSIST_REDUNDANT_BOOT_SHIFT (26U)
32666 #define SRC_GPR_PERSIST_REDUNDANT_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSIST_REDUNDANT_BOOT_SHIFT)) & SRC_GPR_PERSIST_REDUNDANT_BOOT_MASK)
32667 #define SRC_GPR_PERSIST_SECONDARY_BOOT_MASK (0x40000000U)
32668 #define SRC_GPR_PERSIST_SECONDARY_BOOT_SHIFT (30U)
32669 #define SRC_GPR_PERSIST_SECONDARY_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSIST_SECONDARY_BOOT_SHIFT)) & SRC_GPR_PERSIST_SECONDARY_BOOT_MASK)
32672 /* The count of SRC_GPR */
32673 #define SRC_GPR_COUNT (10U)
32674 
32675  /* end of group SRC_Register_Masks */
32679 
32680 
32681 /* SRC - Peripheral instance base addresses */
32683 #define SRC_BASE (0x400F8000u)
32685 #define SRC ((SRC_Type *)SRC_BASE)
32687 #define SRC_BASE_ADDRS { SRC_BASE }
32689 #define SRC_BASE_PTRS { SRC }
32691 #define SRC_IRQS { SRC_IRQn }
32692 /* Backward compatibility */
32693 #define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK
32694 #define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT
32695 #define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)
32696 #define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK
32697 #define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT
32698 #define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)
32699 #define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK
32700 #define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT
32701 #define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)
32702 #define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK
32703 #define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT
32704 #define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)
32705 #define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK
32706 #define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT
32707 #define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)
32708 /* Extra definition */
32709 #define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \
32710  | SRC_SRSR_JTAG_SW_RST_MASK \
32711  | SRC_SRSR_JTAG_RST_B_MASK \
32712  | SRC_SRSR_WDOG_RST_B_MASK \
32713  | SRC_SRSR_IPP_USER_RESET_B_MASK \
32714  | SRC_SRSR_CSU_RESET_B_MASK \
32715  | SRC_SRSR_LOCKUP_MASK \
32716  | SRC_SRSR_IPP_RESET_B_MASK)
32717 
32718  /* end of group SRC_Peripheral_Access_Layer */
32722 
32723 
32724 /* ----------------------------------------------------------------------------
32725  -- TEMPMON Peripheral Access Layer
32726  ---------------------------------------------------------------------------- */
32727 
32734 typedef struct {
32735  uint8_t RESERVED_0[384];
32736  __IO uint32_t TEMPSENSE0;
32737  __IO uint32_t TEMPSENSE0_SET;
32738  __IO uint32_t TEMPSENSE0_CLR;
32739  __IO uint32_t TEMPSENSE0_TOG;
32740  __IO uint32_t TEMPSENSE1;
32741  __IO uint32_t TEMPSENSE1_SET;
32742  __IO uint32_t TEMPSENSE1_CLR;
32743  __IO uint32_t TEMPSENSE1_TOG;
32744  uint8_t RESERVED_1[240];
32745  __IO uint32_t TEMPSENSE2;
32746  __IO uint32_t TEMPSENSE2_SET;
32747  __IO uint32_t TEMPSENSE2_CLR;
32748  __IO uint32_t TEMPSENSE2_TOG;
32749 } TEMPMON_Type;
32750 
32751 /* ----------------------------------------------------------------------------
32752  -- TEMPMON Register Masks
32753  ---------------------------------------------------------------------------- */
32754 
32762 #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)
32763 #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)
32768 #define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
32769 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)
32770 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)
32775 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
32776 #define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)
32777 #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)
32782 #define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
32783 #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)
32784 #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)
32785 #define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
32786 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)
32787 #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)
32788 #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
32793 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)
32794 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)
32799 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
32800 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
32801 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
32806 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
32807 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)
32808 #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)
32813 #define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
32814 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)
32815 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)
32816 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
32817 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)
32818 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
32819 #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
32824 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)
32825 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)
32830 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
32831 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
32832 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
32837 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
32838 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)
32839 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)
32844 #define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
32845 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)
32846 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)
32847 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
32848 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)
32849 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
32850 #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
32855 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)
32856 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)
32861 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
32862 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
32863 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
32868 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
32869 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)
32870 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)
32875 #define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
32876 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)
32877 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)
32878 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
32879 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)
32880 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
32881 #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
32886 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)
32887 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)
32888 #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
32893 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
32894 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
32895 #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
32900 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
32901 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
32902 #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
32907 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
32908 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
32909 #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
32914 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)
32915 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
32916 #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
32917 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
32918 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
32919 #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
32924 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
32925 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
32926 #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
32927 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
32928 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
32929 #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
32934 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
32935 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
32936 #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
32937 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
32938 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
32939 #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
32944 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
32945 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
32946 #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
32947 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
32948 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
32949 #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) /* end of group TEMPMON_Register_Masks */
32956 
32957 
32958 /* TEMPMON - Peripheral instance base addresses */
32960 #define TEMPMON_BASE (0x400D8000u)
32962 #define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)
32964 #define TEMPMON_BASE_ADDRS { TEMPMON_BASE }
32966 #define TEMPMON_BASE_PTRS { TEMPMON }
32967  /* end of group TEMPMON_Peripheral_Access_Layer */
32971 
32972 
32973 /* ----------------------------------------------------------------------------
32974  -- TMR Peripheral Access Layer
32975  ---------------------------------------------------------------------------- */
32976 
32983 typedef struct {
32984  struct { /* offset: 0x0, array step: 0x20 */
32985  __IO uint16_t COMP1;
32986  __IO uint16_t COMP2;
32987  __IO uint16_t CAPT;
32988  __IO uint16_t LOAD;
32989  __IO uint16_t HOLD;
32990  __IO uint16_t CNTR;
32991  __IO uint16_t CTRL;
32992  __IO uint16_t SCTRL;
32993  __IO uint16_t CMPLD1;
32994  __IO uint16_t CMPLD2;
32995  __IO uint16_t CSCTRL;
32996  __IO uint16_t FILT;
32997  __IO uint16_t DMA;
32998  uint8_t RESERVED_0[4];
32999  __IO uint16_t ENBL;
33000  } CHANNEL[4];
33001 } TMR_Type;
33002 
33003 /* ----------------------------------------------------------------------------
33004  -- TMR Register Masks
33005  ---------------------------------------------------------------------------- */
33006 
33014 #define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
33015 #define TMR_COMP1_COMPARISON_1_SHIFT (0U)
33018 #define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
33021 /* The count of TMR_COMP1 */
33022 #define TMR_COMP1_COUNT (4U)
33023 
33026 #define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
33027 #define TMR_COMP2_COMPARISON_2_SHIFT (0U)
33030 #define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
33033 /* The count of TMR_COMP2 */
33034 #define TMR_COMP2_COUNT (4U)
33035 
33038 #define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
33039 #define TMR_CAPT_CAPTURE_SHIFT (0U)
33042 #define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
33045 /* The count of TMR_CAPT */
33046 #define TMR_CAPT_COUNT (4U)
33047 
33050 #define TMR_LOAD_LOAD_MASK (0xFFFFU)
33051 #define TMR_LOAD_LOAD_SHIFT (0U)
33054 #define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
33057 /* The count of TMR_LOAD */
33058 #define TMR_LOAD_COUNT (4U)
33059 
33062 #define TMR_HOLD_HOLD_MASK (0xFFFFU)
33063 #define TMR_HOLD_HOLD_SHIFT (0U)
33064 #define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
33067 /* The count of TMR_HOLD */
33068 #define TMR_HOLD_COUNT (4U)
33069 
33072 #define TMR_CNTR_COUNTER_MASK (0xFFFFU)
33073 #define TMR_CNTR_COUNTER_SHIFT (0U)
33074 #define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
33077 /* The count of TMR_CNTR */
33078 #define TMR_CNTR_COUNT (4U)
33079 
33082 #define TMR_CTRL_OUTMODE_MASK (0x7U)
33083 #define TMR_CTRL_OUTMODE_SHIFT (0U)
33094 #define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
33095 #define TMR_CTRL_COINIT_MASK (0x8U)
33096 #define TMR_CTRL_COINIT_SHIFT (3U)
33101 #define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
33102 #define TMR_CTRL_DIR_MASK (0x10U)
33103 #define TMR_CTRL_DIR_SHIFT (4U)
33108 #define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
33109 #define TMR_CTRL_LENGTH_MASK (0x20U)
33110 #define TMR_CTRL_LENGTH_SHIFT (5U)
33119 #define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
33120 #define TMR_CTRL_ONCE_MASK (0x40U)
33121 #define TMR_CTRL_ONCE_SHIFT (6U)
33129 #define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
33130 #define TMR_CTRL_SCS_MASK (0x180U)
33131 #define TMR_CTRL_SCS_SHIFT (7U)
33138 #define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
33139 #define TMR_CTRL_PCS_MASK (0x1E00U)
33140 #define TMR_CTRL_PCS_SHIFT (9U)
33159 #define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
33160 #define TMR_CTRL_CM_MASK (0xE000U)
33161 #define TMR_CTRL_CM_SHIFT (13U)
33175 #define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
33178 /* The count of TMR_CTRL */
33179 #define TMR_CTRL_COUNT (4U)
33180 
33183 #define TMR_SCTRL_OEN_MASK (0x1U)
33184 #define TMR_SCTRL_OEN_SHIFT (0U)
33190 #define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
33191 #define TMR_SCTRL_OPS_MASK (0x2U)
33192 #define TMR_SCTRL_OPS_SHIFT (1U)
33197 #define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
33198 #define TMR_SCTRL_FORCE_MASK (0x4U)
33199 #define TMR_SCTRL_FORCE_SHIFT (2U)
33202 #define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
33203 #define TMR_SCTRL_VAL_MASK (0x8U)
33204 #define TMR_SCTRL_VAL_SHIFT (3U)
33207 #define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
33208 #define TMR_SCTRL_EEOF_MASK (0x10U)
33209 #define TMR_SCTRL_EEOF_SHIFT (4U)
33212 #define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
33213 #define TMR_SCTRL_MSTR_MASK (0x20U)
33214 #define TMR_SCTRL_MSTR_SHIFT (5U)
33217 #define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
33218 #define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
33219 #define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
33226 #define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
33227 #define TMR_SCTRL_INPUT_MASK (0x100U)
33228 #define TMR_SCTRL_INPUT_SHIFT (8U)
33231 #define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
33232 #define TMR_SCTRL_IPS_MASK (0x200U)
33233 #define TMR_SCTRL_IPS_SHIFT (9U)
33236 #define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
33237 #define TMR_SCTRL_IEFIE_MASK (0x400U)
33238 #define TMR_SCTRL_IEFIE_SHIFT (10U)
33241 #define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
33242 #define TMR_SCTRL_IEF_MASK (0x800U)
33243 #define TMR_SCTRL_IEF_SHIFT (11U)
33246 #define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
33247 #define TMR_SCTRL_TOFIE_MASK (0x1000U)
33248 #define TMR_SCTRL_TOFIE_SHIFT (12U)
33251 #define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
33252 #define TMR_SCTRL_TOF_MASK (0x2000U)
33253 #define TMR_SCTRL_TOF_SHIFT (13U)
33256 #define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
33257 #define TMR_SCTRL_TCFIE_MASK (0x4000U)
33258 #define TMR_SCTRL_TCFIE_SHIFT (14U)
33261 #define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
33262 #define TMR_SCTRL_TCF_MASK (0x8000U)
33263 #define TMR_SCTRL_TCF_SHIFT (15U)
33266 #define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
33269 /* The count of TMR_SCTRL */
33270 #define TMR_SCTRL_COUNT (4U)
33271 
33274 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
33275 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
33276 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
33279 /* The count of TMR_CMPLD1 */
33280 #define TMR_CMPLD1_COUNT (4U)
33281 
33284 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
33285 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
33286 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
33289 /* The count of TMR_CMPLD2 */
33290 #define TMR_CMPLD2_COUNT (4U)
33291 
33294 #define TMR_CSCTRL_CL1_MASK (0x3U)
33295 #define TMR_CSCTRL_CL1_SHIFT (0U)
33302 #define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
33303 #define TMR_CSCTRL_CL2_MASK (0xCU)
33304 #define TMR_CSCTRL_CL2_SHIFT (2U)
33311 #define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
33312 #define TMR_CSCTRL_TCF1_MASK (0x10U)
33313 #define TMR_CSCTRL_TCF1_SHIFT (4U)
33316 #define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
33317 #define TMR_CSCTRL_TCF2_MASK (0x20U)
33318 #define TMR_CSCTRL_TCF2_SHIFT (5U)
33321 #define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
33322 #define TMR_CSCTRL_TCF1EN_MASK (0x40U)
33323 #define TMR_CSCTRL_TCF1EN_SHIFT (6U)
33326 #define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
33327 #define TMR_CSCTRL_TCF2EN_MASK (0x80U)
33328 #define TMR_CSCTRL_TCF2EN_SHIFT (7U)
33331 #define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
33332 #define TMR_CSCTRL_UP_MASK (0x200U)
33333 #define TMR_CSCTRL_UP_SHIFT (9U)
33338 #define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
33339 #define TMR_CSCTRL_TCI_MASK (0x400U)
33340 #define TMR_CSCTRL_TCI_SHIFT (10U)
33345 #define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
33346 #define TMR_CSCTRL_ROC_MASK (0x800U)
33347 #define TMR_CSCTRL_ROC_SHIFT (11U)
33352 #define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
33353 #define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
33354 #define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
33359 #define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
33360 #define TMR_CSCTRL_FAULT_MASK (0x2000U)
33361 #define TMR_CSCTRL_FAULT_SHIFT (13U)
33366 #define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
33367 #define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
33368 #define TMR_CSCTRL_DBG_EN_SHIFT (14U)
33375 #define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
33378 /* The count of TMR_CSCTRL */
33379 #define TMR_CSCTRL_COUNT (4U)
33380 
33383 #define TMR_FILT_FILT_PER_MASK (0xFFU)
33384 #define TMR_FILT_FILT_PER_SHIFT (0U)
33387 #define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
33388 #define TMR_FILT_FILT_CNT_MASK (0x700U)
33389 #define TMR_FILT_FILT_CNT_SHIFT (8U)
33392 #define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
33395 /* The count of TMR_FILT */
33396 #define TMR_FILT_COUNT (4U)
33397 
33400 #define TMR_DMA_IEFDE_MASK (0x1U)
33401 #define TMR_DMA_IEFDE_SHIFT (0U)
33404 #define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
33405 #define TMR_DMA_CMPLD1DE_MASK (0x2U)
33406 #define TMR_DMA_CMPLD1DE_SHIFT (1U)
33409 #define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
33410 #define TMR_DMA_CMPLD2DE_MASK (0x4U)
33411 #define TMR_DMA_CMPLD2DE_SHIFT (2U)
33414 #define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
33417 /* The count of TMR_DMA */
33418 #define TMR_DMA_COUNT (4U)
33419 
33422 #define TMR_ENBL_ENBL_MASK (0xFU)
33423 #define TMR_ENBL_ENBL_SHIFT (0U)
33428 #define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
33431 /* The count of TMR_ENBL */
33432 #define TMR_ENBL_COUNT (4U)
33433 
33434  /* end of group TMR_Register_Masks */
33438 
33439 
33440 /* TMR - Peripheral instance base addresses */
33442 #define TMR1_BASE (0x401DC000u)
33444 #define TMR1 ((TMR_Type *)TMR1_BASE)
33446 #define TMR2_BASE (0x401E0000u)
33448 #define TMR2 ((TMR_Type *)TMR2_BASE)
33450 #define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE }
33452 #define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2 }
33454 #define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn }
33455  /* end of group TMR_Peripheral_Access_Layer */
33459 
33460 
33461 /* ----------------------------------------------------------------------------
33462  -- TRNG Peripheral Access Layer
33463  ---------------------------------------------------------------------------- */
33464 
33471 typedef struct {
33472  __IO uint32_t MCTL;
33473  __IO uint32_t SCMISC;
33474  __IO uint32_t PKRRNG;
33475  union { /* offset: 0xC */
33476  __IO uint32_t PKRMAX;
33477  __I uint32_t PKRSQ;
33478  };
33479  __IO uint32_t SDCTL;
33480  union { /* offset: 0x14 */
33481  __IO uint32_t SBLIM;
33482  __I uint32_t TOTSAM;
33483  };
33484  __IO uint32_t FRQMIN;
33485  union { /* offset: 0x1C */
33486  __I uint32_t FRQCNT;
33487  __IO uint32_t FRQMAX;
33488  };
33489  union { /* offset: 0x20 */
33490  __I uint32_t SCMC;
33491  __IO uint32_t SCML;
33492  };
33493  union { /* offset: 0x24 */
33494  __I uint32_t SCR1C;
33495  __IO uint32_t SCR1L;
33496  };
33497  union { /* offset: 0x28 */
33498  __I uint32_t SCR2C;
33499  __IO uint32_t SCR2L;
33500  };
33501  union { /* offset: 0x2C */
33502  __I uint32_t SCR3C;
33503  __IO uint32_t SCR3L;
33504  };
33505  union { /* offset: 0x30 */
33506  __I uint32_t SCR4C;
33507  __IO uint32_t SCR4L;
33508  };
33509  union { /* offset: 0x34 */
33510  __I uint32_t SCR5C;
33511  __IO uint32_t SCR5L;
33512  };
33513  union { /* offset: 0x38 */
33514  __I uint32_t SCR6PC;
33515  __IO uint32_t SCR6PL;
33516  };
33517  __I uint32_t STATUS;
33518  __I uint32_t ENT[16];
33519  __I uint32_t PKRCNT10;
33520  __I uint32_t PKRCNT32;
33521  __I uint32_t PKRCNT54;
33522  __I uint32_t PKRCNT76;
33523  __I uint32_t PKRCNT98;
33524  __I uint32_t PKRCNTBA;
33525  __I uint32_t PKRCNTDC;
33526  __I uint32_t PKRCNTFE;
33527  __IO uint32_t SEC_CFG;
33528  __IO uint32_t INT_CTRL;
33529  __IO uint32_t INT_MASK;
33530  __I uint32_t INT_STATUS;
33531  uint8_t RESERVED_0[64];
33532  __I uint32_t VID1;
33533  __I uint32_t VID2;
33534 } TRNG_Type;
33535 
33536 /* ----------------------------------------------------------------------------
33537  -- TRNG Register Masks
33538  ---------------------------------------------------------------------------- */
33539 
33547 #define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
33548 #define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
33555 #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
33556 #define TRNG_MCTL_OSC_DIV_MASK (0xCU)
33557 #define TRNG_MCTL_OSC_DIV_SHIFT (2U)
33564 #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
33565 #define TRNG_MCTL_UNUSED4_MASK (0x10U)
33566 #define TRNG_MCTL_UNUSED4_SHIFT (4U)
33567 #define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
33568 #define TRNG_MCTL_TRNG_ACC_MASK (0x20U)
33569 #define TRNG_MCTL_TRNG_ACC_SHIFT (5U)
33570 #define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
33571 #define TRNG_MCTL_RST_DEF_MASK (0x40U)
33572 #define TRNG_MCTL_RST_DEF_SHIFT (6U)
33573 #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
33574 #define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
33575 #define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
33576 #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
33577 #define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
33578 #define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
33579 #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
33580 #define TRNG_MCTL_FCT_VAL_MASK (0x200U)
33581 #define TRNG_MCTL_FCT_VAL_SHIFT (9U)
33582 #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
33583 #define TRNG_MCTL_ENT_VAL_MASK (0x400U)
33584 #define TRNG_MCTL_ENT_VAL_SHIFT (10U)
33585 #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
33586 #define TRNG_MCTL_TST_OUT_MASK (0x800U)
33587 #define TRNG_MCTL_TST_OUT_SHIFT (11U)
33588 #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
33589 #define TRNG_MCTL_ERR_MASK (0x1000U)
33590 #define TRNG_MCTL_ERR_SHIFT (12U)
33591 #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
33592 #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
33593 #define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
33594 #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
33595 #define TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
33596 #define TRNG_MCTL_LRUN_CONT_SHIFT (14U)
33597 #define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
33598 #define TRNG_MCTL_PRGM_MASK (0x10000U)
33599 #define TRNG_MCTL_PRGM_SHIFT (16U)
33600 #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
33605 #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
33606 #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
33607 #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
33608 #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
33609 #define TRNG_SCMISC_RTY_CT_SHIFT (16U)
33610 #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
33615 #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
33616 #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
33617 #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
33622 #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
33623 #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
33626 #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
33631 #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
33632 #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
33635 #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
33640 #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
33641 #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
33642 #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
33643 #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
33644 #define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
33645 #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
33650 #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
33651 #define TRNG_SBLIM_SB_LIM_SHIFT (0U)
33652 #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
33657 #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
33658 #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
33659 #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
33664 #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
33665 #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
33666 #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
33671 #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
33672 #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
33673 #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
33678 #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
33679 #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
33680 #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
33685 #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
33686 #define TRNG_SCMC_MONO_CT_SHIFT (0U)
33687 #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
33692 #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
33693 #define TRNG_SCML_MONO_MAX_SHIFT (0U)
33694 #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
33695 #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
33696 #define TRNG_SCML_MONO_RNG_SHIFT (16U)
33697 #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
33702 #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
33703 #define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
33704 #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
33705 #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
33706 #define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
33707 #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
33712 #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
33713 #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
33714 #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
33715 #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
33716 #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
33717 #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
33722 #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
33723 #define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
33724 #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
33725 #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
33726 #define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
33727 #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
33732 #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
33733 #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
33734 #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
33735 #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
33736 #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
33737 #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
33742 #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
33743 #define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
33744 #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
33745 #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
33746 #define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
33747 #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
33752 #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
33753 #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
33754 #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
33755 #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
33756 #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
33757 #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
33762 #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
33763 #define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
33764 #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
33765 #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
33766 #define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
33767 #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
33772 #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
33773 #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
33774 #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
33775 #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
33776 #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
33777 #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
33782 #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
33783 #define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
33784 #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
33785 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
33786 #define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
33787 #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
33792 #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
33793 #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
33794 #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
33795 #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
33796 #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
33797 #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
33802 #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
33803 #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
33804 #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
33805 #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
33806 #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
33807 #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
33812 #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
33813 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
33814 #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
33815 #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
33816 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
33817 #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
33822 #define TRNG_STATUS_TF1BR0_MASK (0x1U)
33823 #define TRNG_STATUS_TF1BR0_SHIFT (0U)
33824 #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
33825 #define TRNG_STATUS_TF1BR1_MASK (0x2U)
33826 #define TRNG_STATUS_TF1BR1_SHIFT (1U)
33827 #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
33828 #define TRNG_STATUS_TF2BR0_MASK (0x4U)
33829 #define TRNG_STATUS_TF2BR0_SHIFT (2U)
33830 #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
33831 #define TRNG_STATUS_TF2BR1_MASK (0x8U)
33832 #define TRNG_STATUS_TF2BR1_SHIFT (3U)
33833 #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
33834 #define TRNG_STATUS_TF3BR0_MASK (0x10U)
33835 #define TRNG_STATUS_TF3BR0_SHIFT (4U)
33836 #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
33837 #define TRNG_STATUS_TF3BR1_MASK (0x20U)
33838 #define TRNG_STATUS_TF3BR1_SHIFT (5U)
33839 #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
33840 #define TRNG_STATUS_TF4BR0_MASK (0x40U)
33841 #define TRNG_STATUS_TF4BR0_SHIFT (6U)
33842 #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
33843 #define TRNG_STATUS_TF4BR1_MASK (0x80U)
33844 #define TRNG_STATUS_TF4BR1_SHIFT (7U)
33845 #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
33846 #define TRNG_STATUS_TF5BR0_MASK (0x100U)
33847 #define TRNG_STATUS_TF5BR0_SHIFT (8U)
33848 #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
33849 #define TRNG_STATUS_TF5BR1_MASK (0x200U)
33850 #define TRNG_STATUS_TF5BR1_SHIFT (9U)
33851 #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
33852 #define TRNG_STATUS_TF6PBR0_MASK (0x400U)
33853 #define TRNG_STATUS_TF6PBR0_SHIFT (10U)
33854 #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
33855 #define TRNG_STATUS_TF6PBR1_MASK (0x800U)
33856 #define TRNG_STATUS_TF6PBR1_SHIFT (11U)
33857 #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
33858 #define TRNG_STATUS_TFSB_MASK (0x1000U)
33859 #define TRNG_STATUS_TFSB_SHIFT (12U)
33860 #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
33861 #define TRNG_STATUS_TFLR_MASK (0x2000U)
33862 #define TRNG_STATUS_TFLR_SHIFT (13U)
33863 #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
33864 #define TRNG_STATUS_TFP_MASK (0x4000U)
33865 #define TRNG_STATUS_TFP_SHIFT (14U)
33866 #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
33867 #define TRNG_STATUS_TFMB_MASK (0x8000U)
33868 #define TRNG_STATUS_TFMB_SHIFT (15U)
33869 #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
33870 #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
33871 #define TRNG_STATUS_RETRY_CT_SHIFT (16U)
33872 #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
33877 #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
33878 #define TRNG_ENT_ENT_SHIFT (0U)
33879 #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
33882 /* The count of TRNG_ENT */
33883 #define TRNG_ENT_COUNT (16U)
33884 
33887 #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
33888 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
33889 #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
33890 #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
33891 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
33892 #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
33897 #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
33898 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
33899 #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
33900 #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
33901 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
33902 #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
33907 #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
33908 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
33909 #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
33910 #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
33911 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
33912 #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
33917 #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
33918 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
33919 #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
33920 #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
33921 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
33922 #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
33927 #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
33928 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
33929 #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
33930 #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
33931 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
33932 #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
33937 #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
33938 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
33939 #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
33940 #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
33941 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
33942 #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
33947 #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
33948 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
33949 #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
33950 #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
33951 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
33952 #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
33957 #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
33958 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
33959 #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
33960 #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
33961 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
33962 #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
33967 #define TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
33968 #define TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
33969 #define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
33970 #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
33971 #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
33976 #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
33977 #define TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
33978 #define TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
33979 #define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
33984 #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
33985 #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
33990 #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
33991 #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
33992 #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
33997 #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
33998 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
33999 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
34004 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
34005 #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
34006 #define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
34007 #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
34012 #define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
34013 #define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
34018 #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
34019 #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
34020 #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
34025 #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
34026 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
34027 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
34032 #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
34037 #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
34038 #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
34043 #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
34044 #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
34045 #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
34050 #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
34051 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
34052 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
34057 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
34062 #define TRNG_VID1_MIN_REV_MASK (0xFFU)
34063 #define TRNG_VID1_MIN_REV_SHIFT (0U)
34067 #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
34068 #define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
34069 #define TRNG_VID1_MAJ_REV_SHIFT (8U)
34073 #define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
34074 #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
34075 #define TRNG_VID1_IP_ID_SHIFT (16U)
34079 #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
34084 #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
34085 #define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
34089 #define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
34090 #define TRNG_VID2_ECO_REV_MASK (0xFF00U)
34091 #define TRNG_VID2_ECO_REV_SHIFT (8U)
34095 #define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
34096 #define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
34097 #define TRNG_VID2_INTG_OPT_SHIFT (16U)
34101 #define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
34102 #define TRNG_VID2_ERA_MASK (0xFF000000U)
34103 #define TRNG_VID2_ERA_SHIFT (24U)
34107 #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) /* end of group TRNG_Register_Masks */
34114 
34115 
34116 /* TRNG - Peripheral instance base addresses */
34118 #define TRNG_BASE (0x400CC000u)
34120 #define TRNG ((TRNG_Type *)TRNG_BASE)
34122 #define TRNG_BASE_ADDRS { TRNG_BASE }
34124 #define TRNG_BASE_PTRS { TRNG }
34126 #define TRNG_IRQS { TRNG_IRQn }
34127  /* end of group TRNG_Peripheral_Access_Layer */
34131 
34132 
34133 /* ----------------------------------------------------------------------------
34134  -- USB Peripheral Access Layer
34135  ---------------------------------------------------------------------------- */
34136 
34143 typedef struct {
34144  __I uint32_t ID;
34145  __I uint32_t HWGENERAL;
34146  __I uint32_t HWHOST;
34147  __I uint32_t HWDEVICE;
34148  __I uint32_t HWTXBUF;
34149  __I uint32_t HWRXBUF;
34150  uint8_t RESERVED_0[104];
34151  __IO uint32_t GPTIMER0LD;
34152  __IO uint32_t GPTIMER0CTRL;
34153  __IO uint32_t GPTIMER1LD;
34154  __IO uint32_t GPTIMER1CTRL;
34155  __IO uint32_t SBUSCFG;
34156  uint8_t RESERVED_1[108];
34157  __I uint8_t CAPLENGTH;
34158  uint8_t RESERVED_2[1];
34159  __I uint16_t HCIVERSION;
34160  __I uint32_t HCSPARAMS;
34161  __I uint32_t HCCPARAMS;
34162  uint8_t RESERVED_3[20];
34163  __I uint16_t DCIVERSION;
34164  uint8_t RESERVED_4[2];
34165  __I uint32_t DCCPARAMS;
34166  uint8_t RESERVED_5[24];
34167  __IO uint32_t USBCMD;
34168  __IO uint32_t USBSTS;
34169  __IO uint32_t USBINTR;
34170  __IO uint32_t FRINDEX;
34171  uint8_t RESERVED_6[4];
34172  union { /* offset: 0x154 */
34173  __IO uint32_t DEVICEADDR;
34174  __IO uint32_t PERIODICLISTBASE;
34175  };
34176  union { /* offset: 0x158 */
34177  __IO uint32_t ASYNCLISTADDR;
34178  __IO uint32_t ENDPTLISTADDR;
34179  };
34180  uint8_t RESERVED_7[4];
34181  __IO uint32_t BURSTSIZE;
34182  __IO uint32_t TXFILLTUNING;
34183  uint8_t RESERVED_8[16];
34184  __IO uint32_t ENDPTNAK;
34185  __IO uint32_t ENDPTNAKEN;
34186  __I uint32_t CONFIGFLAG;
34187  __IO uint32_t PORTSC1;
34188  uint8_t RESERVED_9[28];
34189  __IO uint32_t OTGSC;
34190  __IO uint32_t USBMODE;
34191  __IO uint32_t ENDPTSETUPSTAT;
34192  __IO uint32_t ENDPTPRIME;
34193  __IO uint32_t ENDPTFLUSH;
34194  __I uint32_t ENDPTSTAT;
34195  __IO uint32_t ENDPTCOMPLETE;
34196  __IO uint32_t ENDPTCTRL0;
34197  __IO uint32_t ENDPTCTRL[7];
34198 } USB_Type;
34199 
34200 /* ----------------------------------------------------------------------------
34201  -- USB Register Masks
34202  ---------------------------------------------------------------------------- */
34203 
34211 #define USB_ID_ID_MASK (0x3FU)
34212 #define USB_ID_ID_SHIFT (0U)
34213 #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
34214 #define USB_ID_NID_MASK (0x3F00U)
34215 #define USB_ID_NID_SHIFT (8U)
34216 #define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
34217 #define USB_ID_REVISION_MASK (0xFF0000U)
34218 #define USB_ID_REVISION_SHIFT (16U)
34219 #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
34224 #define USB_HWGENERAL_PHYW_MASK (0x30U)
34225 #define USB_HWGENERAL_PHYW_SHIFT (4U)
34232 #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
34233 #define USB_HWGENERAL_PHYM_MASK (0x1C0U)
34234 #define USB_HWGENERAL_PHYM_SHIFT (6U)
34245 #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
34246 #define USB_HWGENERAL_SM_MASK (0x600U)
34247 #define USB_HWGENERAL_SM_SHIFT (9U)
34254 #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
34259 #define USB_HWHOST_HC_MASK (0x1U)
34260 #define USB_HWHOST_HC_SHIFT (0U)
34265 #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
34266 #define USB_HWHOST_NPORT_MASK (0xEU)
34267 #define USB_HWHOST_NPORT_SHIFT (1U)
34268 #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
34273 #define USB_HWDEVICE_DC_MASK (0x1U)
34274 #define USB_HWDEVICE_DC_SHIFT (0U)
34279 #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
34280 #define USB_HWDEVICE_DEVEP_MASK (0x3EU)
34281 #define USB_HWDEVICE_DEVEP_SHIFT (1U)
34282 #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
34287 #define USB_HWTXBUF_TXBURST_MASK (0xFFU)
34288 #define USB_HWTXBUF_TXBURST_SHIFT (0U)
34289 #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
34290 #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
34291 #define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
34292 #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
34297 #define USB_HWRXBUF_RXBURST_MASK (0xFFU)
34298 #define USB_HWRXBUF_RXBURST_SHIFT (0U)
34299 #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
34300 #define USB_HWRXBUF_RXADD_MASK (0xFF00U)
34301 #define USB_HWRXBUF_RXADD_SHIFT (8U)
34302 #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
34307 #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
34308 #define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
34309 #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
34314 #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
34315 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
34316 #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
34317 #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
34318 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
34323 #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
34324 #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
34325 #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
34330 #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
34331 #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
34332 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
34337 #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
34342 #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
34343 #define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
34344 #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
34349 #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
34350 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
34351 #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
34352 #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
34353 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
34358 #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
34359 #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
34360 #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
34365 #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
34366 #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
34367 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
34372 #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
34377 #define USB_SBUSCFG_AHBBRST_MASK (0x7U)
34378 #define USB_SBUSCFG_AHBBRST_SHIFT (0U)
34389 #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
34394 #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
34395 #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
34396 #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
34401 #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
34402 #define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
34403 #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
34408 #define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
34409 #define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
34410 #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
34411 #define USB_HCSPARAMS_PPC_MASK (0x10U)
34412 #define USB_HCSPARAMS_PPC_SHIFT (4U)
34413 #define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
34414 #define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
34415 #define USB_HCSPARAMS_N_PCC_SHIFT (8U)
34416 #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
34417 #define USB_HCSPARAMS_N_CC_MASK (0xF000U)
34418 #define USB_HCSPARAMS_N_CC_SHIFT (12U)
34423 #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
34424 #define USB_HCSPARAMS_PI_MASK (0x10000U)
34425 #define USB_HCSPARAMS_PI_SHIFT (16U)
34426 #define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
34427 #define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
34428 #define USB_HCSPARAMS_N_PTT_SHIFT (20U)
34429 #define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
34430 #define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
34431 #define USB_HCSPARAMS_N_TT_SHIFT (24U)
34432 #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
34437 #define USB_HCCPARAMS_ADC_MASK (0x1U)
34438 #define USB_HCCPARAMS_ADC_SHIFT (0U)
34439 #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
34440 #define USB_HCCPARAMS_PFL_MASK (0x2U)
34441 #define USB_HCCPARAMS_PFL_SHIFT (1U)
34442 #define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
34443 #define USB_HCCPARAMS_ASP_MASK (0x4U)
34444 #define USB_HCCPARAMS_ASP_SHIFT (2U)
34445 #define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
34446 #define USB_HCCPARAMS_IST_MASK (0xF0U)
34447 #define USB_HCCPARAMS_IST_SHIFT (4U)
34448 #define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
34449 #define USB_HCCPARAMS_EECP_MASK (0xFF00U)
34450 #define USB_HCCPARAMS_EECP_SHIFT (8U)
34451 #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
34456 #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
34457 #define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
34458 #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
34463 #define USB_DCCPARAMS_DEN_MASK (0x1FU)
34464 #define USB_DCCPARAMS_DEN_SHIFT (0U)
34465 #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
34466 #define USB_DCCPARAMS_DC_MASK (0x80U)
34467 #define USB_DCCPARAMS_DC_SHIFT (7U)
34468 #define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
34469 #define USB_DCCPARAMS_HC_MASK (0x100U)
34470 #define USB_DCCPARAMS_HC_SHIFT (8U)
34471 #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
34476 #define USB_USBCMD_RS_MASK (0x1U)
34477 #define USB_USBCMD_RS_SHIFT (0U)
34478 #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
34479 #define USB_USBCMD_RST_MASK (0x2U)
34480 #define USB_USBCMD_RST_SHIFT (1U)
34481 #define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
34482 #define USB_USBCMD_FS_1_MASK (0xCU)
34483 #define USB_USBCMD_FS_1_SHIFT (2U)
34484 #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
34485 #define USB_USBCMD_PSE_MASK (0x10U)
34486 #define USB_USBCMD_PSE_SHIFT (4U)
34491 #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
34492 #define USB_USBCMD_ASE_MASK (0x20U)
34493 #define USB_USBCMD_ASE_SHIFT (5U)
34498 #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
34499 #define USB_USBCMD_IAA_MASK (0x40U)
34500 #define USB_USBCMD_IAA_SHIFT (6U)
34501 #define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
34502 #define USB_USBCMD_ASP_MASK (0x300U)
34503 #define USB_USBCMD_ASP_SHIFT (8U)
34504 #define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
34505 #define USB_USBCMD_ASPE_MASK (0x800U)
34506 #define USB_USBCMD_ASPE_SHIFT (11U)
34507 #define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
34508 #define USB_USBCMD_SUTW_MASK (0x2000U)
34509 #define USB_USBCMD_SUTW_SHIFT (13U)
34510 #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
34511 #define USB_USBCMD_ATDTW_MASK (0x4000U)
34512 #define USB_USBCMD_ATDTW_SHIFT (14U)
34513 #define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
34514 #define USB_USBCMD_FS_2_MASK (0x8000U)
34515 #define USB_USBCMD_FS_2_SHIFT (15U)
34520 #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
34521 #define USB_USBCMD_ITC_MASK (0xFF0000U)
34522 #define USB_USBCMD_ITC_SHIFT (16U)
34533 #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
34538 #define USB_USBSTS_UI_MASK (0x1U)
34539 #define USB_USBSTS_UI_SHIFT (0U)
34540 #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
34541 #define USB_USBSTS_UEI_MASK (0x2U)
34542 #define USB_USBSTS_UEI_SHIFT (1U)
34543 #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
34544 #define USB_USBSTS_PCI_MASK (0x4U)
34545 #define USB_USBSTS_PCI_SHIFT (2U)
34546 #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
34547 #define USB_USBSTS_FRI_MASK (0x8U)
34548 #define USB_USBSTS_FRI_SHIFT (3U)
34549 #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
34550 #define USB_USBSTS_SEI_MASK (0x10U)
34551 #define USB_USBSTS_SEI_SHIFT (4U)
34552 #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
34553 #define USB_USBSTS_AAI_MASK (0x20U)
34554 #define USB_USBSTS_AAI_SHIFT (5U)
34555 #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
34556 #define USB_USBSTS_URI_MASK (0x40U)
34557 #define USB_USBSTS_URI_SHIFT (6U)
34558 #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
34559 #define USB_USBSTS_SRI_MASK (0x80U)
34560 #define USB_USBSTS_SRI_SHIFT (7U)
34561 #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
34562 #define USB_USBSTS_SLI_MASK (0x100U)
34563 #define USB_USBSTS_SLI_SHIFT (8U)
34564 #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
34565 #define USB_USBSTS_ULPII_MASK (0x400U)
34566 #define USB_USBSTS_ULPII_SHIFT (10U)
34567 #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
34568 #define USB_USBSTS_HCH_MASK (0x1000U)
34569 #define USB_USBSTS_HCH_SHIFT (12U)
34570 #define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
34571 #define USB_USBSTS_RCL_MASK (0x2000U)
34572 #define USB_USBSTS_RCL_SHIFT (13U)
34573 #define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
34574 #define USB_USBSTS_PS_MASK (0x4000U)
34575 #define USB_USBSTS_PS_SHIFT (14U)
34576 #define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
34577 #define USB_USBSTS_AS_MASK (0x8000U)
34578 #define USB_USBSTS_AS_SHIFT (15U)
34579 #define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
34580 #define USB_USBSTS_NAKI_MASK (0x10000U)
34581 #define USB_USBSTS_NAKI_SHIFT (16U)
34582 #define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
34583 #define USB_USBSTS_TI0_MASK (0x1000000U)
34584 #define USB_USBSTS_TI0_SHIFT (24U)
34585 #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
34586 #define USB_USBSTS_TI1_MASK (0x2000000U)
34587 #define USB_USBSTS_TI1_SHIFT (25U)
34588 #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
34593 #define USB_USBINTR_UE_MASK (0x1U)
34594 #define USB_USBINTR_UE_SHIFT (0U)
34595 #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
34596 #define USB_USBINTR_UEE_MASK (0x2U)
34597 #define USB_USBINTR_UEE_SHIFT (1U)
34598 #define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
34599 #define USB_USBINTR_PCE_MASK (0x4U)
34600 #define USB_USBINTR_PCE_SHIFT (2U)
34601 #define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
34602 #define USB_USBINTR_FRE_MASK (0x8U)
34603 #define USB_USBINTR_FRE_SHIFT (3U)
34604 #define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
34605 #define USB_USBINTR_SEE_MASK (0x10U)
34606 #define USB_USBINTR_SEE_SHIFT (4U)
34607 #define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
34608 #define USB_USBINTR_AAE_MASK (0x20U)
34609 #define USB_USBINTR_AAE_SHIFT (5U)
34610 #define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
34611 #define USB_USBINTR_URE_MASK (0x40U)
34612 #define USB_USBINTR_URE_SHIFT (6U)
34613 #define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
34614 #define USB_USBINTR_SRE_MASK (0x80U)
34615 #define USB_USBINTR_SRE_SHIFT (7U)
34616 #define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
34617 #define USB_USBINTR_SLE_MASK (0x100U)
34618 #define USB_USBINTR_SLE_SHIFT (8U)
34619 #define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
34620 #define USB_USBINTR_ULPIE_MASK (0x400U)
34621 #define USB_USBINTR_ULPIE_SHIFT (10U)
34622 #define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
34623 #define USB_USBINTR_NAKE_MASK (0x10000U)
34624 #define USB_USBINTR_NAKE_SHIFT (16U)
34625 #define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
34626 #define USB_USBINTR_UAIE_MASK (0x40000U)
34627 #define USB_USBINTR_UAIE_SHIFT (18U)
34628 #define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
34629 #define USB_USBINTR_UPIE_MASK (0x80000U)
34630 #define USB_USBINTR_UPIE_SHIFT (19U)
34631 #define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
34632 #define USB_USBINTR_TIE0_MASK (0x1000000U)
34633 #define USB_USBINTR_TIE0_SHIFT (24U)
34634 #define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
34635 #define USB_USBINTR_TIE1_MASK (0x2000000U)
34636 #define USB_USBINTR_TIE1_SHIFT (25U)
34637 #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
34642 #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
34643 #define USB_FRINDEX_FRINDEX_SHIFT (0U)
34654 #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
34659 #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
34660 #define USB_DEVICEADDR_USBADRA_SHIFT (24U)
34661 #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
34662 #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
34663 #define USB_DEVICEADDR_USBADR_SHIFT (25U)
34664 #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
34669 #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
34670 #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
34671 #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
34676 #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
34677 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
34678 #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
34683 #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
34684 #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
34685 #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
34690 #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
34691 #define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
34692 #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
34693 #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
34694 #define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
34695 #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
34700 #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
34701 #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
34702 #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
34703 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
34704 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
34705 #define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
34706 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
34707 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
34708 #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
34713 #define USB_ENDPTNAK_EPRN_MASK (0xFFU)
34714 #define USB_ENDPTNAK_EPRN_SHIFT (0U)
34715 #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
34716 #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
34717 #define USB_ENDPTNAK_EPTN_SHIFT (16U)
34718 #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
34723 #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
34724 #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
34725 #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
34726 #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
34727 #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
34728 #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
34733 #define USB_CONFIGFLAG_CF_MASK (0x1U)
34734 #define USB_CONFIGFLAG_CF_SHIFT (0U)
34739 #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
34744 #define USB_PORTSC1_CCS_MASK (0x1U)
34745 #define USB_PORTSC1_CCS_SHIFT (0U)
34746 #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
34747 #define USB_PORTSC1_CSC_MASK (0x2U)
34748 #define USB_PORTSC1_CSC_SHIFT (1U)
34749 #define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
34750 #define USB_PORTSC1_PE_MASK (0x4U)
34751 #define USB_PORTSC1_PE_SHIFT (2U)
34752 #define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
34753 #define USB_PORTSC1_PEC_MASK (0x8U)
34754 #define USB_PORTSC1_PEC_SHIFT (3U)
34755 #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
34756 #define USB_PORTSC1_OCA_MASK (0x10U)
34757 #define USB_PORTSC1_OCA_SHIFT (4U)
34762 #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
34763 #define USB_PORTSC1_OCC_MASK (0x20U)
34764 #define USB_PORTSC1_OCC_SHIFT (5U)
34765 #define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
34766 #define USB_PORTSC1_FPR_MASK (0x40U)
34767 #define USB_PORTSC1_FPR_SHIFT (6U)
34768 #define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
34769 #define USB_PORTSC1_SUSP_MASK (0x80U)
34770 #define USB_PORTSC1_SUSP_SHIFT (7U)
34771 #define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
34772 #define USB_PORTSC1_PR_MASK (0x100U)
34773 #define USB_PORTSC1_PR_SHIFT (8U)
34774 #define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
34775 #define USB_PORTSC1_HSP_MASK (0x200U)
34776 #define USB_PORTSC1_HSP_SHIFT (9U)
34777 #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
34778 #define USB_PORTSC1_LS_MASK (0xC00U)
34779 #define USB_PORTSC1_LS_SHIFT (10U)
34786 #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
34787 #define USB_PORTSC1_PP_MASK (0x1000U)
34788 #define USB_PORTSC1_PP_SHIFT (12U)
34789 #define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
34790 #define USB_PORTSC1_PO_MASK (0x2000U)
34791 #define USB_PORTSC1_PO_SHIFT (13U)
34792 #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
34793 #define USB_PORTSC1_PIC_MASK (0xC000U)
34794 #define USB_PORTSC1_PIC_SHIFT (14U)
34801 #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
34802 #define USB_PORTSC1_PTC_MASK (0xF0000U)
34803 #define USB_PORTSC1_PTC_SHIFT (16U)
34814 #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
34815 #define USB_PORTSC1_WKCN_MASK (0x100000U)
34816 #define USB_PORTSC1_WKCN_SHIFT (20U)
34817 #define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
34818 #define USB_PORTSC1_WKDC_MASK (0x200000U)
34819 #define USB_PORTSC1_WKDC_SHIFT (21U)
34820 #define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
34821 #define USB_PORTSC1_WKOC_MASK (0x400000U)
34822 #define USB_PORTSC1_WKOC_SHIFT (22U)
34823 #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
34824 #define USB_PORTSC1_PHCD_MASK (0x800000U)
34825 #define USB_PORTSC1_PHCD_SHIFT (23U)
34830 #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
34831 #define USB_PORTSC1_PFSC_MASK (0x1000000U)
34832 #define USB_PORTSC1_PFSC_SHIFT (24U)
34837 #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
34838 #define USB_PORTSC1_PTS_2_MASK (0x2000000U)
34839 #define USB_PORTSC1_PTS_2_SHIFT (25U)
34840 #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
34841 #define USB_PORTSC1_PSPD_MASK (0xC000000U)
34842 #define USB_PORTSC1_PSPD_SHIFT (26U)
34849 #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
34850 #define USB_PORTSC1_PTW_MASK (0x10000000U)
34851 #define USB_PORTSC1_PTW_SHIFT (28U)
34856 #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
34857 #define USB_PORTSC1_STS_MASK (0x20000000U)
34858 #define USB_PORTSC1_STS_SHIFT (29U)
34859 #define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
34860 #define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
34861 #define USB_PORTSC1_PTS_1_SHIFT (30U)
34862 #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
34867 #define USB_OTGSC_VD_MASK (0x1U)
34868 #define USB_OTGSC_VD_SHIFT (0U)
34869 #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
34870 #define USB_OTGSC_VC_MASK (0x2U)
34871 #define USB_OTGSC_VC_SHIFT (1U)
34872 #define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
34873 #define USB_OTGSC_OT_MASK (0x8U)
34874 #define USB_OTGSC_OT_SHIFT (3U)
34875 #define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
34876 #define USB_OTGSC_DP_MASK (0x10U)
34877 #define USB_OTGSC_DP_SHIFT (4U)
34878 #define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
34879 #define USB_OTGSC_IDPU_MASK (0x20U)
34880 #define USB_OTGSC_IDPU_SHIFT (5U)
34881 #define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
34882 #define USB_OTGSC_ID_MASK (0x100U)
34883 #define USB_OTGSC_ID_SHIFT (8U)
34884 #define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
34885 #define USB_OTGSC_AVV_MASK (0x200U)
34886 #define USB_OTGSC_AVV_SHIFT (9U)
34887 #define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
34888 #define USB_OTGSC_ASV_MASK (0x400U)
34889 #define USB_OTGSC_ASV_SHIFT (10U)
34890 #define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
34891 #define USB_OTGSC_BSV_MASK (0x800U)
34892 #define USB_OTGSC_BSV_SHIFT (11U)
34893 #define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
34894 #define USB_OTGSC_BSE_MASK (0x1000U)
34895 #define USB_OTGSC_BSE_SHIFT (12U)
34896 #define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
34897 #define USB_OTGSC_TOG_1MS_MASK (0x2000U)
34898 #define USB_OTGSC_TOG_1MS_SHIFT (13U)
34899 #define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
34900 #define USB_OTGSC_DPS_MASK (0x4000U)
34901 #define USB_OTGSC_DPS_SHIFT (14U)
34902 #define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
34903 #define USB_OTGSC_IDIS_MASK (0x10000U)
34904 #define USB_OTGSC_IDIS_SHIFT (16U)
34905 #define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
34906 #define USB_OTGSC_AVVIS_MASK (0x20000U)
34907 #define USB_OTGSC_AVVIS_SHIFT (17U)
34908 #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
34909 #define USB_OTGSC_ASVIS_MASK (0x40000U)
34910 #define USB_OTGSC_ASVIS_SHIFT (18U)
34911 #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
34912 #define USB_OTGSC_BSVIS_MASK (0x80000U)
34913 #define USB_OTGSC_BSVIS_SHIFT (19U)
34914 #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
34915 #define USB_OTGSC_BSEIS_MASK (0x100000U)
34916 #define USB_OTGSC_BSEIS_SHIFT (20U)
34917 #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
34918 #define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
34919 #define USB_OTGSC_STATUS_1MS_SHIFT (21U)
34920 #define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
34921 #define USB_OTGSC_DPIS_MASK (0x400000U)
34922 #define USB_OTGSC_DPIS_SHIFT (22U)
34923 #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
34924 #define USB_OTGSC_IDIE_MASK (0x1000000U)
34925 #define USB_OTGSC_IDIE_SHIFT (24U)
34926 #define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
34927 #define USB_OTGSC_AVVIE_MASK (0x2000000U)
34928 #define USB_OTGSC_AVVIE_SHIFT (25U)
34929 #define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
34930 #define USB_OTGSC_ASVIE_MASK (0x4000000U)
34931 #define USB_OTGSC_ASVIE_SHIFT (26U)
34932 #define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
34933 #define USB_OTGSC_BSVIE_MASK (0x8000000U)
34934 #define USB_OTGSC_BSVIE_SHIFT (27U)
34935 #define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
34936 #define USB_OTGSC_BSEIE_MASK (0x10000000U)
34937 #define USB_OTGSC_BSEIE_SHIFT (28U)
34938 #define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
34939 #define USB_OTGSC_EN_1MS_MASK (0x20000000U)
34940 #define USB_OTGSC_EN_1MS_SHIFT (29U)
34941 #define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
34942 #define USB_OTGSC_DPIE_MASK (0x40000000U)
34943 #define USB_OTGSC_DPIE_SHIFT (30U)
34944 #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
34949 #define USB_USBMODE_CM_MASK (0x3U)
34950 #define USB_USBMODE_CM_SHIFT (0U)
34957 #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
34958 #define USB_USBMODE_ES_MASK (0x4U)
34959 #define USB_USBMODE_ES_SHIFT (2U)
34964 #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
34965 #define USB_USBMODE_SLOM_MASK (0x8U)
34966 #define USB_USBMODE_SLOM_SHIFT (3U)
34971 #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
34972 #define USB_USBMODE_SDIS_MASK (0x10U)
34973 #define USB_USBMODE_SDIS_SHIFT (4U)
34974 #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
34979 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
34980 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
34981 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
34986 #define USB_ENDPTPRIME_PERB_MASK (0xFFU)
34987 #define USB_ENDPTPRIME_PERB_SHIFT (0U)
34988 #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
34989 #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
34990 #define USB_ENDPTPRIME_PETB_SHIFT (16U)
34991 #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
34996 #define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
34997 #define USB_ENDPTFLUSH_FERB_SHIFT (0U)
34998 #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
34999 #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
35000 #define USB_ENDPTFLUSH_FETB_SHIFT (16U)
35001 #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
35006 #define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
35007 #define USB_ENDPTSTAT_ERBR_SHIFT (0U)
35008 #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
35009 #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
35010 #define USB_ENDPTSTAT_ETBR_SHIFT (16U)
35011 #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
35016 #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
35017 #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
35018 #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
35019 #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
35020 #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
35021 #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
35026 #define USB_ENDPTCTRL0_RXS_MASK (0x1U)
35027 #define USB_ENDPTCTRL0_RXS_SHIFT (0U)
35028 #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
35029 #define USB_ENDPTCTRL0_RXT_MASK (0xCU)
35030 #define USB_ENDPTCTRL0_RXT_SHIFT (2U)
35031 #define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
35032 #define USB_ENDPTCTRL0_RXE_MASK (0x80U)
35033 #define USB_ENDPTCTRL0_RXE_SHIFT (7U)
35034 #define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
35035 #define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
35036 #define USB_ENDPTCTRL0_TXS_SHIFT (16U)
35037 #define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
35038 #define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
35039 #define USB_ENDPTCTRL0_TXT_SHIFT (18U)
35040 #define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
35041 #define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
35042 #define USB_ENDPTCTRL0_TXE_SHIFT (23U)
35043 #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
35048 #define USB_ENDPTCTRL_RXS_MASK (0x1U)
35049 #define USB_ENDPTCTRL_RXS_SHIFT (0U)
35050 #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
35051 #define USB_ENDPTCTRL_RXD_MASK (0x2U)
35052 #define USB_ENDPTCTRL_RXD_SHIFT (1U)
35053 #define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
35054 #define USB_ENDPTCTRL_RXT_MASK (0xCU)
35055 #define USB_ENDPTCTRL_RXT_SHIFT (2U)
35056 #define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
35057 #define USB_ENDPTCTRL_RXI_MASK (0x20U)
35058 #define USB_ENDPTCTRL_RXI_SHIFT (5U)
35059 #define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
35060 #define USB_ENDPTCTRL_RXR_MASK (0x40U)
35061 #define USB_ENDPTCTRL_RXR_SHIFT (6U)
35062 #define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
35063 #define USB_ENDPTCTRL_RXE_MASK (0x80U)
35064 #define USB_ENDPTCTRL_RXE_SHIFT (7U)
35065 #define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
35066 #define USB_ENDPTCTRL_TXS_MASK (0x10000U)
35067 #define USB_ENDPTCTRL_TXS_SHIFT (16U)
35068 #define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
35069 #define USB_ENDPTCTRL_TXD_MASK (0x20000U)
35070 #define USB_ENDPTCTRL_TXD_SHIFT (17U)
35071 #define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
35072 #define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
35073 #define USB_ENDPTCTRL_TXT_SHIFT (18U)
35074 #define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
35075 #define USB_ENDPTCTRL_TXI_MASK (0x200000U)
35076 #define USB_ENDPTCTRL_TXI_SHIFT (21U)
35077 #define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
35078 #define USB_ENDPTCTRL_TXR_MASK (0x400000U)
35079 #define USB_ENDPTCTRL_TXR_SHIFT (22U)
35080 #define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
35081 #define USB_ENDPTCTRL_TXE_MASK (0x800000U)
35082 #define USB_ENDPTCTRL_TXE_SHIFT (23U)
35083 #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
35086 /* The count of USB_ENDPTCTRL */
35087 #define USB_ENDPTCTRL_COUNT (7U)
35088 
35089  /* end of group USB_Register_Masks */
35093 
35094 
35095 /* USB - Peripheral instance base addresses */
35097 #define USB_BASE (0x402E0000u)
35099 #define USB ((USB_Type *)USB_BASE)
35101 #define USB_BASE_ADDRS { 0u, USB_BASE }
35103 #define USB_BASE_PTRS { (USB_Type *)0u, USB }
35105 #define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn }
35106 /* Backward compatibility */
35107 #define GPTIMER0CTL GPTIMER0CTRL
35108 #define GPTIMER1CTL GPTIMER1CTRL
35109 #define USB_SBUSCFG SBUSCFG
35110 #define EPLISTADDR ENDPTLISTADDR
35111 #define EPSETUPSR ENDPTSETUPSTAT
35112 #define EPPRIME ENDPTPRIME
35113 #define EPFLUSH ENDPTFLUSH
35114 #define EPSR ENDPTSTAT
35115 #define EPCOMPLETE ENDPTCOMPLETE
35116 #define EPCR ENDPTCTRL
35117 #define EPCR0 ENDPTCTRL0
35118 #define USBHS_ID_ID_MASK USB_ID_ID_MASK
35119 #define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
35120 #define USBHS_ID_ID(x) USB_ID_ID(x)
35121 #define USBHS_ID_NID_MASK USB_ID_NID_MASK
35122 #define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
35123 #define USBHS_ID_NID(x) USB_ID_NID(x)
35124 #define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
35125 #define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
35126 #define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
35127 #define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
35128 #define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
35129 #define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
35130 #define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
35131 #define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
35132 #define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
35133 #define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
35134 #define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
35135 #define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
35136 #define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
35137 #define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
35138 #define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
35139 #define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
35140 #define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
35141 #define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
35142 #define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
35143 #define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
35144 #define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
35145 #define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
35146 #define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
35147 #define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
35148 #define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
35149 #define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
35150 #define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
35151 #define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
35152 #define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
35153 #define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
35154 #define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
35155 #define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
35156 #define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
35157 #define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
35158 #define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
35159 #define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
35160 #define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
35161 #define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
35162 #define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
35163 #define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
35164 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
35165 #define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
35166 #define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
35167 #define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
35168 #define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
35169 #define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
35170 #define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
35171 #define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
35172 #define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
35173 #define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
35174 #define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
35175 #define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
35176 #define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
35177 #define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
35178 #define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
35179 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
35180 #define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
35181 #define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
35182 #define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
35183 #define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
35184 #define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
35185 #define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
35186 #define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
35187 #define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
35188 #define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
35189 #define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
35190 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
35191 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
35192 #define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
35193 #define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
35194 #define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
35195 #define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
35196 #define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
35197 #define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
35198 #define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
35199 #define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
35200 #define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
35201 #define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
35202 #define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
35203 #define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
35204 #define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
35205 #define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
35206 #define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
35207 #define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
35208 #define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
35209 #define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
35210 #define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
35211 #define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
35212 #define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
35213 #define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
35214 #define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
35215 #define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
35216 #define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
35217 #define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
35218 #define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
35219 #define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
35220 #define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
35221 #define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
35222 #define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
35223 #define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
35224 #define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
35225 #define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
35226 #define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
35227 #define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
35228 #define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
35229 #define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
35230 #define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
35231 #define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
35232 #define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
35233 #define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
35234 #define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
35235 #define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
35236 #define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
35237 #define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
35238 #define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
35239 #define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
35240 #define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
35241 #define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
35242 #define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
35243 #define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
35244 #define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
35245 #define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
35246 #define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
35247 #define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
35248 #define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
35249 #define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
35250 #define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
35251 #define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
35252 #define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
35253 #define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
35254 #define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
35255 #define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
35256 #define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
35257 #define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
35258 #define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
35259 #define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
35260 #define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
35261 #define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
35262 #define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
35263 #define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
35264 #define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
35265 #define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
35266 #define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
35267 #define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
35268 #define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
35269 #define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
35270 #define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
35271 #define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
35272 #define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
35273 #define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
35274 #define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
35275 #define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
35276 #define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
35277 #define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
35278 #define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
35279 #define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
35280 #define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
35281 #define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
35282 #define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
35283 #define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
35284 #define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
35285 #define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
35286 #define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
35287 #define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
35288 #define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
35289 #define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
35290 #define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
35291 #define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
35292 #define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
35293 #define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
35294 #define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
35295 #define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
35296 #define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
35297 #define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
35298 #define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
35299 #define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
35300 #define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
35301 #define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
35302 #define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
35303 #define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
35304 #define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
35305 #define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
35306 #define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
35307 #define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
35308 #define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
35309 #define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
35310 #define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
35311 #define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
35312 #define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
35313 #define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
35314 #define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
35315 #define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
35316 #define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
35317 #define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
35318 #define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
35319 #define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
35320 #define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
35321 #define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
35322 #define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
35323 #define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
35324 #define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
35325 #define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
35326 #define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
35327 #define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
35328 #define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
35329 #define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
35330 #define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
35331 #define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
35332 #define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
35333 #define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
35334 #define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
35335 #define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
35336 #define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
35337 #define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
35338 #define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
35339 #define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
35340 #define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
35341 #define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
35342 #define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
35343 #define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
35344 #define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
35345 #define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
35346 #define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
35347 #define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
35348 #define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
35349 #define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
35350 #define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
35351 #define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
35352 #define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
35353 #define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
35354 #define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
35355 #define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
35356 #define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
35357 #define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
35358 #define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
35359 #define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
35360 #define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
35361 #define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
35362 #define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
35363 #define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
35364 #define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
35365 #define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
35366 #define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
35367 #define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
35368 #define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
35369 #define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
35370 #define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
35371 #define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
35372 #define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
35373 #define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
35374 #define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
35375 #define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
35376 #define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
35377 #define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
35378 #define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
35379 #define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
35380 #define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
35381 #define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
35382 #define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
35383 #define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
35384 #define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
35385 #define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
35386 #define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
35387 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
35388 #define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
35389 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
35390 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
35391 #define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
35392 #define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
35393 #define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
35394 #define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
35395 #define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
35396 #define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
35397 #define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
35398 #define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
35399 #define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
35400 #define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
35401 #define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
35402 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
35403 #define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
35404 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
35405 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
35406 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
35407 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
35408 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
35409 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
35410 #define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
35411 #define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
35412 #define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
35413 #define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
35414 #define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
35415 #define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
35416 #define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
35417 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
35418 #define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
35419 #define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
35420 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
35421 #define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
35422 #define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
35423 #define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
35424 #define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
35425 #define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
35426 #define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
35427 #define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
35428 #define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
35429 #define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
35430 #define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
35431 #define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
35432 #define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
35433 #define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
35434 #define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
35435 #define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
35436 #define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
35437 #define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
35438 #define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
35439 #define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
35440 #define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
35441 #define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
35442 #define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
35443 #define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
35444 #define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
35445 #define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
35446 #define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
35447 #define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
35448 #define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
35449 #define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
35450 #define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
35451 #define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
35452 #define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
35453 #define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
35454 #define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
35455 #define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
35456 #define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
35457 #define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
35458 #define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
35459 #define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
35460 #define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
35461 #define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
35462 #define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
35463 #define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
35464 #define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
35465 #define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
35466 #define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
35467 #define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
35468 #define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
35469 #define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
35470 #define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
35471 #define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
35472 #define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
35473 #define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
35474 #define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
35475 #define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
35476 #define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
35477 #define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
35478 #define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
35479 #define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
35480 #define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
35481 #define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
35482 #define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
35483 #define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
35484 #define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
35485 #define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
35486 #define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
35487 #define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
35488 #define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
35489 #define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
35490 #define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
35491 #define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
35492 #define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
35493 #define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
35494 #define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
35495 #define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
35496 #define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
35497 #define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
35498 #define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
35499 #define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
35500 #define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
35501 #define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
35502 #define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
35503 #define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
35504 #define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
35505 #define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
35506 #define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
35507 #define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
35508 #define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
35509 #define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
35510 #define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
35511 #define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
35512 #define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
35513 #define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
35514 #define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
35515 #define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
35516 #define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
35517 #define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
35518 #define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
35519 #define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
35520 #define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
35521 #define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
35522 #define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
35523 #define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
35524 #define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
35525 #define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
35526 #define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
35527 #define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
35528 #define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
35529 #define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
35530 #define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
35531 #define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
35532 #define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
35533 #define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
35534 #define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
35535 #define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
35536 #define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
35537 #define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
35538 #define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
35539 #define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
35540 #define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
35541 #define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
35542 #define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
35543 #define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
35544 #define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
35545 #define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
35546 #define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
35547 #define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
35548 #define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
35549 #define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
35550 #define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
35551 #define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
35552 #define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
35553 #define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
35554 #define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
35555 #define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
35556 #define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
35557 #define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
35558 #define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
35559 #define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
35560 #define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
35561 #define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
35562 #define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
35563 #define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
35564 #define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
35565 #define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
35566 #define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
35567 #define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
35568 #define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
35569 #define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
35570 #define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
35571 #define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
35572 #define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
35573 #define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
35574 #define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
35575 #define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
35576 #define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
35577 #define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
35578 #define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
35579 #define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
35580 #define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
35581 #define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
35582 #define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
35583 #define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
35584 #define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
35585 #define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
35586 #define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
35587 #define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
35588 #define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
35589 #define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
35590 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
35591 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
35592 #define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
35593 #define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
35594 #define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
35595 #define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
35596 #define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
35597 #define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
35598 #define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
35599 #define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
35600 #define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
35601 #define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
35602 #define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
35603 #define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
35604 #define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
35605 #define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
35606 #define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
35607 #define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
35608 #define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
35609 #define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
35610 #define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
35611 #define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
35612 #define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
35613 #define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
35614 #define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
35615 #define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
35616 #define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
35617 #define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
35618 #define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
35619 #define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
35620 #define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
35621 #define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
35622 #define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
35623 #define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
35624 #define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
35625 #define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
35626 #define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
35627 #define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
35628 #define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
35629 #define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
35630 #define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
35631 #define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
35632 #define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
35633 #define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
35634 #define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
35635 #define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
35636 #define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
35637 #define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
35638 #define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
35639 #define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
35640 #define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
35641 #define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
35642 #define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
35643 #define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
35644 #define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
35645 #define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
35646 #define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
35647 #define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
35648 #define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
35649 #define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
35650 #define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
35651 #define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
35652 #define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
35653 #define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
35654 #define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
35655 #define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
35656 #define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
35657 #define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
35658 #define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
35659 #define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
35660 #define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
35661 #define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
35662 #define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
35663 #define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
35664 #define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
35665 #define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
35666 #define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
35667 #define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
35668 #define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
35669 #define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
35670 #define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
35671 #define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
35672 #define USBHS_Type USB_Type
35673 #define USBHS_BASE_ADDRS { USB_BASE }
35674 #define USBHS_IRQS { USB_OTG1_IRQn }
35675 #define USBHS_IRQHandler USB_OTG1_IRQHandler
35676 
35677  /* end of group USB_Peripheral_Access_Layer */
35681 
35682 
35683 /* ----------------------------------------------------------------------------
35684  -- USBNC Peripheral Access Layer
35685  ---------------------------------------------------------------------------- */
35686 
35693 typedef struct {
35694  uint8_t RESERVED_0[2048];
35695  __IO uint32_t USB_OTGn_CTRL;
35696  uint8_t RESERVED_1[20];
35697  __IO uint32_t USB_OTGn_PHY_CTRL_0;
35698 } USBNC_Type;
35699 
35700 /* ----------------------------------------------------------------------------
35701  -- USBNC Register Masks
35702  ---------------------------------------------------------------------------- */
35703 
35711 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)
35712 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)
35717 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
35718 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)
35719 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)
35724 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
35725 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)
35726 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)
35731 #define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
35732 #define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)
35733 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)
35738 #define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
35739 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)
35740 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)
35745 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
35746 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)
35747 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)
35752 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
35753 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)
35754 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)
35759 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
35760 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)
35761 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)
35766 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
35767 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)
35768 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)
35773 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
35774 #define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)
35775 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)
35780 #define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
35785 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
35786 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
35791 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) /* end of group USBNC_Register_Masks */
35798 
35799 
35800 /* USBNC - Peripheral instance base addresses */
35802 #define USBNC_BASE (0x402E0000u)
35804 #define USBNC ((USBNC_Type *)USBNC_BASE)
35806 #define USBNC_BASE_ADDRS { 0u, USBNC_BASE }
35808 #define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC }
35809  /* end of group USBNC_Peripheral_Access_Layer */
35813 
35814 
35815 /* ----------------------------------------------------------------------------
35816  -- USBPHY Peripheral Access Layer
35817  ---------------------------------------------------------------------------- */
35818 
35825 typedef struct {
35826  __IO uint32_t PWD;
35827  __IO uint32_t PWD_SET;
35828  __IO uint32_t PWD_CLR;
35829  __IO uint32_t PWD_TOG;
35830  __IO uint32_t TX;
35831  __IO uint32_t TX_SET;
35832  __IO uint32_t TX_CLR;
35833  __IO uint32_t TX_TOG;
35834  __IO uint32_t RX;
35835  __IO uint32_t RX_SET;
35836  __IO uint32_t RX_CLR;
35837  __IO uint32_t RX_TOG;
35838  __IO uint32_t CTRL;
35839  __IO uint32_t CTRL_SET;
35840  __IO uint32_t CTRL_CLR;
35841  __IO uint32_t CTRL_TOG;
35842  __IO uint32_t STATUS;
35843  uint8_t RESERVED_0[12];
35844  __IO uint32_t DEBUGr;
35845  __IO uint32_t DEBUG_SET;
35846  __IO uint32_t DEBUG_CLR;
35847  __IO uint32_t DEBUG_TOG;
35848  __I uint32_t DEBUG0_STATUS;
35849  uint8_t RESERVED_1[12];
35850  __IO uint32_t DEBUG1;
35851  __IO uint32_t DEBUG1_SET;
35852  __IO uint32_t DEBUG1_CLR;
35853  __IO uint32_t DEBUG1_TOG;
35854  __I uint32_t VERSION;
35855 } USBPHY_Type;
35856 
35857 /* ----------------------------------------------------------------------------
35858  -- USBPHY Register Masks
35859  ---------------------------------------------------------------------------- */
35860 
35868 #define USBPHY_PWD_RSVD0_MASK (0x3FFU)
35869 #define USBPHY_PWD_RSVD0_SHIFT (0U)
35870 #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
35871 #define USBPHY_PWD_TXPWDFS_MASK (0x400U)
35872 #define USBPHY_PWD_TXPWDFS_SHIFT (10U)
35873 #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
35874 #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
35875 #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
35876 #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
35877 #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
35878 #define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
35879 #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
35880 #define USBPHY_PWD_RSVD1_MASK (0x1E000U)
35881 #define USBPHY_PWD_RSVD1_SHIFT (13U)
35882 #define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
35883 #define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
35884 #define USBPHY_PWD_RXPWDENV_SHIFT (17U)
35885 #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
35886 #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
35887 #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
35888 #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
35889 #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
35890 #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
35891 #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
35892 #define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
35893 #define USBPHY_PWD_RXPWDRX_SHIFT (20U)
35894 #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
35895 #define USBPHY_PWD_RSVD2_MASK (0xFFE00000U)
35896 #define USBPHY_PWD_RSVD2_SHIFT (21U)
35897 #define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
35902 #define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)
35903 #define USBPHY_PWD_SET_RSVD0_SHIFT (0U)
35904 #define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
35905 #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
35906 #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
35907 #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
35908 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
35909 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
35910 #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
35911 #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
35912 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
35913 #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
35914 #define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)
35915 #define USBPHY_PWD_SET_RSVD1_SHIFT (13U)
35916 #define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
35917 #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
35918 #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
35919 #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
35920 #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
35921 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
35922 #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
35923 #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
35924 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
35925 #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
35926 #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
35927 #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
35928 #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
35929 #define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)
35930 #define USBPHY_PWD_SET_RSVD2_SHIFT (21U)
35931 #define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
35936 #define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)
35937 #define USBPHY_PWD_CLR_RSVD0_SHIFT (0U)
35938 #define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
35939 #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
35940 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
35941 #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
35942 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
35943 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
35944 #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
35945 #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
35946 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
35947 #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
35948 #define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)
35949 #define USBPHY_PWD_CLR_RSVD1_SHIFT (13U)
35950 #define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
35951 #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
35952 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
35953 #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
35954 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
35955 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
35956 #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
35957 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
35958 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
35959 #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
35960 #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
35961 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
35962 #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
35963 #define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)
35964 #define USBPHY_PWD_CLR_RSVD2_SHIFT (21U)
35965 #define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
35970 #define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)
35971 #define USBPHY_PWD_TOG_RSVD0_SHIFT (0U)
35972 #define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
35973 #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
35974 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
35975 #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
35976 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
35977 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
35978 #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
35979 #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
35980 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
35981 #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
35982 #define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)
35983 #define USBPHY_PWD_TOG_RSVD1_SHIFT (13U)
35984 #define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
35985 #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
35986 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
35987 #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
35988 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
35989 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
35990 #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
35991 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
35992 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
35993 #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
35994 #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
35995 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
35996 #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
35997 #define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)
35998 #define USBPHY_PWD_TOG_RSVD2_SHIFT (21U)
35999 #define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
36004 #define USBPHY_TX_D_CAL_MASK (0xFU)
36005 #define USBPHY_TX_D_CAL_SHIFT (0U)
36006 #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
36007 #define USBPHY_TX_RSVD0_MASK (0xF0U)
36008 #define USBPHY_TX_RSVD0_SHIFT (4U)
36009 #define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
36010 #define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
36011 #define USBPHY_TX_TXCAL45DN_SHIFT (8U)
36012 #define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
36013 #define USBPHY_TX_RSVD1_MASK (0xF000U)
36014 #define USBPHY_TX_RSVD1_SHIFT (12U)
36015 #define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
36016 #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
36017 #define USBPHY_TX_TXCAL45DP_SHIFT (16U)
36018 #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
36019 #define USBPHY_TX_RSVD2_MASK (0x3F00000U)
36020 #define USBPHY_TX_RSVD2_SHIFT (20U)
36021 #define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
36022 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
36023 #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
36024 #define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
36025 #define USBPHY_TX_RSVD5_MASK (0xE0000000U)
36026 #define USBPHY_TX_RSVD5_SHIFT (29U)
36027 #define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
36032 #define USBPHY_TX_SET_D_CAL_MASK (0xFU)
36033 #define USBPHY_TX_SET_D_CAL_SHIFT (0U)
36034 #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
36035 #define USBPHY_TX_SET_RSVD0_MASK (0xF0U)
36036 #define USBPHY_TX_SET_RSVD0_SHIFT (4U)
36037 #define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
36038 #define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
36039 #define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
36040 #define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
36041 #define USBPHY_TX_SET_RSVD1_MASK (0xF000U)
36042 #define USBPHY_TX_SET_RSVD1_SHIFT (12U)
36043 #define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
36044 #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
36045 #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
36046 #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
36047 #define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)
36048 #define USBPHY_TX_SET_RSVD2_SHIFT (20U)
36049 #define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
36050 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
36051 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
36052 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
36053 #define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)
36054 #define USBPHY_TX_SET_RSVD5_SHIFT (29U)
36055 #define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
36060 #define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
36061 #define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
36062 #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
36063 #define USBPHY_TX_CLR_RSVD0_MASK (0xF0U)
36064 #define USBPHY_TX_CLR_RSVD0_SHIFT (4U)
36065 #define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
36066 #define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
36067 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
36068 #define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
36069 #define USBPHY_TX_CLR_RSVD1_MASK (0xF000U)
36070 #define USBPHY_TX_CLR_RSVD1_SHIFT (12U)
36071 #define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
36072 #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
36073 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
36074 #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
36075 #define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)
36076 #define USBPHY_TX_CLR_RSVD2_SHIFT (20U)
36077 #define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
36078 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
36079 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
36080 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
36081 #define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)
36082 #define USBPHY_TX_CLR_RSVD5_SHIFT (29U)
36083 #define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
36088 #define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
36089 #define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
36090 #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
36091 #define USBPHY_TX_TOG_RSVD0_MASK (0xF0U)
36092 #define USBPHY_TX_TOG_RSVD0_SHIFT (4U)
36093 #define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
36094 #define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
36095 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
36096 #define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
36097 #define USBPHY_TX_TOG_RSVD1_MASK (0xF000U)
36098 #define USBPHY_TX_TOG_RSVD1_SHIFT (12U)
36099 #define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
36100 #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
36101 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
36102 #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
36103 #define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)
36104 #define USBPHY_TX_TOG_RSVD2_SHIFT (20U)
36105 #define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
36106 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
36107 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
36108 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
36109 #define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)
36110 #define USBPHY_TX_TOG_RSVD5_SHIFT (29U)
36111 #define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
36116 #define USBPHY_RX_ENVADJ_MASK (0x7U)
36117 #define USBPHY_RX_ENVADJ_SHIFT (0U)
36118 #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
36119 #define USBPHY_RX_RSVD0_MASK (0x8U)
36120 #define USBPHY_RX_RSVD0_SHIFT (3U)
36121 #define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
36122 #define USBPHY_RX_DISCONADJ_MASK (0x70U)
36123 #define USBPHY_RX_DISCONADJ_SHIFT (4U)
36124 #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
36125 #define USBPHY_RX_RSVD1_MASK (0x3FFF80U)
36126 #define USBPHY_RX_RSVD1_SHIFT (7U)
36127 #define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
36128 #define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
36129 #define USBPHY_RX_RXDBYPASS_SHIFT (22U)
36130 #define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
36131 #define USBPHY_RX_RSVD2_MASK (0xFF800000U)
36132 #define USBPHY_RX_RSVD2_SHIFT (23U)
36133 #define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
36138 #define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
36139 #define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
36140 #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
36141 #define USBPHY_RX_SET_RSVD0_MASK (0x8U)
36142 #define USBPHY_RX_SET_RSVD0_SHIFT (3U)
36143 #define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
36144 #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
36145 #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
36146 #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
36147 #define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)
36148 #define USBPHY_RX_SET_RSVD1_SHIFT (7U)
36149 #define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
36150 #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
36151 #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
36152 #define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
36153 #define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)
36154 #define USBPHY_RX_SET_RSVD2_SHIFT (23U)
36155 #define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
36160 #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
36161 #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
36162 #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
36163 #define USBPHY_RX_CLR_RSVD0_MASK (0x8U)
36164 #define USBPHY_RX_CLR_RSVD0_SHIFT (3U)
36165 #define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
36166 #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
36167 #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
36168 #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
36169 #define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)
36170 #define USBPHY_RX_CLR_RSVD1_SHIFT (7U)
36171 #define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
36172 #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
36173 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
36174 #define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
36175 #define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)
36176 #define USBPHY_RX_CLR_RSVD2_SHIFT (23U)
36177 #define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
36182 #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
36183 #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
36184 #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
36185 #define USBPHY_RX_TOG_RSVD0_MASK (0x8U)
36186 #define USBPHY_RX_TOG_RSVD0_SHIFT (3U)
36187 #define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
36188 #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
36189 #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
36190 #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
36191 #define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)
36192 #define USBPHY_RX_TOG_RSVD1_SHIFT (7U)
36193 #define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
36194 #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
36195 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
36196 #define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
36197 #define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)
36198 #define USBPHY_RX_TOG_RSVD2_SHIFT (23U)
36199 #define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
36204 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
36205 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
36206 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
36207 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
36208 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
36209 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
36210 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
36211 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
36212 #define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
36213 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
36214 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
36215 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
36216 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
36217 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
36218 #define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
36219 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
36220 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
36221 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
36222 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
36223 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
36224 #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
36225 #define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
36226 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
36227 #define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
36228 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
36229 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
36230 #define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
36231 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
36232 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
36233 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
36234 #define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
36235 #define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
36236 #define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
36237 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
36238 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
36239 #define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
36240 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
36241 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
36242 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
36243 #define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)
36244 #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)
36245 #define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
36246 #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
36247 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
36248 #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
36249 #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
36250 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
36251 #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
36252 #define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
36253 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
36254 #define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
36255 #define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
36256 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
36257 #define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
36258 #define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)
36259 #define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)
36260 #define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
36261 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
36262 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
36263 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
36264 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
36265 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
36266 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
36267 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
36268 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
36269 #define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
36270 #define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
36271 #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
36272 #define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
36273 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
36274 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
36275 #define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
36276 #define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
36277 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
36278 #define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
36279 #define USBPHY_CTRL_RSVD1_MASK (0x6000000U)
36280 #define USBPHY_CTRL_RSVD1_SHIFT (25U)
36281 #define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
36282 #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
36283 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
36284 #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
36285 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
36286 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
36287 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
36288 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
36289 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
36290 #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
36291 #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
36292 #define USBPHY_CTRL_CLKGATE_SHIFT (30U)
36293 #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
36294 #define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
36295 #define USBPHY_CTRL_SFTRST_SHIFT (31U)
36296 #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
36301 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
36302 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
36303 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
36304 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
36305 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
36306 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
36307 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
36308 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
36309 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
36310 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
36311 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
36312 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
36313 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
36314 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
36315 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
36316 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
36317 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
36318 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
36319 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
36320 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
36321 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
36322 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
36323 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
36324 #define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
36325 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
36326 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
36327 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
36328 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
36329 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
36330 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
36331 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
36332 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
36333 #define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
36334 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
36335 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
36336 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
36337 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
36338 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
36339 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
36340 #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)
36341 #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)
36342 #define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
36343 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
36344 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
36345 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
36346 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
36347 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
36348 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
36349 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
36350 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
36351 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
36352 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
36353 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
36354 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
36355 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)
36356 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)
36357 #define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
36358 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
36359 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
36360 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
36361 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
36362 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
36363 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
36364 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
36365 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
36366 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
36367 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
36368 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
36369 #define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
36370 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
36371 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
36372 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
36373 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
36374 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
36375 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
36376 #define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)
36377 #define USBPHY_CTRL_SET_RSVD1_SHIFT (25U)
36378 #define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
36379 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
36380 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
36381 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
36382 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
36383 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
36384 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
36385 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
36386 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
36387 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
36388 #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
36389 #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
36390 #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
36391 #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
36392 #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
36393 #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
36398 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
36399 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
36400 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
36401 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
36402 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
36403 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
36404 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
36405 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
36406 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
36407 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
36408 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
36409 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
36410 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
36411 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
36412 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
36413 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
36414 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
36415 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
36416 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
36417 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
36418 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
36419 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
36420 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
36421 #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
36422 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
36423 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
36424 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
36425 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
36426 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
36427 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
36428 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
36429 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
36430 #define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
36431 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
36432 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
36433 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
36434 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
36435 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
36436 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
36437 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)
36438 #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)
36439 #define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
36440 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
36441 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
36442 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
36443 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
36444 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
36445 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
36446 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
36447 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
36448 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
36449 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
36450 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
36451 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
36452 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)
36453 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)
36454 #define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
36455 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
36456 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
36457 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
36458 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
36459 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
36460 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
36461 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
36462 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
36463 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
36464 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
36465 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
36466 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
36467 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
36468 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
36469 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
36470 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
36471 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
36472 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
36473 #define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)
36474 #define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)
36475 #define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
36476 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
36477 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
36478 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
36479 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
36480 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
36481 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
36482 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
36483 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
36484 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
36485 #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
36486 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
36487 #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
36488 #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
36489 #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
36490 #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
36495 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
36496 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
36497 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
36498 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
36499 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
36500 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
36501 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
36502 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
36503 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
36504 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
36505 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
36506 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
36507 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
36508 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
36509 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
36510 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
36511 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
36512 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
36513 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
36514 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
36515 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
36516 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
36517 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
36518 #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
36519 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
36520 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
36521 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
36522 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
36523 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
36524 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
36525 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
36526 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
36527 #define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
36528 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
36529 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
36530 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
36531 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
36532 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
36533 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
36534 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)
36535 #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)
36536 #define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
36537 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
36538 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
36539 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
36540 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
36541 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
36542 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
36543 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
36544 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
36545 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
36546 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
36547 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
36548 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
36549 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)
36550 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)
36551 #define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
36552 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
36553 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
36554 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
36555 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
36556 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
36557 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
36558 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
36559 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
36560 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
36561 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
36562 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
36563 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
36564 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
36565 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
36566 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
36567 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
36568 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
36569 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
36570 #define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)
36571 #define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)
36572 #define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
36573 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
36574 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
36575 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
36576 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
36577 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
36578 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
36579 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
36580 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
36581 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
36582 #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
36583 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
36584 #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
36585 #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
36586 #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
36587 #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
36592 #define USBPHY_STATUS_RSVD0_MASK (0x7U)
36593 #define USBPHY_STATUS_RSVD0_SHIFT (0U)
36594 #define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
36595 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
36596 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
36597 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
36598 #define USBPHY_STATUS_RSVD1_MASK (0x30U)
36599 #define USBPHY_STATUS_RSVD1_SHIFT (4U)
36600 #define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
36601 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
36602 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
36603 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
36604 #define USBPHY_STATUS_RSVD2_MASK (0x80U)
36605 #define USBPHY_STATUS_RSVD2_SHIFT (7U)
36606 #define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
36607 #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
36608 #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
36609 #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
36610 #define USBPHY_STATUS_RSVD3_MASK (0x200U)
36611 #define USBPHY_STATUS_RSVD3_SHIFT (9U)
36612 #define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
36613 #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
36614 #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
36615 #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
36616 #define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)
36617 #define USBPHY_STATUS_RSVD4_SHIFT (11U)
36618 #define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
36623 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
36624 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
36625 #define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
36626 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
36627 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
36628 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
36629 #define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
36630 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
36631 #define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
36632 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
36633 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
36634 #define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
36635 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U)
36636 #define USBPHY_DEBUG_RSVD0_SHIFT (6U)
36637 #define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
36638 #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
36639 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
36640 #define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
36641 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
36642 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
36643 #define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
36644 #define USBPHY_DEBUG_RSVD1_MASK (0xE000U)
36645 #define USBPHY_DEBUG_RSVD1_SHIFT (13U)
36646 #define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
36647 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
36648 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
36649 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
36650 #define USBPHY_DEBUG_RSVD2_MASK (0xE00000U)
36651 #define USBPHY_DEBUG_RSVD2_SHIFT (21U)
36652 #define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
36653 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
36654 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
36655 #define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
36656 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
36657 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
36658 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
36659 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
36660 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
36661 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
36662 #define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
36663 #define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
36664 #define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
36665 #define USBPHY_DEBUG_RSVD3_MASK (0x80000000U)
36666 #define USBPHY_DEBUG_RSVD3_SHIFT (31U)
36667 #define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
36672 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
36673 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
36674 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
36675 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
36676 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
36677 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
36678 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
36679 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
36680 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
36681 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
36682 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
36683 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
36684 #define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)
36685 #define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)
36686 #define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
36687 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
36688 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
36689 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
36690 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
36691 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
36692 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
36693 #define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)
36694 #define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)
36695 #define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
36696 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
36697 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
36698 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
36699 #define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)
36700 #define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)
36701 #define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
36702 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
36703 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
36704 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
36705 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
36706 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
36707 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
36708 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
36709 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
36710 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
36711 #define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
36712 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
36713 #define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
36714 #define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)
36715 #define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)
36716 #define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
36721 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
36722 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
36723 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
36724 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
36725 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
36726 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
36727 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
36728 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
36729 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
36730 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
36731 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
36732 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
36733 #define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)
36734 #define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)
36735 #define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
36736 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
36737 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
36738 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
36739 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
36740 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
36741 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
36742 #define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)
36743 #define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)
36744 #define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
36745 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
36746 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
36747 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
36748 #define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)
36749 #define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)
36750 #define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
36751 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
36752 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
36753 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
36754 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
36755 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
36756 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
36757 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
36758 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
36759 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
36760 #define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
36761 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
36762 #define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
36763 #define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)
36764 #define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)
36765 #define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
36770 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
36771 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
36772 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
36773 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
36774 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
36775 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
36776 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
36777 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
36778 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
36779 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
36780 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
36781 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
36782 #define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)
36783 #define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)
36784 #define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
36785 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
36786 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
36787 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
36788 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
36789 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
36790 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
36791 #define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)
36792 #define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)
36793 #define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
36794 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
36795 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
36796 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
36797 #define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)
36798 #define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)
36799 #define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
36800 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
36801 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
36802 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
36803 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
36804 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
36805 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
36806 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
36807 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
36808 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
36809 #define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
36810 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
36811 #define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
36812 #define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)
36813 #define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)
36814 #define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
36819 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
36820 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
36821 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
36822 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
36823 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
36824 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
36825 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
36826 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
36827 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
36832 #define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)
36833 #define USBPHY_DEBUG1_RSVD0_SHIFT (0U)
36834 #define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
36835 #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
36836 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
36837 #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
36838 #define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)
36839 #define USBPHY_DEBUG1_RSVD1_SHIFT (15U)
36840 #define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
36845 #define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)
36846 #define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)
36847 #define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
36848 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
36849 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
36850 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
36851 #define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)
36852 #define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)
36853 #define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
36858 #define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)
36859 #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)
36860 #define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
36861 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
36862 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
36863 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
36864 #define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)
36865 #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)
36866 #define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
36871 #define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)
36872 #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)
36873 #define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
36874 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
36875 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
36876 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
36877 #define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)
36878 #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)
36879 #define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
36884 #define USBPHY_VERSION_STEP_MASK (0xFFFFU)
36885 #define USBPHY_VERSION_STEP_SHIFT (0U)
36886 #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
36887 #define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
36888 #define USBPHY_VERSION_MINOR_SHIFT (16U)
36889 #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
36890 #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
36891 #define USBPHY_VERSION_MAJOR_SHIFT (24U)
36892 #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) /* end of group USBPHY_Register_Masks */
36899 
36900 
36901 /* USBPHY - Peripheral instance base addresses */
36903 #define USBPHY_BASE (0x400D9000u)
36905 #define USBPHY ((USBPHY_Type *)USBPHY_BASE)
36907 #define USBPHY_BASE_ADDRS { 0u, USBPHY_BASE }
36909 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY }
36911 #define USBPHY_IRQS { NotAvail_IRQn, USB_PHY_IRQn }
36912 /* Backward compatibility */
36913 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
36914 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
36915 #define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
36916 #define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
36917 #define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
36918 #define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
36919 
36920  /* end of group USBPHY_Peripheral_Access_Layer */
36924 
36925 
36926 /* ----------------------------------------------------------------------------
36927  -- USB_ANALOG Peripheral Access Layer
36928  ---------------------------------------------------------------------------- */
36929 
36936 typedef struct {
36937  uint8_t RESERVED_0[416];
36938  struct { /* offset: 0x1A0, array step: 0x60 */
36939  __IO uint32_t VBUS_DETECT;
36940  __IO uint32_t VBUS_DETECT_SET;
36941  __IO uint32_t VBUS_DETECT_CLR;
36942  __IO uint32_t VBUS_DETECT_TOG;
36943  __IO uint32_t CHRG_DETECT;
36944  __IO uint32_t CHRG_DETECT_SET;
36945  __IO uint32_t CHRG_DETECT_CLR;
36946  __IO uint32_t CHRG_DETECT_TOG;
36947  __I uint32_t VBUS_DETECT_STAT;
36948  uint8_t RESERVED_0[12];
36949  __I uint32_t CHRG_DETECT_STAT;
36950  uint8_t RESERVED_1[12];
36951  __IO uint32_t LOOPBACK;
36952  __IO uint32_t LOOPBACK_SET;
36953  __IO uint32_t LOOPBACK_CLR;
36954  __IO uint32_t LOOPBACK_TOG;
36955  __IO uint32_t MISC;
36956  __IO uint32_t MISC_SET;
36957  __IO uint32_t MISC_CLR;
36958  __IO uint32_t MISC_TOG;
36959  } INSTANCE[1];
36960  uint8_t RESERVED_1[96];
36961  __I uint32_t DIGPROG;
36962 } USB_ANALOG_Type;
36963 
36964 /* ----------------------------------------------------------------------------
36965  -- USB_ANALOG Register Masks
36966  ---------------------------------------------------------------------------- */
36967 
36975 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
36976 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
36987 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
36988 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
36989 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
36990 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
36991 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
36992 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
36993 #define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
36994 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)
36995 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
36996 #define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
36999 /* The count of USB_ANALOG_VBUS_DETECT */
37000 #define USB_ANALOG_VBUS_DETECT_COUNT (1U)
37001 
37004 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
37005 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
37016 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
37017 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
37018 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
37019 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
37020 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
37021 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
37022 #define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
37023 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
37024 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
37025 #define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
37028 /* The count of USB_ANALOG_VBUS_DETECT_SET */
37029 #define USB_ANALOG_VBUS_DETECT_SET_COUNT (1U)
37030 
37033 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
37034 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
37045 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
37046 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
37047 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
37048 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
37049 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
37050 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
37051 #define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
37052 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
37053 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
37054 #define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
37057 /* The count of USB_ANALOG_VBUS_DETECT_CLR */
37058 #define USB_ANALOG_VBUS_DETECT_CLR_COUNT (1U)
37059 
37062 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
37063 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
37074 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
37075 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
37076 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
37077 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
37078 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
37079 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
37080 #define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
37081 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
37082 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
37083 #define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
37086 /* The count of USB_ANALOG_VBUS_DETECT_TOG */
37087 #define USB_ANALOG_VBUS_DETECT_TOG_COUNT (1U)
37088 
37091 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
37092 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
37097 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
37098 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)
37099 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
37104 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
37105 #define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)
37106 #define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)
37111 #define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
37114 /* The count of USB_ANALOG_CHRG_DETECT */
37115 #define USB_ANALOG_CHRG_DETECT_COUNT (1U)
37116 
37119 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
37120 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
37125 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
37126 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
37127 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
37132 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
37133 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)
37134 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)
37139 #define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
37142 /* The count of USB_ANALOG_CHRG_DETECT_SET */
37143 #define USB_ANALOG_CHRG_DETECT_SET_COUNT (1U)
37144 
37147 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
37148 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
37153 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
37154 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
37155 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
37160 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
37161 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)
37162 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)
37167 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
37170 /* The count of USB_ANALOG_CHRG_DETECT_CLR */
37171 #define USB_ANALOG_CHRG_DETECT_CLR_COUNT (1U)
37172 
37175 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
37176 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
37181 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
37182 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
37183 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
37188 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
37189 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)
37190 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)
37195 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
37198 /* The count of USB_ANALOG_CHRG_DETECT_TOG */
37199 #define USB_ANALOG_CHRG_DETECT_TOG_COUNT (1U)
37200 
37203 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
37204 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
37205 #define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
37206 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)
37207 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
37208 #define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
37209 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)
37210 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
37211 #define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
37212 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
37213 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
37214 #define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
37217 /* The count of USB_ANALOG_VBUS_DETECT_STAT */
37218 #define USB_ANALOG_VBUS_DETECT_STAT_COUNT (1U)
37219 
37222 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
37223 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
37228 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
37229 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
37230 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
37235 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
37236 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
37237 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
37238 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
37239 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
37240 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
37241 #define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
37244 /* The count of USB_ANALOG_CHRG_DETECT_STAT */
37245 #define USB_ANALOG_CHRG_DETECT_STAT_COUNT (1U)
37246 
37249 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
37250 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
37251 #define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
37254 /* The count of USB_ANALOG_LOOPBACK */
37255 #define USB_ANALOG_LOOPBACK_COUNT (1U)
37256 
37259 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
37260 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
37261 #define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
37264 /* The count of USB_ANALOG_LOOPBACK_SET */
37265 #define USB_ANALOG_LOOPBACK_SET_COUNT (1U)
37266 
37269 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
37270 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
37271 #define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
37274 /* The count of USB_ANALOG_LOOPBACK_CLR */
37275 #define USB_ANALOG_LOOPBACK_CLR_COUNT (1U)
37276 
37279 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
37280 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
37281 #define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
37284 /* The count of USB_ANALOG_LOOPBACK_TOG */
37285 #define USB_ANALOG_LOOPBACK_TOG_COUNT (1U)
37286 
37289 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)
37290 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)
37291 #define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
37292 #define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)
37293 #define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)
37294 #define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
37295 #define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)
37296 #define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)
37297 #define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
37300 /* The count of USB_ANALOG_MISC */
37301 #define USB_ANALOG_MISC_COUNT (1U)
37302 
37305 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
37306 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
37307 #define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
37308 #define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)
37309 #define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)
37310 #define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
37311 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)
37312 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)
37313 #define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
37316 /* The count of USB_ANALOG_MISC_SET */
37317 #define USB_ANALOG_MISC_SET_COUNT (1U)
37318 
37321 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
37322 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
37323 #define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
37324 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)
37325 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)
37326 #define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
37327 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)
37328 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)
37329 #define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
37332 /* The count of USB_ANALOG_MISC_CLR */
37333 #define USB_ANALOG_MISC_CLR_COUNT (1U)
37334 
37337 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
37338 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
37339 #define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
37340 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)
37341 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)
37342 #define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
37343 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)
37344 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)
37345 #define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
37348 /* The count of USB_ANALOG_MISC_TOG */
37349 #define USB_ANALOG_MISC_TOG_COUNT (1U)
37350 
37353 #define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
37354 #define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
37358 #define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) /* end of group USB_ANALOG_Register_Masks */
37365 
37366 
37367 /* USB_ANALOG - Peripheral instance base addresses */
37369 #define USB_ANALOG_BASE (0x400D8000u)
37371 #define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)
37373 #define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }
37375 #define USB_ANALOG_BASE_PTRS { USB_ANALOG }
37376  /* end of group USB_ANALOG_Peripheral_Access_Layer */
37380 
37381 
37382 /* ----------------------------------------------------------------------------
37383  -- USDHC Peripheral Access Layer
37384  ---------------------------------------------------------------------------- */
37385 
37392 typedef struct {
37393  __IO uint32_t DS_ADDR;
37394  __IO uint32_t BLK_ATT;
37395  __IO uint32_t CMD_ARG;
37396  __IO uint32_t CMD_XFR_TYP;
37397  __I uint32_t CMD_RSP0;
37398  __I uint32_t CMD_RSP1;
37399  __I uint32_t CMD_RSP2;
37400  __I uint32_t CMD_RSP3;
37401  __IO uint32_t DATA_BUFF_ACC_PORT;
37402  __I uint32_t PRES_STATE;
37403  __IO uint32_t PROT_CTRL;
37404  __IO uint32_t SYS_CTRL;
37405  __IO uint32_t INT_STATUS;
37406  __IO uint32_t INT_STATUS_EN;
37407  __IO uint32_t INT_SIGNAL_EN;
37408  __IO uint32_t AUTOCMD12_ERR_STATUS;
37409  __IO uint32_t HOST_CTRL_CAP;
37410  __IO uint32_t WTMK_LVL;
37411  __IO uint32_t MIX_CTRL;
37412  uint8_t RESERVED_0[4];
37413  __O uint32_t FORCE_EVENT;
37414  __I uint32_t ADMA_ERR_STATUS;
37415  __IO uint32_t ADMA_SYS_ADDR;
37416  uint8_t RESERVED_1[4];
37417  __IO uint32_t DLL_CTRL;
37418  __I uint32_t DLL_STATUS;
37419  __IO uint32_t CLK_TUNE_CTRL_STATUS;
37420  uint8_t RESERVED_2[84];
37421  __IO uint32_t VEND_SPEC;
37422  __IO uint32_t MMC_BOOT;
37423  __IO uint32_t VEND_SPEC2;
37424  __IO uint32_t TUNING_CTRL;
37425 } USDHC_Type;
37426 
37427 /* ----------------------------------------------------------------------------
37428  -- USDHC Register Masks
37429  ---------------------------------------------------------------------------- */
37430 
37438 #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
37439 #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
37442 #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
37447 #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
37448 #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
37460 #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
37461 #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
37462 #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
37469 #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
37474 #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
37475 #define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
37478 #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
37483 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
37484 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
37491 #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
37492 #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
37493 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
37498 #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
37499 #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
37500 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
37505 #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
37506 #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
37507 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
37512 #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
37513 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
37514 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
37521 #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
37522 #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
37523 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
37526 #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
37531 #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
37532 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
37535 #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
37540 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
37541 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
37544 #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
37549 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
37550 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
37553 #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
37558 #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
37559 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
37562 #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
37567 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
37568 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
37571 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
37576 #define USDHC_PRES_STATE_CIHB_MASK (0x1U)
37577 #define USDHC_PRES_STATE_CIHB_SHIFT (0U)
37582 #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
37583 #define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
37584 #define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
37589 #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
37590 #define USDHC_PRES_STATE_DLA_MASK (0x4U)
37591 #define USDHC_PRES_STATE_DLA_SHIFT (2U)
37596 #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
37597 #define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
37598 #define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
37603 #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
37604 #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
37605 #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
37610 #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
37611 #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
37612 #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
37617 #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
37618 #define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
37619 #define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
37624 #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
37625 #define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
37626 #define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
37631 #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
37632 #define USDHC_PRES_STATE_WTA_MASK (0x100U)
37633 #define USDHC_PRES_STATE_WTA_SHIFT (8U)
37638 #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
37639 #define USDHC_PRES_STATE_RTA_MASK (0x200U)
37640 #define USDHC_PRES_STATE_RTA_SHIFT (9U)
37645 #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
37646 #define USDHC_PRES_STATE_BWEN_MASK (0x400U)
37647 #define USDHC_PRES_STATE_BWEN_SHIFT (10U)
37652 #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
37653 #define USDHC_PRES_STATE_BREN_MASK (0x800U)
37654 #define USDHC_PRES_STATE_BREN_SHIFT (11U)
37659 #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
37660 #define USDHC_PRES_STATE_RTR_MASK (0x1000U)
37661 #define USDHC_PRES_STATE_RTR_SHIFT (12U)
37666 #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
37667 #define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
37668 #define USDHC_PRES_STATE_TSCD_SHIFT (15U)
37673 #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
37674 #define USDHC_PRES_STATE_CINST_MASK (0x10000U)
37675 #define USDHC_PRES_STATE_CINST_SHIFT (16U)
37680 #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
37681 #define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
37682 #define USDHC_PRES_STATE_CLSL_SHIFT (23U)
37685 #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
37686 #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
37687 #define USDHC_PRES_STATE_DLSL_SHIFT (24U)
37698 #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
37703 #define USDHC_PROT_CTRL_DTW_MASK (0x6U)
37704 #define USDHC_PROT_CTRL_DTW_SHIFT (1U)
37711 #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
37712 #define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
37713 #define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
37718 #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
37719 #define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
37720 #define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
37727 #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
37728 #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
37729 #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
37736 #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
37737 #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
37738 #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
37743 #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
37744 #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
37745 #define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
37750 #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
37751 #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
37752 #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
37757 #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
37758 #define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
37759 #define USDHC_PROT_CTRL_IABG_SHIFT (19U)
37764 #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
37765 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
37766 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
37769 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
37770 #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
37771 #define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
37776 #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
37777 #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
37778 #define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
37783 #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
37784 #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
37785 #define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
37790 #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
37791 #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
37792 #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
37798 #define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
37799 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
37800 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
37805 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
37810 #define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
37811 #define USDHC_SYS_CTRL_DVS_SHIFT (4U)
37818 #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
37819 #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
37820 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
37823 #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
37824 #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
37825 #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
37844 #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
37845 #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
37846 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
37849 #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
37850 #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
37851 #define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
37856 #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
37857 #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
37858 #define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
37863 #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
37864 #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
37865 #define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
37870 #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
37871 #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
37872 #define USDHC_SYS_CTRL_INITA_SHIFT (27U)
37875 #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
37876 #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
37877 #define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
37880 #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
37885 #define USDHC_INT_STATUS_CC_MASK (0x1U)
37886 #define USDHC_INT_STATUS_CC_SHIFT (0U)
37891 #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
37892 #define USDHC_INT_STATUS_TC_MASK (0x2U)
37893 #define USDHC_INT_STATUS_TC_SHIFT (1U)
37898 #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
37899 #define USDHC_INT_STATUS_BGE_MASK (0x4U)
37900 #define USDHC_INT_STATUS_BGE_SHIFT (2U)
37905 #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
37906 #define USDHC_INT_STATUS_DINT_MASK (0x8U)
37907 #define USDHC_INT_STATUS_DINT_SHIFT (3U)
37912 #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
37913 #define USDHC_INT_STATUS_BWR_MASK (0x10U)
37914 #define USDHC_INT_STATUS_BWR_SHIFT (4U)
37919 #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
37920 #define USDHC_INT_STATUS_BRR_MASK (0x20U)
37921 #define USDHC_INT_STATUS_BRR_SHIFT (5U)
37926 #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
37927 #define USDHC_INT_STATUS_CINS_MASK (0x40U)
37928 #define USDHC_INT_STATUS_CINS_SHIFT (6U)
37933 #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
37934 #define USDHC_INT_STATUS_CRM_MASK (0x80U)
37935 #define USDHC_INT_STATUS_CRM_SHIFT (7U)
37940 #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
37941 #define USDHC_INT_STATUS_CINT_MASK (0x100U)
37942 #define USDHC_INT_STATUS_CINT_SHIFT (8U)
37947 #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
37948 #define USDHC_INT_STATUS_RTE_MASK (0x1000U)
37949 #define USDHC_INT_STATUS_RTE_SHIFT (12U)
37954 #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
37955 #define USDHC_INT_STATUS_TP_MASK (0x4000U)
37956 #define USDHC_INT_STATUS_TP_SHIFT (14U)
37959 #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
37960 #define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
37961 #define USDHC_INT_STATUS_CTOE_SHIFT (16U)
37966 #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
37967 #define USDHC_INT_STATUS_CCE_MASK (0x20000U)
37968 #define USDHC_INT_STATUS_CCE_SHIFT (17U)
37973 #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
37974 #define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
37975 #define USDHC_INT_STATUS_CEBE_SHIFT (18U)
37980 #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
37981 #define USDHC_INT_STATUS_CIE_MASK (0x80000U)
37982 #define USDHC_INT_STATUS_CIE_SHIFT (19U)
37987 #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
37988 #define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
37989 #define USDHC_INT_STATUS_DTOE_SHIFT (20U)
37994 #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
37995 #define USDHC_INT_STATUS_DCE_MASK (0x200000U)
37996 #define USDHC_INT_STATUS_DCE_SHIFT (21U)
38001 #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
38002 #define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
38003 #define USDHC_INT_STATUS_DEBE_SHIFT (22U)
38008 #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
38009 #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
38010 #define USDHC_INT_STATUS_AC12E_SHIFT (24U)
38015 #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
38016 #define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
38017 #define USDHC_INT_STATUS_TNE_SHIFT (26U)
38020 #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
38021 #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
38022 #define USDHC_INT_STATUS_DMAE_SHIFT (28U)
38027 #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
38032 #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
38033 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
38038 #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
38039 #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
38040 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
38045 #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
38046 #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
38047 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
38052 #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
38053 #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
38054 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
38059 #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
38060 #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
38061 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
38066 #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
38067 #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
38068 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
38073 #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
38074 #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
38075 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
38080 #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
38081 #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
38082 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
38087 #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
38088 #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
38089 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
38094 #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
38095 #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
38096 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
38101 #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
38102 #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
38103 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
38108 #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
38109 #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
38110 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
38115 #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
38116 #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
38117 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
38122 #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
38123 #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
38124 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
38129 #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
38130 #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
38131 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
38136 #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
38137 #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
38138 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
38143 #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
38144 #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
38145 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
38150 #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
38151 #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
38152 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
38157 #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
38158 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
38159 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
38164 #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
38165 #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
38166 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
38171 #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
38172 #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
38173 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
38178 #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
38183 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
38184 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
38189 #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
38190 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
38191 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
38196 #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
38197 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
38198 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
38203 #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
38204 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
38205 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
38210 #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
38211 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
38212 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
38217 #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
38218 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
38219 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
38224 #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
38225 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
38226 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
38231 #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
38232 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
38233 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
38238 #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
38239 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
38240 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
38245 #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
38246 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
38247 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
38252 #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
38253 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
38254 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
38259 #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
38260 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
38261 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
38266 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
38267 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
38268 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
38273 #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
38274 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
38275 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
38280 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
38281 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
38282 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
38287 #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
38288 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
38289 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
38294 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
38295 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
38296 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
38301 #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
38302 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
38303 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
38308 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
38309 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
38310 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
38315 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
38316 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
38317 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
38322 #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
38323 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
38324 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
38329 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
38334 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
38335 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
38340 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
38341 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
38342 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
38347 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
38348 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
38349 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
38354 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
38355 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
38356 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
38361 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
38362 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
38363 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
38368 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
38369 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
38370 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
38375 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
38376 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
38377 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
38380 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
38381 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
38382 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
38387 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
38392 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
38393 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
38396 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
38397 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
38398 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
38401 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
38402 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
38403 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
38406 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
38407 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
38408 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
38411 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
38412 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
38413 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
38418 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
38419 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
38420 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
38427 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
38428 #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
38429 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
38436 #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
38437 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
38438 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
38443 #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
38444 #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
38445 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
38450 #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
38451 #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
38452 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
38457 #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
38458 #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
38459 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
38464 #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
38465 #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
38466 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
38471 #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
38472 #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
38473 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
38478 #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
38479 #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
38480 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
38485 #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
38490 #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
38491 #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
38494 #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
38495 #define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
38496 #define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
38499 #define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
38500 #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
38501 #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
38504 #define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
38505 #define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
38506 #define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
38509 #define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
38514 #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
38515 #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
38520 #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
38521 #define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
38522 #define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
38527 #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
38528 #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
38529 #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
38534 #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
38535 #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
38536 #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
38539 #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
38540 #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
38541 #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
38546 #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
38547 #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
38548 #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
38553 #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
38554 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
38555 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
38558 #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
38559 #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
38560 #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
38563 #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
38564 #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
38565 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
38570 #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
38571 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
38572 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
38577 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
38578 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
38579 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
38584 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
38585 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
38586 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
38591 #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
38596 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
38597 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
38600 #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
38601 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
38602 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
38605 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
38606 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
38607 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
38610 #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
38611 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
38612 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
38615 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
38616 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
38617 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
38620 #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
38621 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
38622 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
38625 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
38626 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
38627 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
38630 #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
38631 #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
38632 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
38635 #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
38636 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
38637 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
38640 #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
38641 #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
38642 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
38645 #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
38646 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
38647 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
38650 #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
38651 #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
38652 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
38655 #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
38656 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
38657 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
38660 #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
38661 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
38662 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
38665 #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
38666 #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
38667 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
38670 #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
38671 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
38672 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
38675 #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
38676 #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
38677 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
38680 #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
38685 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
38686 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
38689 #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
38690 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
38691 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
38696 #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
38697 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
38698 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
38703 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
38708 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
38709 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
38712 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
38717 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
38718 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
38721 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
38722 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
38723 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
38726 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
38727 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
38728 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
38731 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
38732 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
38733 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
38736 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
38737 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
38738 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
38741 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
38742 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
38743 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
38746 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
38747 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
38748 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
38751 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
38752 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
38753 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
38756 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
38757 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
38758 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
38761 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
38762 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
38763 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
38766 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
38771 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
38772 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
38775 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
38776 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
38777 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
38780 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
38781 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
38782 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
38785 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
38786 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
38787 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
38790 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
38795 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
38796 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
38799 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
38800 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
38801 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
38804 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
38805 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
38806 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
38809 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
38810 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
38811 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
38814 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
38815 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
38816 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
38819 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
38820 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
38821 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
38824 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
38825 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
38826 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
38829 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
38830 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
38831 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
38834 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
38839 #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
38840 #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
38845 #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
38846 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
38847 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
38852 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
38853 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
38854 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
38859 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
38860 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
38861 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
38866 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
38867 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
38868 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
38873 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
38874 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
38875 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
38880 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
38885 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
38886 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
38899 #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
38900 #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
38901 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
38906 #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
38907 #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
38908 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
38913 #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
38914 #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
38915 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
38920 #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
38921 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
38922 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
38925 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
38926 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
38927 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
38932 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
38933 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
38934 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
38937 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
38942 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
38943 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
38948 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
38949 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
38950 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
38953 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
38954 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
38955 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
38958 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
38959 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
38960 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
38965 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
38966 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
38967 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
38972 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
38977 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
38978 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
38981 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
38982 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
38983 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
38986 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
38987 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
38988 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
38991 #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
38992 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
38993 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
38996 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
38997 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
38998 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
39001 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /* end of group USDHC_Register_Masks */
39008 
39009 
39010 /* USDHC - Peripheral instance base addresses */
39012 #define USDHC1_BASE (0x402C0000u)
39014 #define USDHC1 ((USDHC_Type *)USDHC1_BASE)
39016 #define USDHC2_BASE (0x402C4000u)
39018 #define USDHC2 ((USDHC_Type *)USDHC2_BASE)
39020 #define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
39022 #define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
39024 #define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
39025  /* end of group USDHC_Peripheral_Access_Layer */
39029 
39030 
39031 /* ----------------------------------------------------------------------------
39032  -- WDOG Peripheral Access Layer
39033  ---------------------------------------------------------------------------- */
39034 
39041 typedef struct {
39042  __IO uint16_t WCR;
39043  __IO uint16_t WSR;
39044  __I uint16_t WRSR;
39045  __IO uint16_t WICR;
39046  __IO uint16_t WMCR;
39047 } WDOG_Type;
39048 
39049 /* ----------------------------------------------------------------------------
39050  -- WDOG Register Masks
39051  ---------------------------------------------------------------------------- */
39052 
39060 #define WDOG_WCR_WDZST_MASK (0x1U)
39061 #define WDOG_WCR_WDZST_SHIFT (0U)
39066 #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
39067 #define WDOG_WCR_WDBG_MASK (0x2U)
39068 #define WDOG_WCR_WDBG_SHIFT (1U)
39073 #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
39074 #define WDOG_WCR_WDE_MASK (0x4U)
39075 #define WDOG_WCR_WDE_SHIFT (2U)
39080 #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
39081 #define WDOG_WCR_WDT_MASK (0x8U)
39082 #define WDOG_WCR_WDT_SHIFT (3U)
39087 #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
39088 #define WDOG_WCR_SRS_MASK (0x10U)
39089 #define WDOG_WCR_SRS_SHIFT (4U)
39094 #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
39095 #define WDOG_WCR_WDA_MASK (0x20U)
39096 #define WDOG_WCR_WDA_SHIFT (5U)
39101 #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
39102 #define WDOG_WCR_SRE_MASK (0x40U)
39103 #define WDOG_WCR_SRE_SHIFT (6U)
39108 #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
39109 #define WDOG_WCR_WDW_MASK (0x80U)
39110 #define WDOG_WCR_WDW_SHIFT (7U)
39115 #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
39116 #define WDOG_WCR_WT_MASK (0xFF00U)
39117 #define WDOG_WCR_WT_SHIFT (8U)
39125 #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
39130 #define WDOG_WSR_WSR_MASK (0xFFFFU)
39131 #define WDOG_WSR_WSR_SHIFT (0U)
39136 #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
39141 #define WDOG_WRSR_SFTW_MASK (0x1U)
39142 #define WDOG_WRSR_SFTW_SHIFT (0U)
39147 #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
39148 #define WDOG_WRSR_TOUT_MASK (0x2U)
39149 #define WDOG_WRSR_TOUT_SHIFT (1U)
39154 #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
39155 #define WDOG_WRSR_POR_MASK (0x10U)
39156 #define WDOG_WRSR_POR_SHIFT (4U)
39161 #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
39166 #define WDOG_WICR_WICT_MASK (0xFFU)
39167 #define WDOG_WICR_WICT_SHIFT (0U)
39174 #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
39175 #define WDOG_WICR_WTIS_MASK (0x4000U)
39176 #define WDOG_WICR_WTIS_SHIFT (14U)
39181 #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
39182 #define WDOG_WICR_WIE_MASK (0x8000U)
39183 #define WDOG_WICR_WIE_SHIFT (15U)
39188 #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
39193 #define WDOG_WMCR_PDE_MASK (0x1U)
39194 #define WDOG_WMCR_PDE_SHIFT (0U)
39199 #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) /* end of group WDOG_Register_Masks */
39206 
39207 
39208 /* WDOG - Peripheral instance base addresses */
39210 #define WDOG1_BASE (0x400B8000u)
39212 #define WDOG1 ((WDOG_Type *)WDOG1_BASE)
39214 #define WDOG2_BASE (0x400D0000u)
39216 #define WDOG2 ((WDOG_Type *)WDOG2_BASE)
39218 #define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
39220 #define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
39222 #define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
39223  /* end of group WDOG_Peripheral_Access_Layer */
39227 
39228 
39229 /* ----------------------------------------------------------------------------
39230  -- XBARA Peripheral Access Layer
39231  ---------------------------------------------------------------------------- */
39232 
39239 typedef struct {
39240  __IO uint16_t SEL0;
39241  __IO uint16_t SEL1;
39242  __IO uint16_t SEL2;
39243  __IO uint16_t SEL3;
39244  __IO uint16_t SEL4;
39245  __IO uint16_t SEL5;
39246  __IO uint16_t SEL6;
39247  __IO uint16_t SEL7;
39248  __IO uint16_t SEL8;
39249  __IO uint16_t SEL9;
39250  __IO uint16_t SEL10;
39251  __IO uint16_t SEL11;
39252  __IO uint16_t SEL12;
39253  __IO uint16_t SEL13;
39254  __IO uint16_t SEL14;
39255  __IO uint16_t SEL15;
39256  __IO uint16_t SEL16;
39257  __IO uint16_t SEL17;
39258  __IO uint16_t SEL18;
39259  __IO uint16_t SEL19;
39260  __IO uint16_t SEL20;
39261  __IO uint16_t SEL21;
39262  __IO uint16_t SEL22;
39263  __IO uint16_t SEL23;
39264  __IO uint16_t SEL24;
39265  __IO uint16_t SEL25;
39266  __IO uint16_t SEL26;
39267  __IO uint16_t SEL27;
39268  __IO uint16_t SEL28;
39269  __IO uint16_t SEL29;
39270  __IO uint16_t SEL30;
39271  __IO uint16_t SEL31;
39272  __IO uint16_t SEL32;
39273  __IO uint16_t SEL33;
39274  __IO uint16_t SEL34;
39275  __IO uint16_t SEL35;
39276  __IO uint16_t SEL36;
39277  __IO uint16_t SEL37;
39278  __IO uint16_t SEL38;
39279  __IO uint16_t SEL39;
39280  __IO uint16_t SEL40;
39281  __IO uint16_t SEL41;
39282  __IO uint16_t SEL42;
39283  __IO uint16_t SEL43;
39284  __IO uint16_t SEL44;
39285  __IO uint16_t SEL45;
39286  __IO uint16_t SEL46;
39287  __IO uint16_t SEL47;
39288  __IO uint16_t SEL48;
39289  __IO uint16_t SEL49;
39290  __IO uint16_t SEL50;
39291  __IO uint16_t SEL51;
39292  __IO uint16_t SEL52;
39293  __IO uint16_t SEL53;
39294  __IO uint16_t SEL54;
39295  __IO uint16_t SEL55;
39296  __IO uint16_t SEL56;
39297  __IO uint16_t SEL57;
39298  __IO uint16_t SEL58;
39299  __IO uint16_t SEL59;
39300  __IO uint16_t SEL60;
39301  __IO uint16_t SEL61;
39302  __IO uint16_t SEL62;
39303  __IO uint16_t SEL63;
39304  __IO uint16_t SEL64;
39305  __IO uint16_t SEL65;
39306  __IO uint16_t CTRL0;
39307  __IO uint16_t CTRL1;
39308 } XBARA_Type;
39309 
39310 /* ----------------------------------------------------------------------------
39311  -- XBARA Register Masks
39312  ---------------------------------------------------------------------------- */
39313 
39321 #define XBARA_SEL0_SEL0_MASK (0x7FU)
39322 #define XBARA_SEL0_SEL0_SHIFT (0U)
39323 #define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
39324 #define XBARA_SEL0_SEL1_MASK (0x7F00U)
39325 #define XBARA_SEL0_SEL1_SHIFT (8U)
39326 #define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
39331 #define XBARA_SEL1_SEL2_MASK (0x7FU)
39332 #define XBARA_SEL1_SEL2_SHIFT (0U)
39333 #define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
39334 #define XBARA_SEL1_SEL3_MASK (0x7F00U)
39335 #define XBARA_SEL1_SEL3_SHIFT (8U)
39336 #define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
39341 #define XBARA_SEL2_SEL4_MASK (0x7FU)
39342 #define XBARA_SEL2_SEL4_SHIFT (0U)
39343 #define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
39344 #define XBARA_SEL2_SEL5_MASK (0x7F00U)
39345 #define XBARA_SEL2_SEL5_SHIFT (8U)
39346 #define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
39351 #define XBARA_SEL3_SEL6_MASK (0x7FU)
39352 #define XBARA_SEL3_SEL6_SHIFT (0U)
39353 #define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
39354 #define XBARA_SEL3_SEL7_MASK (0x7F00U)
39355 #define XBARA_SEL3_SEL7_SHIFT (8U)
39356 #define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
39361 #define XBARA_SEL4_SEL8_MASK (0x7FU)
39362 #define XBARA_SEL4_SEL8_SHIFT (0U)
39363 #define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
39364 #define XBARA_SEL4_SEL9_MASK (0x7F00U)
39365 #define XBARA_SEL4_SEL9_SHIFT (8U)
39366 #define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
39371 #define XBARA_SEL5_SEL10_MASK (0x7FU)
39372 #define XBARA_SEL5_SEL10_SHIFT (0U)
39373 #define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
39374 #define XBARA_SEL5_SEL11_MASK (0x7F00U)
39375 #define XBARA_SEL5_SEL11_SHIFT (8U)
39376 #define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
39381 #define XBARA_SEL6_SEL12_MASK (0x7FU)
39382 #define XBARA_SEL6_SEL12_SHIFT (0U)
39383 #define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
39384 #define XBARA_SEL6_SEL13_MASK (0x7F00U)
39385 #define XBARA_SEL6_SEL13_SHIFT (8U)
39386 #define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
39391 #define XBARA_SEL7_SEL14_MASK (0x7FU)
39392 #define XBARA_SEL7_SEL14_SHIFT (0U)
39393 #define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
39394 #define XBARA_SEL7_SEL15_MASK (0x7F00U)
39395 #define XBARA_SEL7_SEL15_SHIFT (8U)
39396 #define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
39401 #define XBARA_SEL8_SEL16_MASK (0x7FU)
39402 #define XBARA_SEL8_SEL16_SHIFT (0U)
39403 #define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
39404 #define XBARA_SEL8_SEL17_MASK (0x7F00U)
39405 #define XBARA_SEL8_SEL17_SHIFT (8U)
39406 #define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
39411 #define XBARA_SEL9_SEL18_MASK (0x7FU)
39412 #define XBARA_SEL9_SEL18_SHIFT (0U)
39413 #define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
39414 #define XBARA_SEL9_SEL19_MASK (0x7F00U)
39415 #define XBARA_SEL9_SEL19_SHIFT (8U)
39416 #define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
39421 #define XBARA_SEL10_SEL20_MASK (0x7FU)
39422 #define XBARA_SEL10_SEL20_SHIFT (0U)
39423 #define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
39424 #define XBARA_SEL10_SEL21_MASK (0x7F00U)
39425 #define XBARA_SEL10_SEL21_SHIFT (8U)
39426 #define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
39431 #define XBARA_SEL11_SEL22_MASK (0x7FU)
39432 #define XBARA_SEL11_SEL22_SHIFT (0U)
39433 #define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
39434 #define XBARA_SEL11_SEL23_MASK (0x7F00U)
39435 #define XBARA_SEL11_SEL23_SHIFT (8U)
39436 #define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
39441 #define XBARA_SEL12_SEL24_MASK (0x7FU)
39442 #define XBARA_SEL12_SEL24_SHIFT (0U)
39443 #define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
39444 #define XBARA_SEL12_SEL25_MASK (0x7F00U)
39445 #define XBARA_SEL12_SEL25_SHIFT (8U)
39446 #define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
39451 #define XBARA_SEL13_SEL26_MASK (0x7FU)
39452 #define XBARA_SEL13_SEL26_SHIFT (0U)
39453 #define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
39454 #define XBARA_SEL13_SEL27_MASK (0x7F00U)
39455 #define XBARA_SEL13_SEL27_SHIFT (8U)
39456 #define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
39461 #define XBARA_SEL14_SEL28_MASK (0x7FU)
39462 #define XBARA_SEL14_SEL28_SHIFT (0U)
39463 #define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
39464 #define XBARA_SEL14_SEL29_MASK (0x7F00U)
39465 #define XBARA_SEL14_SEL29_SHIFT (8U)
39466 #define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
39471 #define XBARA_SEL15_SEL30_MASK (0x7FU)
39472 #define XBARA_SEL15_SEL30_SHIFT (0U)
39473 #define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
39474 #define XBARA_SEL15_SEL31_MASK (0x7F00U)
39475 #define XBARA_SEL15_SEL31_SHIFT (8U)
39476 #define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
39481 #define XBARA_SEL16_SEL32_MASK (0x7FU)
39482 #define XBARA_SEL16_SEL32_SHIFT (0U)
39483 #define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
39484 #define XBARA_SEL16_SEL33_MASK (0x7F00U)
39485 #define XBARA_SEL16_SEL33_SHIFT (8U)
39486 #define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
39491 #define XBARA_SEL17_SEL34_MASK (0x7FU)
39492 #define XBARA_SEL17_SEL34_SHIFT (0U)
39493 #define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
39494 #define XBARA_SEL17_SEL35_MASK (0x7F00U)
39495 #define XBARA_SEL17_SEL35_SHIFT (8U)
39496 #define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
39501 #define XBARA_SEL18_SEL36_MASK (0x7FU)
39502 #define XBARA_SEL18_SEL36_SHIFT (0U)
39503 #define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
39504 #define XBARA_SEL18_SEL37_MASK (0x7F00U)
39505 #define XBARA_SEL18_SEL37_SHIFT (8U)
39506 #define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
39511 #define XBARA_SEL19_SEL38_MASK (0x7FU)
39512 #define XBARA_SEL19_SEL38_SHIFT (0U)
39513 #define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
39514 #define XBARA_SEL19_SEL39_MASK (0x7F00U)
39515 #define XBARA_SEL19_SEL39_SHIFT (8U)
39516 #define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
39521 #define XBARA_SEL20_SEL40_MASK (0x7FU)
39522 #define XBARA_SEL20_SEL40_SHIFT (0U)
39523 #define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
39524 #define XBARA_SEL20_SEL41_MASK (0x7F00U)
39525 #define XBARA_SEL20_SEL41_SHIFT (8U)
39526 #define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
39531 #define XBARA_SEL21_SEL42_MASK (0x7FU)
39532 #define XBARA_SEL21_SEL42_SHIFT (0U)
39533 #define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
39534 #define XBARA_SEL21_SEL43_MASK (0x7F00U)
39535 #define XBARA_SEL21_SEL43_SHIFT (8U)
39536 #define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
39541 #define XBARA_SEL22_SEL44_MASK (0x7FU)
39542 #define XBARA_SEL22_SEL44_SHIFT (0U)
39543 #define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
39544 #define XBARA_SEL22_SEL45_MASK (0x7F00U)
39545 #define XBARA_SEL22_SEL45_SHIFT (8U)
39546 #define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
39551 #define XBARA_SEL23_SEL46_MASK (0x7FU)
39552 #define XBARA_SEL23_SEL46_SHIFT (0U)
39553 #define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
39554 #define XBARA_SEL23_SEL47_MASK (0x7F00U)
39555 #define XBARA_SEL23_SEL47_SHIFT (8U)
39556 #define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
39561 #define XBARA_SEL24_SEL48_MASK (0x7FU)
39562 #define XBARA_SEL24_SEL48_SHIFT (0U)
39563 #define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
39564 #define XBARA_SEL24_SEL49_MASK (0x7F00U)
39565 #define XBARA_SEL24_SEL49_SHIFT (8U)
39566 #define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
39571 #define XBARA_SEL25_SEL50_MASK (0x7FU)
39572 #define XBARA_SEL25_SEL50_SHIFT (0U)
39573 #define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
39574 #define XBARA_SEL25_SEL51_MASK (0x7F00U)
39575 #define XBARA_SEL25_SEL51_SHIFT (8U)
39576 #define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
39581 #define XBARA_SEL26_SEL52_MASK (0x7FU)
39582 #define XBARA_SEL26_SEL52_SHIFT (0U)
39583 #define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
39584 #define XBARA_SEL26_SEL53_MASK (0x7F00U)
39585 #define XBARA_SEL26_SEL53_SHIFT (8U)
39586 #define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
39591 #define XBARA_SEL27_SEL54_MASK (0x7FU)
39592 #define XBARA_SEL27_SEL54_SHIFT (0U)
39593 #define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
39594 #define XBARA_SEL27_SEL55_MASK (0x7F00U)
39595 #define XBARA_SEL27_SEL55_SHIFT (8U)
39596 #define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
39601 #define XBARA_SEL28_SEL56_MASK (0x7FU)
39602 #define XBARA_SEL28_SEL56_SHIFT (0U)
39603 #define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
39604 #define XBARA_SEL28_SEL57_MASK (0x7F00U)
39605 #define XBARA_SEL28_SEL57_SHIFT (8U)
39606 #define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
39611 #define XBARA_SEL29_SEL58_MASK (0x7FU)
39612 #define XBARA_SEL29_SEL58_SHIFT (0U)
39613 #define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
39614 #define XBARA_SEL29_SEL59_MASK (0x7F00U)
39615 #define XBARA_SEL29_SEL59_SHIFT (8U)
39616 #define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
39621 #define XBARA_SEL30_SEL60_MASK (0x7FU)
39622 #define XBARA_SEL30_SEL60_SHIFT (0U)
39623 #define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
39624 #define XBARA_SEL30_SEL61_MASK (0x7F00U)
39625 #define XBARA_SEL30_SEL61_SHIFT (8U)
39626 #define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
39631 #define XBARA_SEL31_SEL62_MASK (0x7FU)
39632 #define XBARA_SEL31_SEL62_SHIFT (0U)
39633 #define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
39634 #define XBARA_SEL31_SEL63_MASK (0x7F00U)
39635 #define XBARA_SEL31_SEL63_SHIFT (8U)
39636 #define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
39641 #define XBARA_SEL32_SEL64_MASK (0x7FU)
39642 #define XBARA_SEL32_SEL64_SHIFT (0U)
39643 #define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
39644 #define XBARA_SEL32_SEL65_MASK (0x7F00U)
39645 #define XBARA_SEL32_SEL65_SHIFT (8U)
39646 #define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
39651 #define XBARA_SEL33_SEL66_MASK (0x7FU)
39652 #define XBARA_SEL33_SEL66_SHIFT (0U)
39653 #define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
39654 #define XBARA_SEL33_SEL67_MASK (0x7F00U)
39655 #define XBARA_SEL33_SEL67_SHIFT (8U)
39656 #define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
39661 #define XBARA_SEL34_SEL68_MASK (0x7FU)
39662 #define XBARA_SEL34_SEL68_SHIFT (0U)
39663 #define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
39664 #define XBARA_SEL34_SEL69_MASK (0x7F00U)
39665 #define XBARA_SEL34_SEL69_SHIFT (8U)
39666 #define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
39671 #define XBARA_SEL35_SEL70_MASK (0x7FU)
39672 #define XBARA_SEL35_SEL70_SHIFT (0U)
39673 #define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
39674 #define XBARA_SEL35_SEL71_MASK (0x7F00U)
39675 #define XBARA_SEL35_SEL71_SHIFT (8U)
39676 #define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
39681 #define XBARA_SEL36_SEL72_MASK (0x7FU)
39682 #define XBARA_SEL36_SEL72_SHIFT (0U)
39683 #define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
39684 #define XBARA_SEL36_SEL73_MASK (0x7F00U)
39685 #define XBARA_SEL36_SEL73_SHIFT (8U)
39686 #define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
39691 #define XBARA_SEL37_SEL74_MASK (0x7FU)
39692 #define XBARA_SEL37_SEL74_SHIFT (0U)
39693 #define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
39694 #define XBARA_SEL37_SEL75_MASK (0x7F00U)
39695 #define XBARA_SEL37_SEL75_SHIFT (8U)
39696 #define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
39701 #define XBARA_SEL38_SEL76_MASK (0x7FU)
39702 #define XBARA_SEL38_SEL76_SHIFT (0U)
39703 #define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
39704 #define XBARA_SEL38_SEL77_MASK (0x7F00U)
39705 #define XBARA_SEL38_SEL77_SHIFT (8U)
39706 #define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
39711 #define XBARA_SEL39_SEL78_MASK (0x7FU)
39712 #define XBARA_SEL39_SEL78_SHIFT (0U)
39713 #define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
39714 #define XBARA_SEL39_SEL79_MASK (0x7F00U)
39715 #define XBARA_SEL39_SEL79_SHIFT (8U)
39716 #define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
39721 #define XBARA_SEL40_SEL80_MASK (0x7FU)
39722 #define XBARA_SEL40_SEL80_SHIFT (0U)
39723 #define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
39724 #define XBARA_SEL40_SEL81_MASK (0x7F00U)
39725 #define XBARA_SEL40_SEL81_SHIFT (8U)
39726 #define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
39731 #define XBARA_SEL41_SEL82_MASK (0x7FU)
39732 #define XBARA_SEL41_SEL82_SHIFT (0U)
39733 #define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
39734 #define XBARA_SEL41_SEL83_MASK (0x7F00U)
39735 #define XBARA_SEL41_SEL83_SHIFT (8U)
39736 #define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
39741 #define XBARA_SEL42_SEL84_MASK (0x7FU)
39742 #define XBARA_SEL42_SEL84_SHIFT (0U)
39743 #define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
39744 #define XBARA_SEL42_SEL85_MASK (0x7F00U)
39745 #define XBARA_SEL42_SEL85_SHIFT (8U)
39746 #define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
39751 #define XBARA_SEL43_SEL86_MASK (0x7FU)
39752 #define XBARA_SEL43_SEL86_SHIFT (0U)
39753 #define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
39754 #define XBARA_SEL43_SEL87_MASK (0x7F00U)
39755 #define XBARA_SEL43_SEL87_SHIFT (8U)
39756 #define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
39761 #define XBARA_SEL44_SEL88_MASK (0x7FU)
39762 #define XBARA_SEL44_SEL88_SHIFT (0U)
39763 #define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
39764 #define XBARA_SEL44_SEL89_MASK (0x7F00U)
39765 #define XBARA_SEL44_SEL89_SHIFT (8U)
39766 #define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
39771 #define XBARA_SEL45_SEL90_MASK (0x7FU)
39772 #define XBARA_SEL45_SEL90_SHIFT (0U)
39773 #define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
39774 #define XBARA_SEL45_SEL91_MASK (0x7F00U)
39775 #define XBARA_SEL45_SEL91_SHIFT (8U)
39776 #define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
39781 #define XBARA_SEL46_SEL92_MASK (0x7FU)
39782 #define XBARA_SEL46_SEL92_SHIFT (0U)
39783 #define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
39784 #define XBARA_SEL46_SEL93_MASK (0x7F00U)
39785 #define XBARA_SEL46_SEL93_SHIFT (8U)
39786 #define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
39791 #define XBARA_SEL47_SEL94_MASK (0x7FU)
39792 #define XBARA_SEL47_SEL94_SHIFT (0U)
39793 #define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
39794 #define XBARA_SEL47_SEL95_MASK (0x7F00U)
39795 #define XBARA_SEL47_SEL95_SHIFT (8U)
39796 #define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
39801 #define XBARA_SEL48_SEL96_MASK (0x7FU)
39802 #define XBARA_SEL48_SEL96_SHIFT (0U)
39803 #define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
39804 #define XBARA_SEL48_SEL97_MASK (0x7F00U)
39805 #define XBARA_SEL48_SEL97_SHIFT (8U)
39806 #define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
39811 #define XBARA_SEL49_SEL98_MASK (0x7FU)
39812 #define XBARA_SEL49_SEL98_SHIFT (0U)
39813 #define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
39814 #define XBARA_SEL49_SEL99_MASK (0x7F00U)
39815 #define XBARA_SEL49_SEL99_SHIFT (8U)
39816 #define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
39821 #define XBARA_SEL50_SEL100_MASK (0x7FU)
39822 #define XBARA_SEL50_SEL100_SHIFT (0U)
39823 #define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
39824 #define XBARA_SEL50_SEL101_MASK (0x7F00U)
39825 #define XBARA_SEL50_SEL101_SHIFT (8U)
39826 #define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
39831 #define XBARA_SEL51_SEL102_MASK (0x7FU)
39832 #define XBARA_SEL51_SEL102_SHIFT (0U)
39833 #define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
39834 #define XBARA_SEL51_SEL103_MASK (0x7F00U)
39835 #define XBARA_SEL51_SEL103_SHIFT (8U)
39836 #define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
39841 #define XBARA_SEL52_SEL104_MASK (0x7FU)
39842 #define XBARA_SEL52_SEL104_SHIFT (0U)
39843 #define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
39844 #define XBARA_SEL52_SEL105_MASK (0x7F00U)
39845 #define XBARA_SEL52_SEL105_SHIFT (8U)
39846 #define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
39851 #define XBARA_SEL53_SEL106_MASK (0x7FU)
39852 #define XBARA_SEL53_SEL106_SHIFT (0U)
39853 #define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
39854 #define XBARA_SEL53_SEL107_MASK (0x7F00U)
39855 #define XBARA_SEL53_SEL107_SHIFT (8U)
39856 #define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
39861 #define XBARA_SEL54_SEL108_MASK (0x7FU)
39862 #define XBARA_SEL54_SEL108_SHIFT (0U)
39863 #define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
39864 #define XBARA_SEL54_SEL109_MASK (0x7F00U)
39865 #define XBARA_SEL54_SEL109_SHIFT (8U)
39866 #define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
39871 #define XBARA_SEL55_SEL110_MASK (0x7FU)
39872 #define XBARA_SEL55_SEL110_SHIFT (0U)
39873 #define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
39874 #define XBARA_SEL55_SEL111_MASK (0x7F00U)
39875 #define XBARA_SEL55_SEL111_SHIFT (8U)
39876 #define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
39881 #define XBARA_SEL56_SEL112_MASK (0x7FU)
39882 #define XBARA_SEL56_SEL112_SHIFT (0U)
39883 #define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
39884 #define XBARA_SEL56_SEL113_MASK (0x7F00U)
39885 #define XBARA_SEL56_SEL113_SHIFT (8U)
39886 #define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
39891 #define XBARA_SEL57_SEL114_MASK (0x7FU)
39892 #define XBARA_SEL57_SEL114_SHIFT (0U)
39893 #define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
39894 #define XBARA_SEL57_SEL115_MASK (0x7F00U)
39895 #define XBARA_SEL57_SEL115_SHIFT (8U)
39896 #define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
39901 #define XBARA_SEL58_SEL116_MASK (0x7FU)
39902 #define XBARA_SEL58_SEL116_SHIFT (0U)
39903 #define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
39904 #define XBARA_SEL58_SEL117_MASK (0x7F00U)
39905 #define XBARA_SEL58_SEL117_SHIFT (8U)
39906 #define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
39911 #define XBARA_SEL59_SEL118_MASK (0x7FU)
39912 #define XBARA_SEL59_SEL118_SHIFT (0U)
39913 #define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
39914 #define XBARA_SEL59_SEL119_MASK (0x7F00U)
39915 #define XBARA_SEL59_SEL119_SHIFT (8U)
39916 #define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
39921 #define XBARA_SEL60_SEL120_MASK (0x7FU)
39922 #define XBARA_SEL60_SEL120_SHIFT (0U)
39923 #define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
39924 #define XBARA_SEL60_SEL121_MASK (0x7F00U)
39925 #define XBARA_SEL60_SEL121_SHIFT (8U)
39926 #define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
39931 #define XBARA_SEL61_SEL122_MASK (0x7FU)
39932 #define XBARA_SEL61_SEL122_SHIFT (0U)
39933 #define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
39934 #define XBARA_SEL61_SEL123_MASK (0x7F00U)
39935 #define XBARA_SEL61_SEL123_SHIFT (8U)
39936 #define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
39941 #define XBARA_SEL62_SEL124_MASK (0x7FU)
39942 #define XBARA_SEL62_SEL124_SHIFT (0U)
39943 #define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
39944 #define XBARA_SEL62_SEL125_MASK (0x7F00U)
39945 #define XBARA_SEL62_SEL125_SHIFT (8U)
39946 #define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
39951 #define XBARA_SEL63_SEL126_MASK (0x7FU)
39952 #define XBARA_SEL63_SEL126_SHIFT (0U)
39953 #define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
39954 #define XBARA_SEL63_SEL127_MASK (0x7F00U)
39955 #define XBARA_SEL63_SEL127_SHIFT (8U)
39956 #define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
39961 #define XBARA_SEL64_SEL128_MASK (0x7FU)
39962 #define XBARA_SEL64_SEL128_SHIFT (0U)
39963 #define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
39964 #define XBARA_SEL64_SEL129_MASK (0x7F00U)
39965 #define XBARA_SEL64_SEL129_SHIFT (8U)
39966 #define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
39971 #define XBARA_SEL65_SEL130_MASK (0x7FU)
39972 #define XBARA_SEL65_SEL130_SHIFT (0U)
39973 #define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
39974 #define XBARA_SEL65_SEL131_MASK (0x7F00U)
39975 #define XBARA_SEL65_SEL131_SHIFT (8U)
39976 #define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
39981 #define XBARA_CTRL0_DEN0_MASK (0x1U)
39982 #define XBARA_CTRL0_DEN0_SHIFT (0U)
39987 #define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
39988 #define XBARA_CTRL0_IEN0_MASK (0x2U)
39989 #define XBARA_CTRL0_IEN0_SHIFT (1U)
39994 #define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
39995 #define XBARA_CTRL0_EDGE0_MASK (0xCU)
39996 #define XBARA_CTRL0_EDGE0_SHIFT (2U)
40003 #define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
40004 #define XBARA_CTRL0_STS0_MASK (0x10U)
40005 #define XBARA_CTRL0_STS0_SHIFT (4U)
40010 #define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
40011 #define XBARA_CTRL0_DEN1_MASK (0x100U)
40012 #define XBARA_CTRL0_DEN1_SHIFT (8U)
40017 #define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
40018 #define XBARA_CTRL0_IEN1_MASK (0x200U)
40019 #define XBARA_CTRL0_IEN1_SHIFT (9U)
40024 #define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
40025 #define XBARA_CTRL0_EDGE1_MASK (0xC00U)
40026 #define XBARA_CTRL0_EDGE1_SHIFT (10U)
40033 #define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
40034 #define XBARA_CTRL0_STS1_MASK (0x1000U)
40035 #define XBARA_CTRL0_STS1_SHIFT (12U)
40040 #define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
40045 #define XBARA_CTRL1_DEN2_MASK (0x1U)
40046 #define XBARA_CTRL1_DEN2_SHIFT (0U)
40051 #define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
40052 #define XBARA_CTRL1_IEN2_MASK (0x2U)
40053 #define XBARA_CTRL1_IEN2_SHIFT (1U)
40058 #define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
40059 #define XBARA_CTRL1_EDGE2_MASK (0xCU)
40060 #define XBARA_CTRL1_EDGE2_SHIFT (2U)
40067 #define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
40068 #define XBARA_CTRL1_STS2_MASK (0x10U)
40069 #define XBARA_CTRL1_STS2_SHIFT (4U)
40074 #define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
40075 #define XBARA_CTRL1_DEN3_MASK (0x100U)
40076 #define XBARA_CTRL1_DEN3_SHIFT (8U)
40081 #define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
40082 #define XBARA_CTRL1_IEN3_MASK (0x200U)
40083 #define XBARA_CTRL1_IEN3_SHIFT (9U)
40088 #define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
40089 #define XBARA_CTRL1_EDGE3_MASK (0xC00U)
40090 #define XBARA_CTRL1_EDGE3_SHIFT (10U)
40097 #define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
40098 #define XBARA_CTRL1_STS3_MASK (0x1000U)
40099 #define XBARA_CTRL1_STS3_SHIFT (12U)
40104 #define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) /* end of group XBARA_Register_Masks */
40111 
40112 
40113 /* XBARA - Peripheral instance base addresses */
40115 #define XBARA_BASE (0x403BC000u)
40117 #define XBARA ((XBARA_Type *)XBARA_BASE)
40119 #define XBARA_BASE_ADDRS { XBARA_BASE }
40121 #define XBARA_BASE_PTRS { XBARA }
40122  /* end of group XBARA_Peripheral_Access_Layer */
40126 
40127 
40128 /* ----------------------------------------------------------------------------
40129  -- XBARB Peripheral Access Layer
40130  ---------------------------------------------------------------------------- */
40131 
40138 typedef struct {
40139  __IO uint16_t SEL0;
40140  __IO uint16_t SEL1;
40141  __IO uint16_t SEL2;
40142  __IO uint16_t SEL3;
40143  __IO uint16_t SEL4;
40144  __IO uint16_t SEL5;
40145  __IO uint16_t SEL6;
40146  __IO uint16_t SEL7;
40147 } XBARB_Type;
40148 
40149 /* ----------------------------------------------------------------------------
40150  -- XBARB Register Masks
40151  ---------------------------------------------------------------------------- */
40152 
40160 #define XBARB_SEL0_SEL0_MASK (0x3FU)
40161 #define XBARB_SEL0_SEL0_SHIFT (0U)
40162 #define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
40163 #define XBARB_SEL0_SEL1_MASK (0x3F00U)
40164 #define XBARB_SEL0_SEL1_SHIFT (8U)
40165 #define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
40170 #define XBARB_SEL1_SEL2_MASK (0x3FU)
40171 #define XBARB_SEL1_SEL2_SHIFT (0U)
40172 #define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
40173 #define XBARB_SEL1_SEL3_MASK (0x3F00U)
40174 #define XBARB_SEL1_SEL3_SHIFT (8U)
40175 #define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
40180 #define XBARB_SEL2_SEL4_MASK (0x3FU)
40181 #define XBARB_SEL2_SEL4_SHIFT (0U)
40182 #define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
40183 #define XBARB_SEL2_SEL5_MASK (0x3F00U)
40184 #define XBARB_SEL2_SEL5_SHIFT (8U)
40185 #define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
40190 #define XBARB_SEL3_SEL6_MASK (0x3FU)
40191 #define XBARB_SEL3_SEL6_SHIFT (0U)
40192 #define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
40193 #define XBARB_SEL3_SEL7_MASK (0x3F00U)
40194 #define XBARB_SEL3_SEL7_SHIFT (8U)
40195 #define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
40200 #define XBARB_SEL4_SEL8_MASK (0x3FU)
40201 #define XBARB_SEL4_SEL8_SHIFT (0U)
40202 #define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
40203 #define XBARB_SEL4_SEL9_MASK (0x3F00U)
40204 #define XBARB_SEL4_SEL9_SHIFT (8U)
40205 #define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
40210 #define XBARB_SEL5_SEL10_MASK (0x3FU)
40211 #define XBARB_SEL5_SEL10_SHIFT (0U)
40212 #define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
40213 #define XBARB_SEL5_SEL11_MASK (0x3F00U)
40214 #define XBARB_SEL5_SEL11_SHIFT (8U)
40215 #define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
40220 #define XBARB_SEL6_SEL12_MASK (0x3FU)
40221 #define XBARB_SEL6_SEL12_SHIFT (0U)
40222 #define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
40223 #define XBARB_SEL6_SEL13_MASK (0x3F00U)
40224 #define XBARB_SEL6_SEL13_SHIFT (8U)
40225 #define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
40230 #define XBARB_SEL7_SEL14_MASK (0x3FU)
40231 #define XBARB_SEL7_SEL14_SHIFT (0U)
40232 #define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
40233 #define XBARB_SEL7_SEL15_MASK (0x3F00U)
40234 #define XBARB_SEL7_SEL15_SHIFT (8U)
40235 #define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) /* end of group XBARB_Register_Masks */
40242 
40243 
40244 /* XBARB - Peripheral instance base addresses */
40246 #define XBARB_BASE (0x403C0000u)
40248 #define XBARB ((XBARB_Type *)XBARB_BASE)
40250 #define XBARB_BASE_ADDRS { XBARB_BASE }
40252 #define XBARB_BASE_PTRS { XBARB }
40253  /* end of group XBARB_Peripheral_Access_Layer */
40257 
40258 
40259 /* ----------------------------------------------------------------------------
40260  -- XTALOSC24M Peripheral Access Layer
40261  ---------------------------------------------------------------------------- */
40262 
40269 typedef struct {
40270  uint8_t RESERVED_0[336];
40271  __IO uint32_t MISC0;
40272  __IO uint32_t MISC0_SET;
40273  __IO uint32_t MISC0_CLR;
40274  __IO uint32_t MISC0_TOG;
40275  uint8_t RESERVED_1[272];
40276  __IO uint32_t LOWPWR_CTRL;
40277  __IO uint32_t LOWPWR_CTRL_SET;
40278  __IO uint32_t LOWPWR_CTRL_CLR;
40279  __IO uint32_t LOWPWR_CTRL_TOG;
40280  uint8_t RESERVED_2[32];
40281  __IO uint32_t OSC_CONFIG0;
40282  __IO uint32_t OSC_CONFIG0_SET;
40283  __IO uint32_t OSC_CONFIG0_CLR;
40284  __IO uint32_t OSC_CONFIG0_TOG;
40285  __IO uint32_t OSC_CONFIG1;
40286  __IO uint32_t OSC_CONFIG1_SET;
40287  __IO uint32_t OSC_CONFIG1_CLR;
40288  __IO uint32_t OSC_CONFIG1_TOG;
40289  __IO uint32_t OSC_CONFIG2;
40290  __IO uint32_t OSC_CONFIG2_SET;
40291  __IO uint32_t OSC_CONFIG2_CLR;
40292  __IO uint32_t OSC_CONFIG2_TOG;
40293 } XTALOSC24M_Type;
40294 
40295 /* ----------------------------------------------------------------------------
40296  -- XTALOSC24M Register Masks
40297  ---------------------------------------------------------------------------- */
40298 
40306 #define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
40307 #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
40308 #define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
40309 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
40310 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
40315 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
40316 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
40317 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
40328 #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
40329 #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
40330 #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
40331 #define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
40332 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
40333 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
40340 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
40341 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
40342 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
40347 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
40348 #define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
40349 #define XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
40356 #define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
40357 #define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
40358 #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
40359 #define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
40360 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
40361 #define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
40362 #define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
40363 #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
40364 #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
40369 #define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
40370 #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
40371 #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
40382 #define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
40383 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
40384 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
40389 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
40390 #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
40391 #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
40392 #define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
40393 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
40394 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
40399 #define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
40404 #define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
40405 #define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
40406 #define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
40407 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
40408 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
40413 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
40414 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
40415 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
40426 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
40427 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
40428 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
40429 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
40430 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
40431 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
40438 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
40439 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
40440 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
40445 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
40446 #define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
40447 #define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
40454 #define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
40455 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
40456 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
40457 #define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
40458 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
40459 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
40460 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
40461 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
40462 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
40467 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
40468 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
40469 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
40480 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
40481 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
40482 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
40487 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
40488 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
40489 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
40490 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
40491 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
40492 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
40497 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
40502 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
40503 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
40504 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
40505 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
40506 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
40511 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
40512 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
40513 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
40524 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
40525 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
40526 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
40527 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
40528 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
40529 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
40536 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
40537 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
40538 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
40543 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
40544 #define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
40545 #define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
40552 #define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
40553 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
40554 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
40555 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
40556 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
40557 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
40558 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
40559 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
40560 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
40565 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
40566 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
40567 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
40578 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
40579 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
40580 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
40585 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
40586 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
40587 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
40588 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
40589 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
40590 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
40595 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
40600 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
40601 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
40602 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
40603 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
40604 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
40609 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
40610 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
40611 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
40622 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
40623 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
40624 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
40625 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
40626 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
40627 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
40634 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
40635 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
40636 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
40641 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
40642 #define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
40643 #define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
40650 #define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
40651 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
40652 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
40653 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
40654 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
40655 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
40656 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
40657 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
40658 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
40663 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
40664 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
40665 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
40676 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
40677 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
40678 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
40683 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
40684 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
40685 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
40686 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
40687 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
40688 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
40693 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
40698 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
40699 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
40704 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
40705 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
40706 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
40711 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
40712 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
40713 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
40718 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
40719 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
40720 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
40721 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
40722 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
40723 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
40724 #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
40725 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
40726 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
40727 #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
40728 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
40729 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
40730 #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
40731 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
40732 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
40733 #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
40734 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
40735 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
40736 #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
40737 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
40738 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
40739 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
40740 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
40741 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
40748 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
40749 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
40750 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
40755 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
40756 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
40757 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
40758 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
40759 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
40760 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
40761 #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
40766 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
40767 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
40772 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
40773 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
40774 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
40779 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
40780 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
40781 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
40786 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
40787 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
40788 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
40789 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
40790 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
40791 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
40792 #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
40793 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
40794 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
40795 #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
40796 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
40797 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
40798 #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
40799 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
40800 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
40801 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
40802 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
40803 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
40804 #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
40805 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
40806 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
40807 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
40808 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
40809 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
40816 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
40817 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
40818 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
40823 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
40824 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
40825 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
40826 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
40827 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
40828 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
40829 #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
40834 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
40835 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
40840 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
40841 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
40842 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
40847 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
40848 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
40849 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
40854 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
40855 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
40856 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
40857 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
40858 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
40859 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
40860 #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
40861 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
40862 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
40863 #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
40864 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
40865 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
40866 #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
40867 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
40868 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
40869 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
40870 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
40871 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
40872 #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
40873 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
40874 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
40875 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
40876 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
40877 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
40884 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
40885 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
40886 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
40891 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
40892 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
40893 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
40894 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
40895 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
40896 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
40897 #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
40902 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
40903 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
40908 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
40909 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
40910 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
40915 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
40916 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
40917 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
40922 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
40923 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
40924 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
40925 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
40926 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
40927 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
40928 #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
40929 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
40930 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
40931 #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
40932 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
40933 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
40934 #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
40935 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
40936 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
40937 #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
40938 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
40939 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
40940 #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
40941 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
40942 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
40943 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
40944 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
40945 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
40952 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
40953 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
40954 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
40959 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
40960 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
40961 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
40962 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
40963 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
40964 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
40965 #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
40970 #define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
40971 #define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
40972 #define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
40973 #define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
40974 #define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
40975 #define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
40976 #define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
40977 #define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
40978 #define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
40979 #define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
40980 #define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
40981 #define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
40982 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
40983 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
40984 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
40985 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
40986 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
40987 #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
40988 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
40989 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
40990 #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
40991 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
40992 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
40993 #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
40998 #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
40999 #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
41000 #define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
41001 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
41002 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
41003 #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
41004 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
41005 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
41006 #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
41007 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
41008 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
41009 #define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
41010 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
41011 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
41012 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
41013 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
41014 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
41015 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
41016 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
41017 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
41018 #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
41019 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
41020 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
41021 #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
41026 #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
41027 #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
41028 #define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
41029 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
41030 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
41031 #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
41032 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
41033 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
41034 #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
41035 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
41036 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
41037 #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
41038 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
41039 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
41040 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
41041 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
41042 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
41043 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
41044 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
41045 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
41046 #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
41047 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
41048 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
41049 #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
41054 #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
41055 #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
41056 #define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
41057 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
41058 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
41059 #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
41060 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
41061 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
41062 #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
41063 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
41064 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
41065 #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
41066 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
41067 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
41068 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
41069 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
41070 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
41071 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
41072 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
41073 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
41074 #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
41075 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
41076 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
41077 #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
41082 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
41083 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
41084 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
41085 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
41086 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
41087 #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
41092 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
41093 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
41094 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
41095 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
41096 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
41097 #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
41102 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
41103 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
41104 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
41105 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
41106 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
41107 #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
41112 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
41113 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
41114 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
41115 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
41116 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
41117 #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
41122 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
41123 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
41124 #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
41125 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
41126 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
41127 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
41128 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
41129 #define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
41130 #define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
41131 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
41132 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
41133 #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
41138 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
41139 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
41140 #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
41141 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
41142 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
41143 #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
41144 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
41145 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
41146 #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
41147 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
41148 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
41149 #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
41154 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
41155 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
41156 #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
41157 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
41158 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
41159 #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
41160 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
41161 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
41162 #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
41163 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
41164 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
41165 #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
41170 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
41171 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
41172 #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
41173 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
41174 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
41175 #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
41176 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
41177 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
41178 #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
41179 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
41180 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
41181 #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) /* end of group XTALOSC24M_Register_Masks */
41188 
41189 
41190 /* XTALOSC24M - Peripheral instance base addresses */
41192 #define XTALOSC24M_BASE (0x400D8000u)
41194 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)
41196 #define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }
41198 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
41199  /* end of group XTALOSC24M_Peripheral_Access_Layer */
41203 
41204 
41205 /*
41206 ** End of section using anonymous unions
41207 */
41208 
41209 #if defined(__ARMCC_VERSION)
41210  #if (__ARMCC_VERSION >= 6010050)
41211  #pragma clang diagnostic pop
41212  #else
41213  #pragma pop
41214  #endif
41215 #elif defined(__CWCC__)
41216  #pragma pop
41217 #elif defined(__GNUC__)
41218  /* leave anonymous unions enabled */
41219 #elif defined(__IAR_SYSTEMS_ICC__)
41220  #pragma language=default
41221 #else
41222  #error Not supported compiler type
41223 #endif
41224  /* end of group Peripheral_access_layer */
41228 
41229 
41230 /* ----------------------------------------------------------------------------
41231  -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
41232  ---------------------------------------------------------------------------- */
41233 
41239 #if defined(__ARMCC_VERSION)
41240  #if (__ARMCC_VERSION >= 6010050)
41241  #pragma clang system_header
41242  #endif
41243 #elif defined(__IAR_SYSTEMS_ICC__)
41244  #pragma system_include
41245 #endif
41246 
41253 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
41260 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
41261  /* end of group Bit_Field_Generic_Macros */
41265 
41266 
41267 /* ----------------------------------------------------------------------------
41268  -- SDK Compatibility
41269  ---------------------------------------------------------------------------- */
41270 
41276 /* No SDK compatibility issues. */
41277  /* end of group SDK_Compatibility_Symbols */
41281 
41282 
41283 #endif /* _MIMXRT1021_H_ */
41284 
IRQn
IRQn
Definition: MIMXRT1021.h:72
PWM2_2_IRQn
@ PWM2_2_IRQn
Definition: MIMXRT1021.h:227
PendSV_IRQn
@ PendSV_IRQn
Definition: MIMXRT1021.h:84
Reserved148_IRQn
@ Reserved148_IRQn
Definition: MIMXRT1021.h:220
LPI2C1_IRQn
@ LPI2C1_IRQn
Definition: MIMXRT1021.h:116
PWM1_0_IRQn
@ PWM1_0_IRQn
Definition: MIMXRT1021.h:190
USB_PHY_IRQn
@ USB_PHY_IRQn
Definition: MIMXRT1021.h:153
Reserved60_IRQn
@ Reserved60_IRQn
Definition: MIMXRT1021.h:132
Reserved107_IRQn
@ Reserved107_IRQn
Definition: MIMXRT1021.h:179
ADC_ETC_ERROR_IRQ_IRQn
@ ADC_ETC_ERROR_IRQ_IRQn
Definition: MIMXRT1021.h:209
GPIO3_Combined_0_15_IRQn
@ GPIO3_Combined_0_15_IRQn
Definition: MIMXRT1021.h:172
Reserved103_IRQn
@ Reserved103_IRQn
Definition: MIMXRT1021.h:175
DMA0_DMA16_IRQn
@ DMA0_DMA16_IRQn
Definition: MIMXRT1021.h:88
Reserved152_IRQn
@ Reserved152_IRQn
Definition: MIMXRT1021.h:224
GPIO1_INT0_IRQn
@ GPIO1_INT0_IRQn
Definition: MIMXRT1021.h:160
DMA14_DMA30_IRQn
@ DMA14_DMA30_IRQn
Definition: MIMXRT1021.h:102
NotAvail_IRQn
@ NotAvail_IRQn
Definition: MIMXRT1021.h:74
Reserved151_IRQn
@ Reserved151_IRQn
Definition: MIMXRT1021.h:223
DMA13_DMA29_IRQn
@ DMA13_DMA29_IRQn
Definition: MIMXRT1021.h:101
USDHC1_IRQn
@ USDHC1_IRQn
Definition: MIMXRT1021.h:198
CORE_IRQn
@ CORE_IRQn
Definition: MIMXRT1021.h:107
SNVS_HP_WRAPPER_TZ_IRQn
@ SNVS_HP_WRAPPER_TZ_IRQn
Definition: MIMXRT1021.h:135
KPP_IRQn
@ KPP_IRQn
Definition: MIMXRT1021.h:127
GPIO1_INT2_IRQn
@ GPIO1_INT2_IRQn
Definition: MIMXRT1021.h:162
SEMC_IRQn
@ SEMC_IRQn
Definition: MIMXRT1021.h:197
ACMP3_IRQn
@ ACMP3_IRQn
Definition: MIMXRT1021.h:213
FLEXSPI_IRQn
@ FLEXSPI_IRQn
Definition: MIMXRT1021.h:196
PWM2_1_IRQn
@ PWM2_1_IRQn
Definition: MIMXRT1021.h:226
CCM_2_IRQn
@ CCM_2_IRQn
Definition: MIMXRT1021.h:184
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: MIMXRT1021.h:79
GPIO5_Combined_0_15_IRQn
@ GPIO5_Combined_0_15_IRQn
Definition: MIMXRT1021.h:176
ADC1_IRQn
@ ADC1_IRQn
Definition: MIMXRT1021.h:155
SAI1_IRQn
@ SAI1_IRQn
Definition: MIMXRT1021.h:144
LPUART2_IRQn
@ LPUART2_IRQn
Definition: MIMXRT1021.h:109
GPT1_IRQn
@ GPT1_IRQn
Definition: MIMXRT1021.h:188
Reserved102_IRQn
@ Reserved102_IRQn
Definition: MIMXRT1021.h:174
LPI2C4_IRQn
@ LPI2C4_IRQn
Definition: MIMXRT1021.h:119
DMA15_DMA31_IRQn
@ DMA15_DMA31_IRQn
Definition: MIMXRT1021.h:103
ACMP1_IRQn
@ ACMP1_IRQn
Definition: MIMXRT1021.h:211
PWM1_1_IRQn
@ PWM1_1_IRQn
Definition: MIMXRT1021.h:191
Reserved128_IRQn
@ Reserved128_IRQn
Definition: MIMXRT1021.h:200
GPIO1_INT4_IRQn
@ GPIO1_INT4_IRQn
Definition: MIMXRT1021.h:164
Reserved68_IRQn
@ Reserved68_IRQn
Definition: MIMXRT1021.h:140
PWM2_3_IRQn
@ PWM2_3_IRQn
Definition: MIMXRT1021.h:228
RTWDOG_IRQn
@ RTWDOG_IRQn
Definition: MIMXRT1021.h:181
CTI0_ERROR_IRQn
@ CTI0_ERROR_IRQn
Definition: MIMXRT1021.h:105
Reserved78_IRQn
@ Reserved78_IRQn
Definition: MIMXRT1021.h:150
GPIO1_INT1_IRQn
@ GPIO1_INT1_IRQn
Definition: MIMXRT1021.h:161
PWM1_FAULT_IRQn
@ PWM1_FAULT_IRQn
Definition: MIMXRT1021.h:194
SVCall_IRQn
@ SVCall_IRQn
Definition: MIMXRT1021.h:82
DMA_ERROR_IRQn
@ DMA_ERROR_IRQn
Definition: MIMXRT1021.h:104
DMA10_DMA26_IRQn
@ DMA10_DMA26_IRQn
Definition: MIMXRT1021.h:98
BEE_IRQn
@ BEE_IRQn
Definition: MIMXRT1021.h:143
Reserved70_IRQn
@ Reserved70_IRQn
Definition: MIMXRT1021.h:142
SNVS_LP_HP_WRAPPER_IRQn
@ SNVS_LP_HP_WRAPPER_IRQn
Definition: MIMXRT1021.h:136
TEMP_PANIC_IRQn
@ TEMP_PANIC_IRQn
Definition: MIMXRT1021.h:152
LPUART7_IRQn
@ LPUART7_IRQn
Definition: MIMXRT1021.h:114
SAI3_RX_IRQn
@ SAI3_RX_IRQn
Definition: MIMXRT1021.h:146
DMA5_DMA21_IRQn
@ DMA5_DMA21_IRQn
Definition: MIMXRT1021.h:93
CCM_1_IRQn
@ CCM_1_IRQn
Definition: MIMXRT1021.h:183
Reserved58_IRQn
@ Reserved58_IRQn
Definition: MIMXRT1021.h:130
GPIO1_INT3_IRQn
@ GPIO1_INT3_IRQn
Definition: MIMXRT1021.h:163
LPI2C3_IRQn
@ LPI2C3_IRQn
Definition: MIMXRT1021.h:118
GPIO2_Combined_0_15_IRQn
@ GPIO2_Combined_0_15_IRQn
Definition: MIMXRT1021.h:170
USB_OTG1_IRQn
@ USB_OTG1_IRQn
Definition: MIMXRT1021.h:201
DMA3_DMA19_IRQn
@ DMA3_DMA19_IRQn
Definition: MIMXRT1021.h:91
USDHC2_IRQn
@ USDHC2_IRQn
Definition: MIMXRT1021.h:199
UsageFault_IRQn
@ UsageFault_IRQn
Definition: MIMXRT1021.h:81
XBAR1_IRQ_2_3_IRQn
@ XBAR1_IRQ_2_3_IRQn
Definition: MIMXRT1021.h:205
LPUART5_IRQn
@ LPUART5_IRQn
Definition: MIMXRT1021.h:112
GPC_IRQn
@ GPC_IRQn
Definition: MIMXRT1021.h:185
Reserved115_IRQn
@ Reserved115_IRQn
Definition: MIMXRT1021.h:187
DCP_IRQn
@ DCP_IRQn
Definition: MIMXRT1021.h:138
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1021.h:85
Reserved144_IRQn
@ Reserved144_IRQn
Definition: MIMXRT1021.h:216
DMA4_DMA20_IRQn
@ DMA4_DMA20_IRQn
Definition: MIMXRT1021.h:92
LPSPI3_IRQn
@ LPSPI3_IRQn
Definition: MIMXRT1021.h:122
TEMP_LOW_HIGH_IRQn
@ TEMP_LOW_HIGH_IRQn
Definition: MIMXRT1021.h:151
Reserved143_IRQn
@ Reserved143_IRQn
Definition: MIMXRT1021.h:215
CAN1_IRQn
@ CAN1_IRQn
Definition: MIMXRT1021.h:124
LPUART4_IRQn
@ LPUART4_IRQn
Definition: MIMXRT1021.h:111
CTI1_ERROR_IRQn
@ CTI1_ERROR_IRQn
Definition: MIMXRT1021.h:106
GPIO1_INT6_IRQn
@ GPIO1_INT6_IRQn
Definition: MIMXRT1021.h:166
TMR1_IRQn
@ TMR1_IRQn
Definition: MIMXRT1021.h:221
BusFault_IRQn
@ BusFault_IRQn
Definition: MIMXRT1021.h:80
ADC_ETC_IRQ2_IRQn
@ ADC_ETC_IRQ2_IRQn
Definition: MIMXRT1021.h:208
Reserved87_IRQn
@ Reserved87_IRQn
Definition: MIMXRT1021.h:159
CSU_IRQn
@ CSU_IRQn
Definition: MIMXRT1021.h:137
LPUART8_IRQn
@ LPUART8_IRQn
Definition: MIMXRT1021.h:115
ACMP2_IRQn
@ ACMP2_IRQn
Definition: MIMXRT1021.h:212
DMA7_DMA23_IRQn
@ DMA7_DMA23_IRQn
Definition: MIMXRT1021.h:95
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: MIMXRT1021.h:83
ADC2_IRQn
@ ADC2_IRQn
Definition: MIMXRT1021.h:156
TMR2_IRQn
@ TMR2_IRQn
Definition: MIMXRT1021.h:222
SRC_IRQn
@ SRC_IRQn
Definition: MIMXRT1021.h:186
LPI2C2_IRQn
@ LPI2C2_IRQn
Definition: MIMXRT1021.h:117
ADC_ETC_IRQ0_IRQn
@ ADC_ETC_IRQ0_IRQn
Definition: MIMXRT1021.h:206
Reserved59_IRQn
@ Reserved59_IRQn
Definition: MIMXRT1021.h:131
Reserved82_IRQn
@ Reserved82_IRQn
Definition: MIMXRT1021.h:154
EWM_IRQn
@ EWM_IRQn
Definition: MIMXRT1021.h:182
GPR_IRQ_IRQn
@ GPR_IRQ_IRQn
Definition: MIMXRT1021.h:129
DMA8_DMA24_IRQn
@ DMA8_DMA24_IRQn
Definition: MIMXRT1021.h:96
Reserved56_IRQn
@ Reserved56_IRQn
Definition: MIMXRT1021.h:128
Reserved86_IRQn
@ Reserved86_IRQn
Definition: MIMXRT1021.h:158
DMA6_DMA22_IRQn
@ DMA6_DMA22_IRQn
Definition: MIMXRT1021.h:94
ADC_ETC_IRQ1_IRQn
@ ADC_ETC_IRQ1_IRQn
Definition: MIMXRT1021.h:207
WDOG2_IRQn
@ WDOG2_IRQn
Definition: MIMXRT1021.h:133
PWM2_0_IRQn
@ PWM2_0_IRQn
Definition: MIMXRT1021.h:225
XBAR1_IRQ_0_1_IRQn
@ XBAR1_IRQ_0_1_IRQn
Definition: MIMXRT1021.h:204
HardFault_IRQn
@ HardFault_IRQn
Definition: MIMXRT1021.h:78
PMU_IRQn
@ PMU_IRQn
Definition: MIMXRT1021.h:149
ENC2_IRQn
@ ENC2_IRQn
Definition: MIMXRT1021.h:218
DCDC_IRQn
@ DCDC_IRQn
Definition: MIMXRT1021.h:157
TRNG_IRQn
@ TRNG_IRQn
Definition: MIMXRT1021.h:141
ACMP4_IRQn
@ ACMP4_IRQn
Definition: MIMXRT1021.h:214
WDOG1_IRQn
@ WDOG1_IRQn
Definition: MIMXRT1021.h:180
PWM1_2_IRQn
@ PWM1_2_IRQn
Definition: MIMXRT1021.h:192
ENET_1588_Timer_IRQn
@ ENET_1588_Timer_IRQn
Definition: MIMXRT1021.h:203
FLEXRAM_IRQn
@ FLEXRAM_IRQn
Definition: MIMXRT1021.h:126
LPSPI1_IRQn
@ LPSPI1_IRQn
Definition: MIMXRT1021.h:120
SAI2_IRQn
@ SAI2_IRQn
Definition: MIMXRT1021.h:145
PIT_IRQn
@ PIT_IRQn
Definition: MIMXRT1021.h:210
DMA11_DMA27_IRQn
@ DMA11_DMA27_IRQn
Definition: MIMXRT1021.h:99
GPIO5_Combined_16_31_IRQn
@ GPIO5_Combined_16_31_IRQn
Definition: MIMXRT1021.h:177
SAI3_TX_IRQn
@ SAI3_TX_IRQn
Definition: MIMXRT1021.h:147
LPUART3_IRQn
@ LPUART3_IRQn
Definition: MIMXRT1021.h:110
GPT2_IRQn
@ GPT2_IRQn
Definition: MIMXRT1021.h:189
CAN2_IRQn
@ CAN2_IRQn
Definition: MIMXRT1021.h:125
FLEXIO1_IRQn
@ FLEXIO1_IRQn
Definition: MIMXRT1021.h:178
Reserved147_IRQn
@ Reserved147_IRQn
Definition: MIMXRT1021.h:219
ENC1_IRQn
@ ENC1_IRQn
Definition: MIMXRT1021.h:217
DMA2_DMA18_IRQn
@ DMA2_DMA18_IRQn
Definition: MIMXRT1021.h:90
GPIO2_Combined_16_31_IRQn
@ GPIO2_Combined_16_31_IRQn
Definition: MIMXRT1021.h:171
GPIO1_INT7_IRQn
@ GPIO1_INT7_IRQn
Definition: MIMXRT1021.h:167
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: MIMXRT1021.h:77
GPIO3_Combined_16_31_IRQn
@ GPIO3_Combined_16_31_IRQn
Definition: MIMXRT1021.h:173
LPSPI2_IRQn
@ LPSPI2_IRQn
Definition: MIMXRT1021.h:121
Reserved123_IRQn
@ Reserved123_IRQn
Definition: MIMXRT1021.h:195
PWM1_3_IRQn
@ PWM1_3_IRQn
Definition: MIMXRT1021.h:193
LPUART6_IRQn
@ LPUART6_IRQn
Definition: MIMXRT1021.h:113
GPIO1_INT5_IRQn
@ GPIO1_INT5_IRQn
Definition: MIMXRT1021.h:165
SNVS_HP_WRAPPER_IRQn
@ SNVS_HP_WRAPPER_IRQn
Definition: MIMXRT1021.h:134
DMA9_DMA25_IRQn
@ DMA9_DMA25_IRQn
Definition: MIMXRT1021.h:97
SPDIF_IRQn
@ SPDIF_IRQn
Definition: MIMXRT1021.h:148
ENET_IRQn
@ ENET_IRQn
Definition: MIMXRT1021.h:202
DMA12_DMA28_IRQn
@ DMA12_DMA28_IRQn
Definition: MIMXRT1021.h:100
LPSPI4_IRQn
@ LPSPI4_IRQn
Definition: MIMXRT1021.h:123
LPUART1_IRQn
@ LPUART1_IRQn
Definition: MIMXRT1021.h:108
GPIO1_Combined_0_15_IRQn
@ GPIO1_Combined_0_15_IRQn
Definition: MIMXRT1021.h:168
PWM2_FAULT_IRQn
@ PWM2_FAULT_IRQn
Definition: MIMXRT1021.h:229
DCP_VMI_IRQn
@ DCP_VMI_IRQn
Definition: MIMXRT1021.h:139
DMA1_DMA17_IRQn
@ DMA1_DMA17_IRQn
Definition: MIMXRT1021.h:89
GPIO1_Combined_16_31_IRQn
@ GPIO1_Combined_16_31_IRQn
Definition: MIMXRT1021.h:169
dma_request_source_t
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
_dma_request_source
_dma_request_source
Structure for the DMA hardware request.
Definition: MIMXRT1021.h:289
kDmaRequestMuxSai3Rx
@ kDmaRequestMuxSai3Rx
Definition: MIMXRT1021.h:350
kDmaRequestMuxFlexPWM1ValueSub0
@ kDmaRequestMuxFlexPWM1ValueSub0
Definition: MIMXRT1021.h:322
kDmaRequestMuxLPUART3Rx
@ kDmaRequestMuxLPUART3Rx
Definition: MIMXRT1021.h:295
kDmaRequestMuxLPUART7Rx
@ kDmaRequestMuxLPUART7Rx
Definition: MIMXRT1021.h:299
kDmaRequestMuxFlexPWM1CaptureSub0
@ kDmaRequestMuxFlexPWM1CaptureSub0
Definition: MIMXRT1021.h:318
kDmaRequestMuxLPSPI3Rx
@ kDmaRequestMuxLPSPI3Rx
Definition: MIMXRT1021.h:302
kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1021.h:331
kDmaRequestMuxLPI2C1
@ kDmaRequestMuxLPI2C1
Definition: MIMXRT1021.h:304
kDmaRequestMuxLPUART5Tx
@ kDmaRequestMuxLPUART5Tx
Definition: MIMXRT1021.h:296
kDmaRequestMuxLPUART8Rx
@ kDmaRequestMuxLPUART8Rx
Definition: MIMXRT1021.h:343
kDmaRequestMuxACMP2
@ kDmaRequestMuxACMP2
Definition: MIMXRT1021.h:355
kDmaRequestMuxFlexPWM2CaptureSub1
@ kDmaRequestMuxFlexPWM2CaptureSub1
Definition: MIMXRT1021.h:362
kDmaRequestMuxFlexPWM1ValueSub3
@ kDmaRequestMuxFlexPWM1ValueSub3
Definition: MIMXRT1021.h:325
kDmaRequestMuxFlexPWM1ValueSub1
@ kDmaRequestMuxFlexPWM1ValueSub1
Definition: MIMXRT1021.h:323
kDmaRequestMuxLPSPI4Rx
@ kDmaRequestMuxLPSPI4Rx
Definition: MIMXRT1021.h:346
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1021.h:376
kDmaRequestMuxXBAR1Request1
@ kDmaRequestMuxXBAR1Request1
Definition: MIMXRT1021.h:317
kDmaRequestMuxQTIMER1CaptTimer0
@ kDmaRequestMuxQTIMER1CaptTimer0
Definition: MIMXRT1021.h:326
kDmaRequestMuxFlexIO1Request2Request3
@ kDmaRequestMuxFlexIO1Request2Request3
Definition: MIMXRT1021.h:334
kDmaRequestMuxSai1Rx
@ kDmaRequestMuxSai1Rx
Definition: MIMXRT1021.h:306
kDmaRequestMuxLPUART2Tx
@ kDmaRequestMuxLPUART2Tx
Definition: MIMXRT1021.h:336
kDmaRequestMuxADC1
@ kDmaRequestMuxADC1
Definition: MIMXRT1021.h:311
kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1021.h:374
kDmaRequestMuxQTIMER1CaptTimer2
@ kDmaRequestMuxQTIMER1CaptTimer2
Definition: MIMXRT1021.h:328
kDmaRequestMuxQTIMER2CaptTimer1
@ kDmaRequestMuxQTIMER2CaptTimer1
Definition: MIMXRT1021.h:370
kDmaRequestMuxSai2Tx
@ kDmaRequestMuxSai2Tx
Definition: MIMXRT1021.h:309
kDmaRequestMuxQTIMER1CaptTimer3
@ kDmaRequestMuxQTIMER1CaptTimer3
Definition: MIMXRT1021.h:329
kDmaRequestMuxSpdifRx
@ kDmaRequestMuxSpdifRx
Definition: MIMXRT1021.h:352
kDmaRequestMuxACMP1
@ kDmaRequestMuxACMP1
Definition: MIMXRT1021.h:312
kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1021.h:330
kDmaRequestMuxLPUART3Tx
@ kDmaRequestMuxLPUART3Tx
Definition: MIMXRT1021.h:294
kDmaRequestMuxFlexPWM2CaptureSub3
@ kDmaRequestMuxFlexPWM2CaptureSub3
Definition: MIMXRT1021.h:364
kDmaRequestMuxQTIMER2CaptTimer3
@ kDmaRequestMuxQTIMER2CaptTimer3
Definition: MIMXRT1021.h:372
kDmaRequestMuxLPSPI1Rx
@ kDmaRequestMuxLPSPI1Rx
Definition: MIMXRT1021.h:300
kDmaRequestMuxLPUART1Rx
@ kDmaRequestMuxLPUART1Rx
Definition: MIMXRT1021.h:293
kDmaRequestMuxFlexIO1Request0Request1
@ kDmaRequestMuxFlexIO1Request0Request1
Definition: MIMXRT1021.h:290
kDmaRequestMuxQTIMER1CaptTimer1
@ kDmaRequestMuxQTIMER1CaptTimer1
Definition: MIMXRT1021.h:327
kDmaRequestMuxXBAR1Request0
@ kDmaRequestMuxXBAR1Request0
Definition: MIMXRT1021.h:316
kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1021.h:375
kDmaRequestMuxXBAR1Request3
@ kDmaRequestMuxXBAR1Request3
Definition: MIMXRT1021.h:360
kDmaRequestMuxEnetTimer0
@ kDmaRequestMuxEnetTimer0
Definition: MIMXRT1021.h:357
kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1021.h:333
kDmaRequestMuxLPUART2Rx
@ kDmaRequestMuxLPUART2Rx
Definition: MIMXRT1021.h:337
kDmaRequestMuxLPSPI2Rx
@ kDmaRequestMuxLPSPI2Rx
Definition: MIMXRT1021.h:344
kDmaRequestMuxLPI2C3
@ kDmaRequestMuxLPI2C3
Definition: MIMXRT1021.h:305
kDmaRequestMuxFlexPWM2ValueSub0
@ kDmaRequestMuxFlexPWM2ValueSub0
Definition: MIMXRT1021.h:365
kDmaRequestMuxLPUART5Rx
@ kDmaRequestMuxLPUART5Rx
Definition: MIMXRT1021.h:297
kDmaRequestMuxLPUART1Tx
@ kDmaRequestMuxLPUART1Tx
Definition: MIMXRT1021.h:292
kDmaRequestMuxLPUART4Rx
@ kDmaRequestMuxLPUART4Rx
Definition: MIMXRT1021.h:339
kDmaRequestMuxSai1Tx
@ kDmaRequestMuxSai1Tx
Definition: MIMXRT1021.h:307
kDmaRequestMuxADC2
@ kDmaRequestMuxADC2
Definition: MIMXRT1021.h:354
kDmaRequestMuxQTIMER2CaptTimer0
@ kDmaRequestMuxQTIMER2CaptTimer0
Definition: MIMXRT1021.h:369
kDmaRequestMuxEnetTimer1
@ kDmaRequestMuxEnetTimer1
Definition: MIMXRT1021.h:358
kDmaRequestMuxSpdifTx
@ kDmaRequestMuxSpdifTx
Definition: MIMXRT1021.h:353
kDmaRequestMuxFlexPWM1CaptureSub2
@ kDmaRequestMuxFlexPWM1CaptureSub2
Definition: MIMXRT1021.h:320
kDmaRequestMuxLPUART4Tx
@ kDmaRequestMuxLPUART4Tx
Definition: MIMXRT1021.h:338
kDmaRequestMuxFlexPWM2ValueSub1
@ kDmaRequestMuxFlexPWM2ValueSub1
Definition: MIMXRT1021.h:366
kDmaRequestMuxFlexPWM2CaptureSub2
@ kDmaRequestMuxFlexPWM2CaptureSub2
Definition: MIMXRT1021.h:363
kDmaRequestMuxQTIMER2CaptTimer2
@ kDmaRequestMuxQTIMER2CaptTimer2
Definition: MIMXRT1021.h:371
kDmaRequestMuxXBAR1Request2
@ kDmaRequestMuxXBAR1Request2
Definition: MIMXRT1021.h:359
kDmaRequestMuxLPSPI2Tx
@ kDmaRequestMuxLPSPI2Tx
Definition: MIMXRT1021.h:345
kDmaRequestMuxFlexIO1Request6Request7
@ kDmaRequestMuxFlexIO1Request6Request7
Definition: MIMXRT1021.h:335
kDmaRequestMuxFlexPWM1ValueSub2
@ kDmaRequestMuxFlexPWM1ValueSub2
Definition: MIMXRT1021.h:324
kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1021.h:373
kDmaRequestMuxLPUART8Tx
@ kDmaRequestMuxLPUART8Tx
Definition: MIMXRT1021.h:342
kDmaRequestMuxLPUART7Tx
@ kDmaRequestMuxLPUART7Tx
Definition: MIMXRT1021.h:298
kDmaRequestMuxACMP4
@ kDmaRequestMuxACMP4
Definition: MIMXRT1021.h:356
kDmaRequestMuxLPSPI1Tx
@ kDmaRequestMuxLPSPI1Tx
Definition: MIMXRT1021.h:301
kDmaRequestMuxADC_ETC
@ kDmaRequestMuxADC_ETC
Definition: MIMXRT1021.h:310
kDmaRequestMuxFlexSPIRx
@ kDmaRequestMuxFlexSPIRx
Definition: MIMXRT1021.h:314
kDmaRequestMuxFlexPWM1CaptureSub1
@ kDmaRequestMuxFlexPWM1CaptureSub1
Definition: MIMXRT1021.h:319
kDmaRequestMuxLPI2C2
@ kDmaRequestMuxLPI2C2
Definition: MIMXRT1021.h:348
kDmaRequestMuxSai3Tx
@ kDmaRequestMuxSai3Tx
Definition: MIMXRT1021.h:351
kDmaRequestMuxFlexPWM1CaptureSub3
@ kDmaRequestMuxFlexPWM1CaptureSub3
Definition: MIMXRT1021.h:321
kDmaRequestMuxFlexPWM2ValueSub3
@ kDmaRequestMuxFlexPWM2ValueSub3
Definition: MIMXRT1021.h:368
kDmaRequestMuxFlexIO1Request4Request5
@ kDmaRequestMuxFlexIO1Request4Request5
Definition: MIMXRT1021.h:291
kDmaRequestMuxLPUART6Tx
@ kDmaRequestMuxLPUART6Tx
Definition: MIMXRT1021.h:340
kDmaRequestMuxFlexPWM2ValueSub2
@ kDmaRequestMuxFlexPWM2ValueSub2
Definition: MIMXRT1021.h:367
kDmaRequestMuxLPSPI4Tx
@ kDmaRequestMuxLPSPI4Tx
Definition: MIMXRT1021.h:347
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1021.h:332
kDmaRequestMuxFlexPWM2CaptureSub0
@ kDmaRequestMuxFlexPWM2CaptureSub0
Definition: MIMXRT1021.h:361
kDmaRequestMuxSai2Rx
@ kDmaRequestMuxSai2Rx
Definition: MIMXRT1021.h:308
kDmaRequestMuxFlexSPITx
@ kDmaRequestMuxFlexSPITx
Definition: MIMXRT1021.h:315
kDmaRequestMuxLPUART6Rx
@ kDmaRequestMuxLPUART6Rx
Definition: MIMXRT1021.h:341
kDmaRequestMuxLPSPI3Tx
@ kDmaRequestMuxLPSPI3Tx
Definition: MIMXRT1021.h:303
kDmaRequestMuxACMP3
@ kDmaRequestMuxACMP3
Definition: MIMXRT1021.h:313
kDmaRequestMuxLPI2C4
@ kDmaRequestMuxLPI2C4
Definition: MIMXRT1021.h:349
SEMC_Type::DBICR0
__IO uint32_t DBICR0
Definition: MIMXRT1021.h:29743
CCM_Type::CCSR
__IO uint32_t CCSR
Definition: MIMXRT1021.h:3947
TEMPMON_Type::TEMPSENSE0_SET
__IO uint32_t TEMPSENSE0_SET
Definition: MIMXRT1021.h:32737
TRNG_Type::SEC_CFG
__IO uint32_t SEC_CFG
Definition: MIMXRT1021.h:33527
XTALOSC24M_Type::LOWPWR_CTRL_TOG
__IO uint32_t LOWPWR_CTRL_TOG
Definition: MIMXRT1021.h:40279
IOMUXC_SNVS_GPR_Type::GPR1
uint32_t GPR1
Definition: MIMXRT1021.h:21967
ENET_Type::IEEE_R_OCTETS_OK
__I uint32_t IEEE_R_OCTETS_OK
Definition: MIMXRT1021.h:14429
ENET_Type::IEEE_T_DEF
__I uint32_t IEEE_T_DEF
Definition: MIMXRT1021.h:14397
USBPHY_Type::RX_SET
__IO uint32_t RX_SET
Definition: MIMXRT1021.h:35835
USDHC_Type::SYS_CTRL
__IO uint32_t SYS_CTRL
Definition: MIMXRT1021.h:37404
TRNG_Type::PKRCNT76
__I uint32_t PKRCNT76
Definition: MIMXRT1021.h:33522
PWM_Type::CVAL5
__I uint16_t CVAL5
Definition: MIMXRT1021.h:27920
XBARA_Type::CTRL1
__IO uint16_t CTRL1
Definition: MIMXRT1021.h:39307
ADC_ETC_Type::TRIGn_CHAIN_7_6
__IO uint32_t TRIGn_CHAIN_7_6
Definition: MIMXRT1021.h:1433
ENET_Type::TCCR
__IO uint32_t TCCR
Definition: MIMXRT1021.h:14442
ENET_Type::ECR
__IO uint32_t ECR
Definition: MIMXRT1021.h:14333
DCP_Type::CH0OPTS_TOG
__IO uint32_t CH0OPTS_TOG
Definition: MIMXRT1021.h:9011
SNVS_Type::HPSICR
__IO uint32_t HPSICR
Definition: MIMXRT1021.h:30912
DMA_Type::DCHPRI10
__IO uint8_t DCHPRI10
Definition: MIMXRT1021.h:10674
USBPHY_Type::DEBUG1_CLR
__IO uint32_t DEBUG1_CLR
Definition: MIMXRT1021.h:35852
DCP_Type::KEYDATA
__IO uint32_t KEYDATA
Definition: MIMXRT1021.h:8984
OCOTP_Type::MEM3
__IO uint32_t MEM3
Definition: MIMXRT1021.h:24854
CCM_ANALOG_Type::PLL_USB1_CLR
__IO uint32_t PLL_USB1_CLR
Definition: MIMXRT1021.h:5770
XBARA_Type::SEL34
__IO uint16_t SEL34
Definition: MIMXRT1021.h:39274
TRNG_Type::VID1
__I uint32_t VID1
Definition: MIMXRT1021.h:33532
TRNG_Type::SCMC
__I uint32_t SCMC
Definition: MIMXRT1021.h:33490
BEE_Type::CTR_NONCE1_W3
__O uint32_t CTR_NONCE1_W3
Definition: MIMXRT1021.h:2815
TRNG_Type::SCR5L
__IO uint32_t SCR5L
Definition: MIMXRT1021.h:33511
DCP_Type::CH0OPTS
__IO uint32_t CH0OPTS
Definition: MIMXRT1021.h:9008
XBARA_Type::SEL60
__IO uint16_t SEL60
Definition: MIMXRT1021.h:39300
USB_Type::ENDPTCOMPLETE
__IO uint32_t ENDPTCOMPLETE
Definition: MIMXRT1021.h:34195
AOI_Type::BFCRT01
__IO uint16_t BFCRT01
Definition: MIMXRT1021.h:2596
PWM_Type::OUTEN
__IO uint16_t OUTEN
Definition: MIMXRT1021.h:27925
CCM_ANALOG_Type::PLL_AUDIO_TOG
__IO uint32_t PLL_AUDIO_TOG
Definition: MIMXRT1021.h:5786
ENET_Type::IEEE_R_CRC
__I uint32_t IEEE_R_CRC
Definition: MIMXRT1021.h:14425
PMU_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1021.h:25996
OCOTP_Type::ANA0
__IO uint32_t ANA0
Definition: MIMXRT1021.h:24858
EWM_Type::CLKCTRL
__IO uint8_t CLKCTRL
Definition: MIMXRT1021.h:15972
PGC_Type::CPU_PUPSCR
__IO uint32_t CPU_PUPSCR
Definition: MIMXRT1021.h:25690
BEE_Type::ADDR_OFFSET0
__IO uint32_t ADDR_OFFSET0
Definition: MIMXRT1021.h:2801
USDHC_Type::DLL_STATUS
__I uint32_t DLL_STATUS
Definition: MIMXRT1021.h:37418
SPDIF_Type::SIC
__O uint32_t SIC
Definition: MIMXRT1021.h:32014
IOMUXC_GPR_Type::GPR0
uint32_t GPR0
Definition: MIMXRT1021.h:19585
USBPHY_Type::DEBUG_TOG
__IO uint32_t DEBUG_TOG
Definition: MIMXRT1021.h:35847
CSU_Type::HPCONTROL0
__IO uint32_t HPCONTROL0
Definition: MIMXRT1021.h:8030
USB_ANALOG_Type::VBUS_DETECT
__IO uint32_t VBUS_DETECT
Definition: MIMXRT1021.h:36939
CCM_Type::CACRR
__IO uint32_t CACRR
Definition: MIMXRT1021.h:3948
DCP_Type::CH2STAT_SET
__IO uint32_t CH2STAT_SET
Definition: MIMXRT1021.h:9029
CAN_Type::RXMGMASK
__IO uint32_t RXMGMASK
Definition: MIMXRT1021.h:3106
LPI2C_Type::SDER
__IO uint32_t SDER
Definition: MIMXRT1021.h:22234
LPSPI_Type::CR
__IO uint32_t CR
Definition: MIMXRT1021.h:23260
PWM_Type::DTCNT0
__IO uint16_t DTCNT0
Definition: MIMXRT1021.h:27902
PMU_Type::REG_2P5_TOG
__IO uint32_t REG_2P5_TOG
Definition: MIMXRT1021.h:25990
ENET_Type::RAFL
__IO uint32_t RAFL
Definition: MIMXRT1021.h:14365
USB_Type::ENDPTSETUPSTAT
__IO uint32_t ENDPTSETUPSTAT
Definition: MIMXRT1021.h:34191
GPT_Type::CR
__IO uint32_t CR
Definition: MIMXRT1021.h:18306
ENET_Type::RMON_R_JAB
__I uint32_t RMON_R_JAB
Definition: MIMXRT1021.h:14413
USBPHY_Type::TX
__IO uint32_t TX
Definition: MIMXRT1021.h:35830
CAN_Type::RX15MASK
__IO uint32_t RX15MASK
Definition: MIMXRT1021.h:3108
BEE_Type::AES_KEY0_W1
__O uint32_t AES_KEY0_W1
Definition: MIMXRT1021.h:2804
SEMC_Type::IPCMD
__IO uint32_t IPCMD
Definition: MIMXRT1021.h:29749
TEMPMON_Type::TEMPSENSE1_CLR
__IO uint32_t TEMPSENSE1_CLR
Definition: MIMXRT1021.h:32742
USDHC_Type::DATA_BUFF_ACC_PORT
__IO uint32_t DATA_BUFF_ACC_PORT
Definition: MIMXRT1021.h:37401
ENC_Type::LMOD
__IO uint16_t LMOD
Definition: MIMXRT1021.h:13835
SEMC_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1021.h:29719
ENET_Type::TAEM
__IO uint32_t TAEM
Definition: MIMXRT1021.h:14367
TEMPMON_Type::TEMPSENSE0
__IO uint32_t TEMPSENSE0
Definition: MIMXRT1021.h:32736
LPUART_Type::WATER
__IO uint32_t WATER
Definition: MIMXRT1021.h:23893
PWM_Type::MCTRL2
__IO uint16_t MCTRL2
Definition: MIMXRT1021.h:27930
PWM_Type::STS
__IO uint16_t STS
Definition: MIMXRT1021.h:27897
ADC_Type::OFS
__IO uint32_t OFS
Definition: MIMXRT1021.h:1086
ADC_Type::CAL
__IO uint32_t CAL
Definition: MIMXRT1021.h:1087
USBPHY_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1021.h:35841
LPI2C_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1021.h:22207
FLEXSPI_Type::AHBSPNDSTS
__I uint32_t AHBSPNDSTS
Definition: MIMXRT1021.h:16835
PGC_Type::MEGA_PUPSCR
__IO uint32_t MEGA_PUPSCR
Definition: MIMXRT1021.h:25685
FLEXIO_Type::PIN
__I uint32_t PIN
Definition: MIMXRT1021.h:16091
TRNG_Type::PKRRNG
__IO uint32_t PKRRNG
Definition: MIMXRT1021.h:33474
SNVS_Type::HPTAMR
__IO uint32_t HPTAMR
Definition: MIMXRT1021.h:30920
XBARA_Type::SEL26
__IO uint16_t SEL26
Definition: MIMXRT1021.h:39266
DMA_Type::CITER_ELINKYES
__IO uint16_t CITER_ELINKYES
Definition: MIMXRT1021.h:10712
IOMUXC_GPR_Type::GPR21
__IO uint32_t GPR21
Definition: MIMXRT1021.h:19606
CMP_Type::DACCR
__IO uint8_t DACCR
Definition: MIMXRT1021.h:7778
ADC_ETC_Type::DMA_CTRL
__IO uint32_t DMA_CTRL
Definition: MIMXRT1021.h:1426
DCP_Type::CAPABILITY1
__I uint32_t CAPABILITY1
Definition: MIMXRT1021.h:8978
TRNG_Type::SBLIM
__IO uint32_t SBLIM
Definition: MIMXRT1021.h:33481
PWM_Type::CVAL2
__I uint16_t CVAL2
Definition: MIMXRT1021.h:27914
FLEXSPI_Type::IPCR1
__IO uint32_t IPCR1
Definition: MIMXRT1021.h:16824
USB_Type::DEVICEADDR
__IO uint32_t DEVICEADDR
Definition: MIMXRT1021.h:34173
XTALOSC24M_Type::OSC_CONFIG1
__IO uint32_t OSC_CONFIG1
Definition: MIMXRT1021.h:40285
ENC_Type::REV
__IO uint16_t REV
Definition: MIMXRT1021.h:13823
SEMC_Type::STS13
uint32_t STS13
Definition: MIMXRT1021.h:29767
CAN_Type::DBG1
__I uint32_t DBG1
Definition: MIMXRT1021.h:3122
LPSPI_Type::FCR
__IO uint32_t FCR
Definition: MIMXRT1021.h:23272
OCOTP_Type::GP3
__IO uint32_t GP3
Definition: MIMXRT1021.h:24888
ENET_Type::RMON_T_P256TO511
__I uint32_t RMON_T_P256TO511
Definition: MIMXRT1021.h:14388
LPI2C_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1021.h:22210
SEMC_Type::STS12
__I uint32_t STS12
Definition: MIMXRT1021.h:29766
PGC_Type::MEGA_SR
__IO uint32_t MEGA_SR
Definition: MIMXRT1021.h:25687
DMA_Type::DCHPRI18
__IO uint8_t DCHPRI18
Definition: MIMXRT1021.h:10682
GPT_Type::SR
__IO uint32_t SR
Definition: MIMXRT1021.h:18308
OCOTP_Type::SRK3
__IO uint32_t SRK3
Definition: MIMXRT1021.h:24870
FLEXSPI_Type::AHBCR
__IO uint32_t AHBCR
Definition: MIMXRT1021.h:16810
LPI2C_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1021.h:22208
OCOTP_Type::SCS_SET
__IO uint32_t SCS_SET
Definition: MIMXRT1021.h:24824
DCP_Type::CAPABILITY0
__IO uint32_t CAPABILITY0
Definition: MIMXRT1021.h:8976
LPI2C_Type::MFSR
__I uint32_t MFSR
Definition: MIMXRT1021.h:22226
IOMUXC_SNVS_GPR_Type::GPR3
__IO uint32_t GPR3
Definition: MIMXRT1021.h:21969
SEMC_Type::NANDCR0
__IO uint32_t NANDCR0
Definition: MIMXRT1021.h:29731
TRNG_Type::SCR2L
__IO uint32_t SCR2L
Definition: MIMXRT1021.h:33499
IOMUXC_GPR_Type::GPR17
__IO uint32_t GPR17
Definition: MIMXRT1021.h:19602
ENET_Type::RMON_R_P65TO127
__I uint32_t RMON_R_P65TO127
Definition: MIMXRT1021.h:14416
ENET_Type::IEEE_R_ALIGN
__I uint32_t IEEE_R_ALIGN
Definition: MIMXRT1021.h:14426
ENET_Type::RMON_T_FRAG
__I uint32_t RMON_T_FRAG
Definition: MIMXRT1021.h:14382
SEMC_Type::IPRXDAT
__I uint32_t IPRXDAT
Definition: MIMXRT1021.h:29752
SPDIF_Type::STCSCL
__IO uint32_t STCSCL
Definition: MIMXRT1021.h:32026
KPP_Type::KPDR
__IO uint16_t KPDR
Definition: MIMXRT1021.h:22069
ADC_Type::CV
__IO uint32_t CV
Definition: MIMXRT1021.h:1085
CAN_Type::DBG2
__I uint32_t DBG2
Definition: MIMXRT1021.h:3123
CAN_Type::RXFIR
__I uint32_t RXFIR
Definition: MIMXRT1021.h:3120
OCOTP_Type::CFG4
__IO uint32_t CFG4
Definition: MIMXRT1021.h:24842
USBPHY_Type::TX_CLR
__IO uint32_t TX_CLR
Definition: MIMXRT1021.h:35832
PWM_Type::VAL1
__IO uint16_t VAL1
Definition: MIMXRT1021.h:27886
ENC_Type::POSDH
__I uint16_t POSDH
Definition: MIMXRT1021.h:13822
PMU_Type::REG_1P1_SET
__IO uint32_t REG_1P1_SET
Definition: MIMXRT1021.h:25980
LPI2C_Type::MCFGR0
__IO uint32_t MCFGR0
Definition: MIMXRT1021.h:22214
XTALOSC24M_Type::OSC_CONFIG2_TOG
__IO uint32_t OSC_CONFIG2_TOG
Definition: MIMXRT1021.h:40292
SNVS_Type::HPLR
__IO uint32_t HPLR
Definition: MIMXRT1021.h:30909
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ
__IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ
Definition: MIMXRT1021.h:21459
IOMUXC_GPR_Type::GPR3
__IO uint32_t GPR3
Definition: MIMXRT1021.h:19588
ENET_Type::RCR
__IO uint32_t RCR
Definition: MIMXRT1021.h:14340
OCOTP_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1021.h:24810
PIT_Type::TCTRL
__IO uint32_t TCTRL
Definition: MIMXRT1021.h:25828
DCP_Type::CH2OPTS
__IO uint32_t CH2OPTS
Definition: MIMXRT1021.h:9032
BEE_Type::AES_KEY0_W3
__O uint32_t AES_KEY0_W3
Definition: MIMXRT1021.h:2806
SNVS_Type::HPVIDR1
__I uint32_t HPVIDR1
Definition: MIMXRT1021.h:30942
OCOTP_Type::CFG0
__IO uint32_t CFG0
Definition: MIMXRT1021.h:24834
DCP_Type::DBGDATA
__I uint32_t DBGDATA
Definition: MIMXRT1021.h:9051
TEMPMON_Type::TEMPSENSE2
__IO uint32_t TEMPSENSE2
Definition: MIMXRT1021.h:32745
XBARA_Type::SEL15
__IO uint16_t SEL15
Definition: MIMXRT1021.h:39255
DCDC_Type::REG2
__IO uint32_t REG2
Definition: MIMXRT1021.h:8641
OCOTP_Type::ANA1
__IO uint32_t ANA1
Definition: MIMXRT1021.h:24860
LPI2C_Type::MRDR
__I uint32_t MRDR
Definition: MIMXRT1021.h:22229
CCM_Type::CIMR
__IO uint32_t CIMR
Definition: MIMXRT1021.h:3965
DMA_Type::DCHPRI25
__IO uint8_t DCHPRI25
Definition: MIMXRT1021.h:10691
TRNG_Type::PKRCNT32
__I uint32_t PKRCNT32
Definition: MIMXRT1021.h:33520
LPUART_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1021.h:23888
OCOTP_Type::SJC_RESP1
__IO uint32_t SJC_RESP1
Definition: MIMXRT1021.h:24882
CCM_ANALOG_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1021.h:5807
CCM_ANALOG_Type::MISC2_TOG
__IO uint32_t MISC2_TOG
Definition: MIMXRT1021.h:5815
SNVS_Type::LPTAR
__IO uint32_t LPTAR
Definition: MIMXRT1021.h:30931
IOMUXC_GPR_Type::GPR4
__IO uint32_t GPR4
Definition: MIMXRT1021.h:19589
ADC_Type::GC
__IO uint32_t GC
Definition: MIMXRT1021.h:1083
LPSPI_Type::CCR
__IO uint32_t CCR
Definition: MIMXRT1021.h:23270
USBPHY_Type::TX_TOG
__IO uint32_t TX_TOG
Definition: MIMXRT1021.h:35833
DMA_Type::ERQ
__IO uint32_t ERQ
Definition: MIMXRT1021.h:10645
SEMC_Type::IPCR1
__IO uint32_t IPCR1
Definition: MIMXRT1021.h:29747
ENET_Type::RMON_T_JAB
__I uint32_t RMON_T_JAB
Definition: MIMXRT1021.h:14383
DCP_Type::CH2SEMA
__IO uint32_t CH2SEMA
Definition: MIMXRT1021.h:9026
FLEXSPI_Type::INTR
__IO uint32_t INTR
Definition: MIMXRT1021.h:16812
XBARA_Type::SEL0
__IO uint16_t SEL0
Definition: MIMXRT1021.h:39240
FLEXIO_Type::SHIFTSTAT
__IO uint32_t SHIFTSTAT
Definition: MIMXRT1021.h:16092
CCM_ANALOG_Type::PLL_AUDIO_SET
__IO uint32_t PLL_AUDIO_SET
Definition: MIMXRT1021.h:5784
TRNG_Type::INT_MASK
__IO uint32_t INT_MASK
Definition: MIMXRT1021.h:33529
SNVS_Type::LPLR
__IO uint32_t LPLR
Definition: MIMXRT1021.h:30922
IOMUXC_GPR_Type::GPR15
uint32_t GPR15
Definition: MIMXRT1021.h:19600
SEMC_Type::SRAMCR2
__IO uint32_t SRAMCR2
Definition: MIMXRT1021.h:29741
GPIO_Type::DR_SET
__O uint32_t DR_SET
Definition: MIMXRT1021.h:17867
SNVS_Type::LPSMCMR
__IO uint32_t LPSMCMR
Definition: MIMXRT1021.h:30932
IOMUXC_GPR_Type::GPR24
__IO uint32_t GPR24
Definition: MIMXRT1021.h:19609
ENET_Type::TGSR
__IO uint32_t TGSR
Definition: MIMXRT1021.h:14439
TMR_Type::HOLD
__IO uint16_t HOLD
Definition: MIMXRT1021.h:32989
BEE_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1021.h:2800
XBARA_Type::SEL7
__IO uint16_t SEL7
Definition: MIMXRT1021.h:39247
XBARA_Type::SEL35
__IO uint16_t SEL35
Definition: MIMXRT1021.h:39275
PWM_Type::CAPTCOMPX
__IO uint16_t CAPTCOMPX
Definition: MIMXRT1021.h:27909
LPI2C_Type::MCCR0
__IO uint32_t MCCR0
Definition: MIMXRT1021.h:22221
OCOTP_Type::SRK_REVOKE
__IO uint32_t SRK_REVOKE
Definition: MIMXRT1021.h:24908
TRNG_Type::SCR4C
__I uint32_t SCR4C
Definition: MIMXRT1021.h:33506
I2S_Type::RCR4
__IO uint32_t RCR4
Definition: MIMXRT1021.h:18614
USB_Type::HCIVERSION
__I uint16_t HCIVERSION
Definition: MIMXRT1021.h:34159
SNVS_Type::HPTALR
__IO uint32_t HPTALR
Definition: MIMXRT1021.h:30921
RTWDOG_Type::TOVAL
__IO uint32_t TOVAL
Definition: MIMXRT1021.h:29523
XBARA_Type::SEL37
__IO uint16_t SEL37
Definition: MIMXRT1021.h:39277
DCP_Type::PACKET6
__I uint32_t PACKET6
Definition: MIMXRT1021.h:8998
DCP_Type::CH2STAT_CLR
__IO uint32_t CH2STAT_CLR
Definition: MIMXRT1021.h:9030
ENET_Type::IEEE_R_FDXFC
__I uint32_t IEEE_R_FDXFC
Definition: MIMXRT1021.h:14428
OCOTP_Type::CFG3
__IO uint32_t CFG3
Definition: MIMXRT1021.h:24840
OCOTP_Type::SRK5
__IO uint32_t SRK5
Definition: MIMXRT1021.h:24874
LPUART_Type::PINCFG
__IO uint32_t PINCFG
Definition: MIMXRT1021.h:23885
PGC_Type::CPU_CTRL
__IO uint32_t CPU_CTRL
Definition: MIMXRT1021.h:25689
XBARA_Type::SEL29
__IO uint16_t SEL29
Definition: MIMXRT1021.h:39269
WDOG_Type::WMCR
__IO uint16_t WMCR
Definition: MIMXRT1021.h:39046
I2S_Type::TMR
__IO uint32_t TMR
Definition: MIMXRT1021.h:18608
PIT_Type::LTMR64L
__I uint32_t LTMR64L
Definition: MIMXRT1021.h:25823
ADC_ETC_Type::TRIGn_CHAIN_3_2
__IO uint32_t TRIGn_CHAIN_3_2
Definition: MIMXRT1021.h:1431
CCM_Type::CCOSR
__IO uint32_t CCOSR
Definition: MIMXRT1021.h:3966
PMU_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1021.h:25997
SNVS_Type::HPRTCLR
__IO uint32_t HPRTCLR
Definition: MIMXRT1021.h:30919
CCM_Type::CCGR2
__IO uint32_t CCGR2
Definition: MIMXRT1021.h:3970
USDHC_Type::CMD_XFR_TYP
__IO uint32_t CMD_XFR_TYP
Definition: MIMXRT1021.h:37396
ENET_Type::RACC
__IO uint32_t RACC
Definition: MIMXRT1021.h:14373
FLEXRAM_Type::INT_SIG_EN
__IO uint32_t INT_SIG_EN
Definition: MIMXRT1021.h:16663
ENET_Type::EIR
__IO uint32_t EIR
Definition: MIMXRT1021.h:14327
SNVS_Type::LPSR
__IO uint32_t LPSR
Definition: MIMXRT1021.h:30928
DMA_Type::CERR
__O uint8_t CERR
Definition: MIMXRT1021.h:10654
XTALOSC24M_Type::OSC_CONFIG0_TOG
__IO uint32_t OSC_CONFIG0_TOG
Definition: MIMXRT1021.h:40284
IOMUXC_GPR_Type::GPR20
__IO uint32_t GPR20
Definition: MIMXRT1021.h:19605
USB_Type::ID
__I uint32_t ID
Definition: MIMXRT1021.h:34144
USB_Type::GPTIMER1CTRL
__IO uint32_t GPTIMER1CTRL
Definition: MIMXRT1021.h:34154
PMU_Type::REG_CORE_CLR
__IO uint32_t REG_CORE_CLR
Definition: MIMXRT1021.h:25993
DMA_Type::DLAST_SGA
__IO int32_t DLAST_SGA
Definition: MIMXRT1021.h:10714
CCM_ANALOG_Type::PLL_AUDIO
__IO uint32_t PLL_AUDIO
Definition: MIMXRT1021.h:5783
CCM_ANALOG_Type::PFD_480_SET
__IO uint32_t PFD_480_SET
Definition: MIMXRT1021.h:5796
OCOTP_Type::READ_CTRL
__IO uint32_t READ_CTRL
Definition: MIMXRT1021.h:24817
IOMUXC_GPR_Type::GPR5
__IO uint32_t GPR5
Definition: MIMXRT1021.h:19590
TMR_Type::COMP1
__IO uint16_t COMP1
Definition: MIMXRT1021.h:32985
FLEXSPI_Type::IPTXFSTS
__I uint32_t IPTXFSTS
Definition: MIMXRT1021.h:16837
OCOTP_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1021.h:24811
XBARB_Type::SEL2
__IO uint16_t SEL2
Definition: MIMXRT1021.h:40141
GPIO_Type::EDGE_SEL
__IO uint32_t EDGE_SEL
Definition: MIMXRT1021.h:17865
RTWDOG_Type::CNT
__IO uint32_t CNT
Definition: MIMXRT1021.h:29522
LPSPI_Type::CFGR1
__IO uint32_t CFGR1
Definition: MIMXRT1021.h:23265
ENET_Type::TCSR
__IO uint32_t TCSR
Definition: MIMXRT1021.h:14441
ENET_Type::IEEE_T_EXCOL
__I uint32_t IEEE_T_EXCOL
Definition: MIMXRT1021.h:14399
USB_ANALOG_Type::CHRG_DETECT_TOG
__IO uint32_t CHRG_DETECT_TOG
Definition: MIMXRT1021.h:36946
EWM_Type::CTRL
__IO uint8_t CTRL
Definition: MIMXRT1021.h:15968
FLEXRAM_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition: MIMXRT1021.h:16661
WDOG_Type::WCR
__IO uint16_t WCR
Definition: MIMXRT1021.h:39042
OCOTP_Type::CFG1
__IO uint32_t CFG1
Definition: MIMXRT1021.h:24836
BEE_Type::CTR_NONCE0_W0
__O uint32_t CTR_NONCE0_W0
Definition: MIMXRT1021.h:2808
DMA_Type::ATTR
__IO uint16_t ATTR
Definition: MIMXRT1021.h:10701
ENET_Type::MMFR
__IO uint32_t MMFR
Definition: MIMXRT1021.h:14335
PWM_Type::FTST
__IO uint16_t FTST
Definition: MIMXRT1021.h:27934
BEE_Type::CTR_NONCE0_W1
__O uint32_t CTR_NONCE0_W1
Definition: MIMXRT1021.h:2809
DCP_Type::CH3STAT_CLR
__IO uint32_t CH3STAT_CLR
Definition: MIMXRT1021.h:9042
IOMUXC_GPR_Type::GPR22
__IO uint32_t GPR22
Definition: MIMXRT1021.h:19607
KPP_Type::KPSR
__IO uint16_t KPSR
Definition: MIMXRT1021.h:22067
ENET_Type::RMON_T_OVERSIZE
__I uint32_t RMON_T_OVERSIZE
Definition: MIMXRT1021.h:14381
CSU_Type::SA
__IO uint32_t SA
Definition: MIMXRT1021.h:8028
PGC_Type::CPU_PDNSCR
__IO uint32_t CPU_PDNSCR
Definition: MIMXRT1021.h:25691
FLEXSPI_Type::IPRXFSTS
__I uint32_t IPRXFSTS
Definition: MIMXRT1021.h:16836
DCP_Type::CONTEXT
__IO uint32_t CONTEXT
Definition: MIMXRT1021.h:8980
USDHC_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition: MIMXRT1021.h:37405
OCOTP_Type::GP1
__IO uint32_t GP1
Definition: MIMXRT1021.h:24890
XBARA_Type::SEL36
__IO uint16_t SEL36
Definition: MIMXRT1021.h:39276
OCOTP_Type::SW_GP22
__IO uint32_t SW_GP22
Definition: MIMXRT1021.h:24900
SNVS_Type::HPSVCR
__IO uint32_t HPSVCR
Definition: MIMXRT1021.h:30913
LPI2C_Type::MIER
__IO uint32_t MIER
Definition: MIMXRT1021.h:22212
DMA_Type::DCHPRI17
__IO uint8_t DCHPRI17
Definition: MIMXRT1021.h:10683
AIPSTZ_Type::OPACR
__IO uint32_t OPACR
Definition: MIMXRT1021.h:1885
TRNG_Type::PKRCNTDC
__I uint32_t PKRCNTDC
Definition: MIMXRT1021.h:33525
PMU_Type::REG_1P1_TOG
__IO uint32_t REG_1P1_TOG
Definition: MIMXRT1021.h:25982
USB_Type::CAPLENGTH
__I uint8_t CAPLENGTH
Definition: MIMXRT1021.h:34157
XBARA_Type::SEL63
__IO uint16_t SEL63
Definition: MIMXRT1021.h:39303
LPI2C_Type::MCFGR3
__IO uint32_t MCFGR3
Definition: MIMXRT1021.h:22217
DMA_Type::SOFF
__IO uint16_t SOFF
Definition: MIMXRT1021.h:10700
CCM_Type::CBCDR
__IO uint32_t CBCDR
Definition: MIMXRT1021.h:3949
I2S_Type::TCR3
__IO uint32_t TCR3
Definition: MIMXRT1021.h:18601
SNVS_Type::HPCOMR
__IO uint32_t HPCOMR
Definition: MIMXRT1021.h:30910
TMR_Type::ENBL
__IO uint16_t ENBL
Definition: MIMXRT1021.h:32999
XTALOSC24M_Type::OSC_CONFIG1_TOG
__IO uint32_t OSC_CONFIG1_TOG
Definition: MIMXRT1021.h:40288
ENET_Type::GAUR
__IO uint32_t GAUR
Definition: MIMXRT1021.h:14353
USB_Type::TXFILLTUNING
__IO uint32_t TXFILLTUNING
Definition: MIMXRT1021.h:34182
CCM_ANALOG_Type::PLL_AUDIO_CLR
__IO uint32_t PLL_AUDIO_CLR
Definition: MIMXRT1021.h:5785
USBPHY_Type::RX_TOG
__IO uint32_t RX_TOG
Definition: MIMXRT1021.h:35837
PWM_Type::CVAL3CYC
__I uint16_t CVAL3CYC
Definition: MIMXRT1021.h:27917
CCM_Type::CCGR6
__IO uint32_t CCGR6
Definition: MIMXRT1021.h:3974
CAN_Type::RX14MASK
__IO uint32_t RX14MASK
Definition: MIMXRT1021.h:3107
GPIO_Type::ICR1
__IO uint32_t ICR1
Definition: MIMXRT1021.h:17861
XBARA_Type::SEL62
__IO uint16_t SEL62
Definition: MIMXRT1021.h:39302
DCP_Type::PAGETABLE
__IO uint32_t PAGETABLE
Definition: MIMXRT1021.h:9053
CCM_Type::CISR
__IO uint32_t CISR
Definition: MIMXRT1021.h:3964
ENET_Type::ATVR
__IO uint32_t ATVR
Definition: MIMXRT1021.h:14432
I2S_Type::RCSR
__IO uint32_t RCSR
Definition: MIMXRT1021.h:18610
XBARA_Type::SEL57
__IO uint16_t SEL57
Definition: MIMXRT1021.h:39297
USBPHY_Type::DEBUG_CLR
__IO uint32_t DEBUG_CLR
Definition: MIMXRT1021.h:35846
CAN_Type::CRCR
__I uint32_t CRCR
Definition: MIMXRT1021.h:3118
XBARA_Type::SEL12
__IO uint16_t SEL12
Definition: MIMXRT1021.h:39252
USB_ANALOG_Type::LOOPBACK
__IO uint32_t LOOPBACK
Definition: MIMXRT1021.h:36951
AIPSTZ_Type::OPACR2
__IO uint32_t OPACR2
Definition: MIMXRT1021.h:1887
ENET_Type::PAUR
__IO uint32_t PAUR
Definition: MIMXRT1021.h:14345
I2S_Type::TCR1
__IO uint32_t TCR1
Definition: MIMXRT1021.h:18599
USB_Type::HWTXBUF
__I uint32_t HWTXBUF
Definition: MIMXRT1021.h:34148
TMR_Type::FILT
__IO uint16_t FILT
Definition: MIMXRT1021.h:32996
XBARA_Type::SEL65
__IO uint16_t SEL65
Definition: MIMXRT1021.h:39305
DMA_Type::DCHPRI19
__IO uint8_t DCHPRI19
Definition: MIMXRT1021.h:10681
I2S_Type::TCR2
__IO uint32_t TCR2
Definition: MIMXRT1021.h:18600
XBARA_Type::SEL5
__IO uint16_t SEL5
Definition: MIMXRT1021.h:39245
LPI2C_Type::MCFGR1
__IO uint32_t MCFGR1
Definition: MIMXRT1021.h:22215
XTALOSC24M_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1021.h:40272
USDHC_Type::BLK_ATT
__IO uint32_t BLK_ATT
Definition: MIMXRT1021.h:37394
TRNG_Type::MCTL
__IO uint32_t MCTL
Definition: MIMXRT1021.h:33472
CCM_ANALOG_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1021.h:5804
iomuxc_select_input_t
enum _iomuxc_select_input iomuxc_select_input_t
Enumeration for the IOMUXC select input.
DCP_Type::CH0CMDPTR
__IO uint32_t CH0CMDPTR
Definition: MIMXRT1021.h:9000
DCP_Type::PACKET1
__I uint32_t PACKET1
Definition: MIMXRT1021.h:8988
BEE_Type::CTR_NONCE1_W2
__O uint32_t CTR_NONCE1_W2
Definition: MIMXRT1021.h:2814
ENC_Type::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1021.h:13818
ENET_Type::TCR
__IO uint32_t TCR
Definition: MIMXRT1021.h:14342
BEE_Type::AES_KEY0_W0
__O uint32_t AES_KEY0_W0
Definition: MIMXRT1021.h:2803
USB_Type::FRINDEX
__IO uint32_t FRINDEX
Definition: MIMXRT1021.h:34170
USBPHY_Type::PWD_SET
__IO uint32_t PWD_SET
Definition: MIMXRT1021.h:35827
SNVS_Type::HPSVSR
__IO uint32_t HPSVSR
Definition: MIMXRT1021.h:30915
GPIO_Type::DR
__IO uint32_t DR
Definition: MIMXRT1021.h:17858
SPDIF_Type::SIE
__IO uint32_t SIE
Definition: MIMXRT1021.h:32012
ENET_Type::RMON_T_P_GTE2048
__I uint32_t RMON_T_P_GTE2048
Definition: MIMXRT1021.h:14391
DMA_Type::BITER_ELINKYES
__IO uint16_t BITER_ELINKYES
Definition: MIMXRT1021.h:10718
PMU_Type::REG_2P5
__IO uint32_t REG_2P5
Definition: MIMXRT1021.h:25987
CCM_ANALOG_Type::MISC2_SET
__IO uint32_t MISC2_SET
Definition: MIMXRT1021.h:5813
XBARA_Type::SEL42
__IO uint16_t SEL42
Definition: MIMXRT1021.h:39282
PWM_Type::OCTRL
__IO uint16_t OCTRL
Definition: MIMXRT1021.h:27896
XTALOSC24M_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1021.h:40271
CMP_Type::CR1
__IO uint8_t CR1
Definition: MIMXRT1021.h:7775
CMP_Type::FPR
__IO uint8_t FPR
Definition: MIMXRT1021.h:7776
ENET_Type::MRBR
__IO uint32_t MRBR
Definition: MIMXRT1021.h:14360
ENET_Type::RAEM
__IO uint32_t RAEM
Definition: MIMXRT1021.h:14364
CCM_Type::CSCMR1
__IO uint32_t CSCMR1
Definition: MIMXRT1021.h:3951
OCOTP_Type::SRK1
__IO uint32_t SRK1
Definition: MIMXRT1021.h:24866
ENET_Type::RSEM
__IO uint32_t RSEM
Definition: MIMXRT1021.h:14363
XTALOSC24M_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1021.h:40273
XBARA_Type::SEL1
__IO uint16_t SEL1
Definition: MIMXRT1021.h:39241
PWM_Type::FCTRL2
__IO uint16_t FCTRL2
Definition: MIMXRT1021.h:27935
DCP_Type::CHANNELCTRL_TOG
__IO uint32_t CHANNELCTRL_TOG
Definition: MIMXRT1021.h:8975
DMA_Type::DCHPRI2
__IO uint8_t DCHPRI2
Definition: MIMXRT1021.h:10666
AIPSTZ_Type::OPACR1
__IO uint32_t OPACR1
Definition: MIMXRT1021.h:1886
IOMUXC_GPR_Type::GPR14
__IO uint32_t GPR14
Definition: MIMXRT1021.h:19599
BEE_Type::REGION1_TOP
__IO uint32_t REGION1_TOP
Definition: MIMXRT1021.h:2816
CCM_Type::CDHIPR
__I uint32_t CDHIPR
Definition: MIMXRT1021.h:3961
CAN_Type::WORD1
__IO uint32_t WORD1
Definition: MIMXRT1021.h:3129
LPI2C_Type::SSR
__IO uint32_t SSR
Definition: MIMXRT1021.h:22232
PWM_Type::FRACVAL4
__IO uint16_t FRACVAL4
Definition: MIMXRT1021.h:27891
FLEXIO_Type::SHIFTSIEN
__IO uint32_t SHIFTSIEN
Definition: MIMXRT1021.h:16096
LPSPI_Type::DMR0
__IO uint32_t DMR0
Definition: MIMXRT1021.h:23267
I2S_Type::RCR3
__IO uint32_t RCR3
Definition: MIMXRT1021.h:18613
XBARB_Type::SEL3
__IO uint16_t SEL3
Definition: MIMXRT1021.h:40142
CCM_Type::CBCMR
__IO uint32_t CBCMR
Definition: MIMXRT1021.h:3950
CCM_Type::CCGR3
__IO uint32_t CCGR3
Definition: MIMXRT1021.h:3971
SPDIF_Type::STR
__O uint32_t STR
Definition: MIMXRT1021.h:32024
DMA_Type::DCHPRI12
__IO uint8_t DCHPRI12
Definition: MIMXRT1021.h:10680
SEMC_Type::INTR
__IO uint32_t INTR
Definition: MIMXRT1021.h:29726
ENET_Type::IEEE_T_FRAME_OK
__I uint32_t IEEE_T_FRAME_OK
Definition: MIMXRT1021.h:14394
PWM_Type::CNT
__I uint16_t CNT
Definition: MIMXRT1021.h:27879
XBARA_Type::SEL56
__IO uint16_t SEL56
Definition: MIMXRT1021.h:39296
USB_Type::OTGSC
__IO uint32_t OTGSC
Definition: MIMXRT1021.h:34189
CCM_ANALOG_Type::PFD_528_CLR
__IO uint32_t PFD_528_CLR
Definition: MIMXRT1021.h:5801
XBARA_Type::SEL9
__IO uint16_t SEL9
Definition: MIMXRT1021.h:39249
XBARA_Type::SEL54
__IO uint16_t SEL54
Definition: MIMXRT1021.h:39294
ENET_Type::RMON_R_P64
__I uint32_t RMON_R_P64
Definition: MIMXRT1021.h:14415
_xbar_input_signal
_xbar_input_signal
Definition: MIMXRT1021.h:729
OCOTP_Type::SJC_RESP0
__IO uint32_t SJC_RESP0
Definition: MIMXRT1021.h:24880
DMA_Type::DCHPRI5
__IO uint8_t DCHPRI5
Definition: MIMXRT1021.h:10671
PMU_Type::REG_1P1
__IO uint32_t REG_1P1
Definition: MIMXRT1021.h:25979
ENET_Type::RMON_R_FRAG
__I uint32_t RMON_R_FRAG
Definition: MIMXRT1021.h:14412
IOMUXC_GPR_Type::GPR19
__IO uint32_t GPR19
Definition: MIMXRT1021.h:19604
KPP_Type::KDDR
__IO uint16_t KDDR
Definition: MIMXRT1021.h:22068
PMU_Type::MISC1_TOG
__IO uint32_t MISC1_TOG
Definition: MIMXRT1021.h:26002
XBARA_Type::SEL17
__IO uint16_t SEL17
Definition: MIMXRT1021.h:39257
ADC_ETC_Type::TRIGn_CHAIN_1_0
__IO uint32_t TRIGn_CHAIN_1_0
Definition: MIMXRT1021.h:1430
SEMC_Type::SDRAMCR0
__IO uint32_t SDRAMCR0
Definition: MIMXRT1021.h:29727
ENET_Type::RMON_T_DROP
uint32_t RMON_T_DROP
Definition: MIMXRT1021.h:14375
TRNG_Type::SCR1L
__IO uint32_t SCR1L
Definition: MIMXRT1021.h:33495
CCM_Type::CS2CDR
__IO uint32_t CS2CDR
Definition: MIMXRT1021.h:3955
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP
__IO uint32_t SW_PAD_CTL_PAD_WAKEUP
Definition: MIMXRT1021.h:21464
CAN_Type::IFLAG1
__IO uint32_t IFLAG1
Definition: MIMXRT1021.h:3114
SEMC_Type::SRAMCR3
uint32_t SRAMCR3
Definition: MIMXRT1021.h:29742
LPSPI_Type::TDR
__O uint32_t TDR
Definition: MIMXRT1021.h:23275
LPI2C_Type::SAMR
__IO uint32_t SAMR
Definition: MIMXRT1021.h:22239
TMR_Type::CSCTRL
__IO uint16_t CSCTRL
Definition: MIMXRT1021.h:32995
USB_ANALOG_Type::CHRG_DETECT_STAT
__I uint32_t CHRG_DETECT_STAT
Definition: MIMXRT1021.h:36949
USB_Type::USBCMD
__IO uint32_t USBCMD
Definition: MIMXRT1021.h:34167
XBARB_Type::SEL1
__IO uint16_t SEL1
Definition: MIMXRT1021.h:40140
IOMUXC_GPR_Type::GPR9
uint32_t GPR9
Definition: MIMXRT1021.h:19594
PWM_Type::CVAL1CYC
__I uint16_t CVAL1CYC
Definition: MIMXRT1021.h:27913
TEMPMON_Type::TEMPSENSE0_TOG
__IO uint32_t TEMPSENSE0_TOG
Definition: MIMXRT1021.h:32739
TEMPMON_Type::TEMPSENSE1_TOG
__IO uint32_t TEMPSENSE1_TOG
Definition: MIMXRT1021.h:32743
ENET_Type::RMON_T_UNDERSIZE
__I uint32_t RMON_T_UNDERSIZE
Definition: MIMXRT1021.h:14380
TMR_Type::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1021.h:32991
CAN_Type::ECR
__IO uint32_t ECR
Definition: MIMXRT1021.h:3109
DCP_Type::CHANNELCTRL_CLR
__IO uint32_t CHANNELCTRL_CLR
Definition: MIMXRT1021.h:8974
FLEXSPI_Type::LUTKEY
__IO uint32_t LUTKEY
Definition: MIMXRT1021.h:16813
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ
__IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ
Definition: MIMXRT1021.h:21465
USB_Type::ENDPTLISTADDR
__IO uint32_t ENDPTLISTADDR
Definition: MIMXRT1021.h:34178
PMU_Type::MISC1_SET
__IO uint32_t MISC1_SET
Definition: MIMXRT1021.h:26000
XTALOSC24M_Type::LOWPWR_CTRL
__IO uint32_t LOWPWR_CTRL
Definition: MIMXRT1021.h:40276
CCM_Type::CMEOR
__IO uint32_t CMEOR
Definition: MIMXRT1021.h:3976
XBARA_Type::SEL16
__IO uint16_t SEL16
Definition: MIMXRT1021.h:39256
IOMUXC_GPR_Type::GPR16
__IO uint32_t GPR16
Definition: MIMXRT1021.h:19601
USB_Type::ENDPTNAK
__IO uint32_t ENDPTNAK
Definition: MIMXRT1021.h:34184
DMA_Type::HRS
__I uint32_t HRS
Definition: MIMXRT1021.h:10661
USBPHY_Type::PWD_CLR
__IO uint32_t PWD_CLR
Definition: MIMXRT1021.h:35828
TRNG_Type::SCR2C
__I uint32_t SCR2C
Definition: MIMXRT1021.h:33498
TRNG_Type::SCMISC
__IO uint32_t SCMISC
Definition: MIMXRT1021.h:33473
IOMUXC_GPR_Type::GPR11
__IO uint32_t GPR11
Definition: MIMXRT1021.h:19596
GPIO_Type::IMR
__IO uint32_t IMR
Definition: MIMXRT1021.h:17863
TRNG_Type::INT_STATUS
__I uint32_t INT_STATUS
Definition: MIMXRT1021.h:33530
SEMC_Type::SDRAMCR1
__IO uint32_t SDRAMCR1
Definition: MIMXRT1021.h:29728
FLEXSPI_Type::MCR1
__IO uint32_t MCR1
Definition: MIMXRT1021.h:16808
OCOTP_Type::SRK4
__IO uint32_t SRK4
Definition: MIMXRT1021.h:24872
CMP_Type::SCR
__IO uint8_t SCR
Definition: MIMXRT1021.h:7777
PWM_Type::CAPTCTRLB
__IO uint16_t CAPTCTRLB
Definition: MIMXRT1021.h:27906
XBARA_Type::SEL4
__IO uint16_t SEL4
Definition: MIMXRT1021.h:39244
IOMUXC_GPR_Type::GPR13
__IO uint32_t GPR13
Definition: MIMXRT1021.h:19598
SPDIF_Type::SRFM
__I uint32_t SRFM
Definition: MIMXRT1021.h:32028
ENET_Type::RMON_R_OCTETS
__I uint32_t RMON_R_OCTETS
Definition: MIMXRT1021.h:14422
iomuxc_sw_mux_ctl_pad_t
enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
ENET_Type::ATSTMP
__I uint32_t ATSTMP
Definition: MIMXRT1021.h:14437
TEMPMON_Type::TEMPSENSE0_CLR
__IO uint32_t TEMPSENSE0_CLR
Definition: MIMXRT1021.h:32738
SPDIF_Type::SRR
__I uint32_t SRR
Definition: MIMXRT1021.h:32018
DMA_Type::NBYTES_MLOFFYES
__IO uint32_t NBYTES_MLOFFYES
Definition: MIMXRT1021.h:10705
USB_Type::PORTSC1
__IO uint32_t PORTSC1
Definition: MIMXRT1021.h:34187
SRC_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1021.h:32497
TRNG_Type::FRQMAX
__IO uint32_t FRQMAX
Definition: MIMXRT1021.h:33487
OCOTP_Type::TIMING2
__IO uint32_t TIMING2
Definition: MIMXRT1021.h:24830
XBARA_Type::SEL50
__IO uint16_t SEL50
Definition: MIMXRT1021.h:39290
PMU_Type::REG_CORE
__IO uint32_t REG_CORE
Definition: MIMXRT1021.h:25991
DCP_Type::CH2OPTS_TOG
__IO uint32_t CH2OPTS_TOG
Definition: MIMXRT1021.h:9035
OCOTP_Type::SRK0
__IO uint32_t SRK0
Definition: MIMXRT1021.h:24864
GPT_Type::CNT
__I uint32_t CNT
Definition: MIMXRT1021.h:18312
XTALOSC24M_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1021.h:40274
DMA_Type::CSR
__IO uint16_t CSR
Definition: MIMXRT1021.h:10715
LPSPI_Type::DER
__IO uint32_t DER
Definition: MIMXRT1021.h:23263
RTWDOG_Type::CS
__IO uint32_t CS
Definition: MIMXRT1021.h:29521
PMU_Type::REG_CORE_SET
__IO uint32_t REG_CORE_SET
Definition: MIMXRT1021.h:25992
DCP_Type::DBGSELECT
__IO uint32_t DBGSELECT
Definition: MIMXRT1021.h:9049
CCM_ANALOG_Type::PLL_AUDIO_NUM
__IO uint32_t PLL_AUDIO_NUM
Definition: MIMXRT1021.h:5787
PWM_Type::DMAEN
__IO uint16_t DMAEN
Definition: MIMXRT1021.h:27899
XBARA_Type::SEL28
__IO uint16_t SEL28
Definition: MIMXRT1021.h:39268
CCM_ANALOG_Type::MISC1_TOG
__IO uint32_t MISC1_TOG
Definition: MIMXRT1021.h:5811
IOMUXC_SNVS_GPR_Type::GPR2
uint32_t GPR2
Definition: MIMXRT1021.h:21968
TRNG_Type::PKRCNTFE
__I uint32_t PKRCNTFE
Definition: MIMXRT1021.h:33526
OCOTP_Type::GP2
__IO uint32_t GP2
Definition: MIMXRT1021.h:24892
EWM_Type::CLKPRESCALER
__IO uint8_t CLKPRESCALER
Definition: MIMXRT1021.h:15973
ADC_ETC_Type::DONE0_1_IRQ
__IO uint32_t DONE0_1_IRQ
Definition: MIMXRT1021.h:1424
BEE_Type::STATUS
__IO uint32_t STATUS
Definition: MIMXRT1021.h:2807
ENET_Type::ATCOR
__IO uint32_t ATCOR
Definition: MIMXRT1021.h:14435
DMA_Type::DCHPRI14
__IO uint8_t DCHPRI14
Definition: MIMXRT1021.h:10678
DMA_Type::CR
__IO uint32_t CR
Definition: MIMXRT1021.h:10642
DMA_Type::DCHPRI8
__IO uint8_t DCHPRI8
Definition: MIMXRT1021.h:10676
SPDIF_Type::SRQ
__I uint32_t SRQ
Definition: MIMXRT1021.h:32022
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF
__IO uint32_t SW_PAD_CTL_PAD_ONOFF
Definition: MIMXRT1021.h:21463
XBARA_Type::SEL53
__IO uint16_t SEL53
Definition: MIMXRT1021.h:39293
XBARA_Type::SEL32
__IO uint16_t SEL32
Definition: MIMXRT1021.h:39272
ENET_Type::RMON_T_BC_PKT
__I uint32_t RMON_T_BC_PKT
Definition: MIMXRT1021.h:14377
TMR_Type::SCTRL
__IO uint16_t SCTRL
Definition: MIMXRT1021.h:32992
DCP_Type::PACKET0
__I uint32_t PACKET0
Definition: MIMXRT1021.h:8986
ENET_Type::IEEE_T_OCTETS_OK
__I uint32_t IEEE_T_OCTETS_OK
Definition: MIMXRT1021.h:14404
_xbar_output_signal
_xbar_output_signal
Definition: MIMXRT1021.h:879
PIT_Type::LDVAL
__IO uint32_t LDVAL
Definition: MIMXRT1021.h:25826
LPUART_Type::DATA
__IO uint32_t DATA
Definition: MIMXRT1021.h:23889
_iomuxc_sw_pad_ctl_pad
_iomuxc_sw_pad_ctl_pad
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Definition: MIMXRT1021.h:507
TRNG_Type::SCR1C
__I uint32_t SCR1C
Definition: MIMXRT1021.h:33494
DCP_Type::CH1STAT_TOG
__IO uint32_t CH1STAT_TOG
Definition: MIMXRT1021.h:9019
OCOTP_Type::MISC_CONF1
__IO uint32_t MISC_CONF1
Definition: MIMXRT1021.h:24906
ENET_Type::RMON_T_P128TO255
__I uint32_t RMON_T_P128TO255
Definition: MIMXRT1021.h:14387
ENET_Type::RMON_R_CRC_ALIGN
__I uint32_t RMON_R_CRC_ALIGN
Definition: MIMXRT1021.h:14409
ADC_ETC_Type::DONE2_ERR_IRQ
__IO uint32_t DONE2_ERR_IRQ
Definition: MIMXRT1021.h:1425
ADC_ETC_Type::TRIGn_RESULT_7_6
__I uint32_t TRIGn_RESULT_7_6
Definition: MIMXRT1021.h:1437
DMA_Type::DCHPRI7
__IO uint8_t DCHPRI7
Definition: MIMXRT1021.h:10669
CCM_ANALOG_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1021.h:5806
IOMUXC_GPR_Type::GPR12
__IO uint32_t GPR12
Definition: MIMXRT1021.h:19597
DMA_Type::NBYTES_MLOFFNO
__IO uint32_t NBYTES_MLOFFNO
Definition: MIMXRT1021.h:10704
GPIO_Type::ISR
__IO uint32_t ISR
Definition: MIMXRT1021.h:17864
PWM_Type::VAL0
__IO uint16_t VAL0
Definition: MIMXRT1021.h:27884
GPIO_Type::PSR
__I uint32_t PSR
Definition: MIMXRT1021.h:17860
PWM_Type::VAL2
__IO uint16_t VAL2
Definition: MIMXRT1021.h:27888
ENC_Type::WTR
__IO uint16_t WTR
Definition: MIMXRT1021.h:13820
SEMC_Type::NORCR2
__IO uint32_t NORCR2
Definition: MIMXRT1021.h:29737
XBARA_Type::SEL13
__IO uint16_t SEL13
Definition: MIMXRT1021.h:39253
ENC_Type::IMR
__I uint16_t IMR
Definition: MIMXRT1021.h:13831
CMP_Type::MUXCR
__IO uint8_t MUXCR
Definition: MIMXRT1021.h:7779
ADC_ETC_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1021.h:1423
DCP_Type::CH3OPTS_CLR
__IO uint32_t CH3OPTS_CLR
Definition: MIMXRT1021.h:9046
DCP_Type::KEY
__IO uint32_t KEY
Definition: MIMXRT1021.h:8982
PMU_Type::MISC1_CLR
__IO uint32_t MISC1_CLR
Definition: MIMXRT1021.h:26001
OCOTP_Type::SW_GP1
__IO uint32_t SW_GP1
Definition: MIMXRT1021.h:24894
WDOG_Type::WICR
__IO uint16_t WICR
Definition: MIMXRT1021.h:39045
LPUART_Type::FIFO
__IO uint32_t FIFO
Definition: MIMXRT1021.h:23892
ENC_Type::UMOD
__IO uint16_t UMOD
Definition: MIMXRT1021.h:13834
SNVS_Type::HPSR
__IO uint32_t HPSR
Definition: MIMXRT1021.h:30914
DMA_Type::CINT
__O uint8_t CINT
Definition: MIMXRT1021.h:10655
ENET_Type::RMON_T_P65TO127
__I uint32_t RMON_T_P65TO127
Definition: MIMXRT1021.h:14386
OCOTP_Type::MAC0
__IO uint32_t MAC0
Definition: MIMXRT1021.h:24884
PMU_Type::REG_2P5_CLR
__IO uint32_t REG_2P5_CLR
Definition: MIMXRT1021.h:25989
ENET_Type::IEEE_T_DROP
uint32_t IEEE_T_DROP
Definition: MIMXRT1021.h:14393
DCDC_Type::REG0
__IO uint32_t REG0
Definition: MIMXRT1021.h:8639
USDHC_Type::CLK_TUNE_CTRL_STATUS
__IO uint32_t CLK_TUNE_CTRL_STATUS
Definition: MIMXRT1021.h:37419
FLEXIO_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1021.h:16089
DCP_Type::CH1SEMA
__IO uint32_t CH1SEMA
Definition: MIMXRT1021.h:9014
XBARA_Type::CTRL0
__IO uint16_t CTRL0
Definition: MIMXRT1021.h:39306
PWM_Type::FRACVAL5
__IO uint16_t FRACVAL5
Definition: MIMXRT1021.h:27893
XBARA_Type::SEL33
__IO uint16_t SEL33
Definition: MIMXRT1021.h:39273
ENC_Type::FILT
__IO uint16_t FILT
Definition: MIMXRT1021.h:13819
IOMUXC_GPR_Type::GPR8
__IO uint32_t GPR8
Definition: MIMXRT1021.h:19593
USB_ANALOG_Type::VBUS_DETECT_SET
__IO uint32_t VBUS_DETECT_SET
Definition: MIMXRT1021.h:36940
TRNG_Type::SCR4L
__IO uint32_t SCR4L
Definition: MIMXRT1021.h:33507
USBPHY_Type::PWD
__IO uint32_t PWD
Definition: MIMXRT1021.h:35826
USDHC_Type::WTMK_LVL
__IO uint32_t WTMK_LVL
Definition: MIMXRT1021.h:37410
DCP_Type::CH1OPTS_SET
__IO uint32_t CH1OPTS_SET
Definition: MIMXRT1021.h:9021
GPT_Type::PR
__IO uint32_t PR
Definition: MIMXRT1021.h:18307
XBARB_Type::SEL5
__IO uint16_t SEL5
Definition: MIMXRT1021.h:40144
ENET_Type::MIBC
__IO uint32_t MIBC
Definition: MIMXRT1021.h:14338
ENET_Type::IEEE_T_CSERR
__I uint32_t IEEE_T_CSERR
Definition: MIMXRT1021.h:14401
FLEXIO_Type::SHIFTERR
__IO uint32_t SHIFTERR
Definition: MIMXRT1021.h:16093
SEMC_Type::STS15
uint32_t STS15
Definition: MIMXRT1021.h:29769
CCM_Type::CSCDR2
__IO uint32_t CSCDR2
Definition: MIMXRT1021.h:3958
USB_Type::ENDPTSTAT
__I uint32_t ENDPTSTAT
Definition: MIMXRT1021.h:34194
DMA_Type::DCHPRI21
__IO uint8_t DCHPRI21
Definition: MIMXRT1021.h:10687
ENC_Type::LPOSH
__I uint16_t LPOSH
Definition: MIMXRT1021.h:13828
XTALOSC24M_Type::OSC_CONFIG2_SET
__IO uint32_t OSC_CONFIG2_SET
Definition: MIMXRT1021.h:40290
USB_Type::HCSPARAMS
__I uint32_t HCSPARAMS
Definition: MIMXRT1021.h:34160
ENC_Type::TST
__IO uint16_t TST
Definition: MIMXRT1021.h:13832
SEMC_Type::NORCR0
__IO uint32_t NORCR0
Definition: MIMXRT1021.h:29735
I2S_Type::RCR1
__IO uint32_t RCR1
Definition: MIMXRT1021.h:18611
PWM_Type::FFILT
__IO uint16_t FFILT
Definition: MIMXRT1021.h:27933
DMA_Type::DCHPRI27
__IO uint8_t DCHPRI27
Definition: MIMXRT1021.h:10689
SEMC_Type::STS5
uint32_t STS5
Definition: MIMXRT1021.h:29759
LPI2C_Type::MCCR1
__IO uint32_t MCCR1
Definition: MIMXRT1021.h:22223
ENET_Type::RSFL
__IO uint32_t RSFL
Definition: MIMXRT1021.h:14362
ENET_Type::TACC
__IO uint32_t TACC
Definition: MIMXRT1021.h:14372
CAN_Type::ESR2
__I uint32_t ESR2
Definition: MIMXRT1021.h:3116
TEMPMON_Type::TEMPSENSE1
__IO uint32_t TEMPSENSE1
Definition: MIMXRT1021.h:32740
LPI2C_Type::MDER
__IO uint32_t MDER
Definition: MIMXRT1021.h:22213
LPSPI_Type::CFGR0
__IO uint32_t CFGR0
Definition: MIMXRT1021.h:23264
USBPHY_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1021.h:35839
ENET_Type::OPD
__IO uint32_t OPD
Definition: MIMXRT1021.h:14346
SPDIF_Type::SIS
__I uint32_t SIS
Definition: MIMXRT1021.h:32015
CAN_Type::CTRL1
__IO uint32_t CTRL1
Definition: MIMXRT1021.h:3103
iomuxc_sw_pad_ctl_pad_t
enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
DMA_Type::DCHPRI24
__IO uint8_t DCHPRI24
Definition: MIMXRT1021.h:10692
I2S_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1021.h:18597
CCM_ANALOG_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1021.h:5805
DCP_Type::CH0SEMA
__IO uint32_t CH0SEMA
Definition: MIMXRT1021.h:9002
GPT_Type::IR
__IO uint32_t IR
Definition: MIMXRT1021.h:18309
ENET_Type::IEEE_R_DROP
__I uint32_t IEEE_R_DROP
Definition: MIMXRT1021.h:14423
TEMPMON_Type::TEMPSENSE1_SET
__IO uint32_t TEMPSENSE1_SET
Definition: MIMXRT1021.h:32741
FLEXRAM_Type::TCM_CTRL
__IO uint32_t TCM_CTRL
Definition: MIMXRT1021.h:16659
XBARA_Type::SEL2
__IO uint16_t SEL2
Definition: MIMXRT1021.h:39242
LPSPI_Type::IER
__IO uint32_t IER
Definition: MIMXRT1021.h:23262
USBPHY_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1021.h:35840
USBPHY_Type::DEBUG1_TOG
__IO uint32_t DEBUG1_TOG
Definition: MIMXRT1021.h:35853
PWM_Type::FRACVAL3
__IO uint16_t FRACVAL3
Definition: MIMXRT1021.h:27889
SEMC_Type::STS4
uint32_t STS4
Definition: MIMXRT1021.h:29758
XBARA_Type::SEL19
__IO uint16_t SEL19
Definition: MIMXRT1021.h:39259
USB_Type::DCCPARAMS
__I uint32_t DCCPARAMS
Definition: MIMXRT1021.h:34165
ENET_Type::ATOFF
__IO uint32_t ATOFF
Definition: MIMXRT1021.h:14433
DMA_Type::DCHPRI23
__IO uint8_t DCHPRI23
Definition: MIMXRT1021.h:10685
FLEXIO_Type::SHIFTSDEN
__IO uint32_t SHIFTSDEN
Definition: MIMXRT1021.h:16100
PWM_Type::INIT
__IO uint16_t INIT
Definition: MIMXRT1021.h:27880
XTALOSC24M_Type::OSC_CONFIG0_SET
__IO uint32_t OSC_CONFIG0_SET
Definition: MIMXRT1021.h:40282
CCM_Type::CSR
__I uint32_t CSR
Definition: MIMXRT1021.h:3946
CAN_Type::CTRL2
__IO uint32_t CTRL2
Definition: MIMXRT1021.h:3115
ENET_Type::RXIC
__IO uint32_t RXIC
Definition: MIMXRT1021.h:14349
LPUART_Type::GLOBAL
__IO uint32_t GLOBAL
Definition: MIMXRT1021.h:23884
XBARB_Type::SEL6
__IO uint16_t SEL6
Definition: MIMXRT1021.h:40145
PWM_Type::SWCOUT
__IO uint16_t SWCOUT
Definition: MIMXRT1021.h:27927
_iomuxc_select_input
_iomuxc_select_input
Enumeration for the IOMUXC select input.
Definition: MIMXRT1021.h:611
USB_Type::HWRXBUF
__I uint32_t HWRXBUF
Definition: MIMXRT1021.h:34149
CCM_ANALOG_Type::PLL_USB1_SET
__IO uint32_t PLL_USB1_SET
Definition: MIMXRT1021.h:5769
PWM_Type::CVAL1
__I uint16_t CVAL1
Definition: MIMXRT1021.h:27912
XBARA_Type::SEL31
__IO uint16_t SEL31
Definition: MIMXRT1021.h:39271
RTWDOG_Type::WIN
__IO uint32_t WIN
Definition: MIMXRT1021.h:29524
SPDIF_Type::SRPC
__IO uint32_t SRPC
Definition: MIMXRT1021.h:32011
PWM_Type::MCTRL
__IO uint16_t MCTRL
Definition: MIMXRT1021.h:27929
DCP_Type::CH1STAT_CLR
__IO uint32_t CH1STAT_CLR
Definition: MIMXRT1021.h:9018
USDHC_Type::PRES_STATE
__I uint32_t PRES_STATE
Definition: MIMXRT1021.h:37402
ENET_Type::PALR
__IO uint32_t PALR
Definition: MIMXRT1021.h:14344
ENET_Type::TSEM
__IO uint32_t TSEM
Definition: MIMXRT1021.h:14366
OCOTP_Type::READ_FUSE_DATA
__IO uint32_t READ_FUSE_DATA
Definition: MIMXRT1021.h:24819
GPIO_Type::DR_CLEAR
__O uint32_t DR_CLEAR
Definition: MIMXRT1021.h:17868
DCP_Type::CH3OPTS_SET
__IO uint32_t CH3OPTS_SET
Definition: MIMXRT1021.h:9045
LPSPI_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1021.h:23258
SEMC_Type::STS0
__I uint32_t STS0
Definition: MIMXRT1021.h:29754
DMA_Type::DCHPRI30
__IO uint8_t DCHPRI30
Definition: MIMXRT1021.h:10694
DMA_Type::DCHPRI0
__IO uint8_t DCHPRI0
Definition: MIMXRT1021.h:10668
SEMC_Type::STS10
uint32_t STS10
Definition: MIMXRT1021.h:29764
LPSPI_Type::FSR
__I uint32_t FSR
Definition: MIMXRT1021.h:23273
TRNG_Type::SCR5C
__I uint32_t SCR5C
Definition: MIMXRT1021.h:33510
XTALOSC24M_Type::OSC_CONFIG2_CLR
__IO uint32_t OSC_CONFIG2_CLR
Definition: MIMXRT1021.h:40291
DCP_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1021.h:8964
OCOTP_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1021.h:24812
USB_Type::HCCPARAMS
__I uint32_t HCCPARAMS
Definition: MIMXRT1021.h:34161
SEMC_Type::BMCR1
__IO uint32_t BMCR1
Definition: MIMXRT1021.h:29722
USB_Type::USBSTS
__IO uint32_t USBSTS
Definition: MIMXRT1021.h:34168
SEMC_Type::NORCR3
uint32_t NORCR3
Definition: MIMXRT1021.h:29738
LPUART_Type::MATCH
__IO uint32_t MATCH
Definition: MIMXRT1021.h:23890
USDHC_Type::TUNING_CTRL
__IO uint32_t TUNING_CTRL
Definition: MIMXRT1021.h:37424
OCOTP_Type::DATA
__IO uint32_t DATA
Definition: MIMXRT1021.h:24815
SNVS_Type::LPSMCLR
__IO uint32_t LPSMCLR
Definition: MIMXRT1021.h:30933
OCOTP_Type::SRK6
__IO uint32_t SRK6
Definition: MIMXRT1021.h:24876
FLEXSPI_Type::STS2
__I uint32_t STS2
Definition: MIMXRT1021.h:16834
USBPHY_Type::DEBUG_SET
__IO uint32_t DEBUG_SET
Definition: MIMXRT1021.h:35845
OCOTP_Type::SW_GP21
__IO uint32_t SW_GP21
Definition: MIMXRT1021.h:24898
SPDIF_Type::STCSCH
__IO uint32_t STCSCH
Definition: MIMXRT1021.h:32025
IOMUXC_GPR_Type::GPR6
__IO uint32_t GPR6
Definition: MIMXRT1021.h:19591
XBARA_Type::SEL25
__IO uint16_t SEL25
Definition: MIMXRT1021.h:39265
XBARA_Type::SEL48
__IO uint16_t SEL48
Definition: MIMXRT1021.h:39288
PWM_Type::CVAL0CYC
__I uint16_t CVAL0CYC
Definition: MIMXRT1021.h:27911
OCOTP_Type::CFG5
__IO uint32_t CFG5
Definition: MIMXRT1021.h:24844
EWM_Type::SERV
__O uint8_t SERV
Definition: MIMXRT1021.h:15969
TRNG_Type::VID2
__I uint32_t VID2
Definition: MIMXRT1021.h:33533
LPSPI_Type::SR
__IO uint32_t SR
Definition: MIMXRT1021.h:23261
SEMC_Type::STS8
uint32_t STS8
Definition: MIMXRT1021.h:29762
SEMC_Type::SRAMCR0
__IO uint32_t SRAMCR0
Definition: MIMXRT1021.h:29739
BEE_Type::CTR_NONCE1_W1
__O uint32_t CTR_NONCE1_W1
Definition: MIMXRT1021.h:2813
XBARA_Type::SEL46
__IO uint16_t SEL46
Definition: MIMXRT1021.h:39286
ENET_Type::RMON_R_P_GTE2048
__I uint32_t RMON_R_P_GTE2048
Definition: MIMXRT1021.h:14421
SEMC_Type::STS14
uint32_t STS14
Definition: MIMXRT1021.h:29768
PWM_Type::VAL5
__IO uint16_t VAL5
Definition: MIMXRT1021.h:27894
PWM_Type::CVAL3
__I uint16_t CVAL3
Definition: MIMXRT1021.h:27916
DCP_Type::CH2OPTS_SET
__IO uint32_t CH2OPTS_SET
Definition: MIMXRT1021.h:9033
ENET_Type::IEEE_T_FDXFC
__I uint32_t IEEE_T_FDXFC
Definition: MIMXRT1021.h:14403
OCOTP_Type::SCS_CLR
__IO uint32_t SCS_CLR
Definition: MIMXRT1021.h:24825
DMA_Type::DCHPRI26
__IO uint8_t DCHPRI26
Definition: MIMXRT1021.h:10690
FLEXIO_Type::SHIFTSTATE
__IO uint32_t SHIFTSTATE
Definition: MIMXRT1021.h:16102
ENET_Type::RMON_T_COL
__I uint32_t RMON_T_COL
Definition: MIMXRT1021.h:14384
TRNG_Type::PKRSQ
__I uint32_t PKRSQ
Definition: MIMXRT1021.h:33477
XBARB_Type::SEL7
__IO uint16_t SEL7
Definition: MIMXRT1021.h:40146
SEMC_Type::STS3
uint32_t STS3
Definition: MIMXRT1021.h:29757
XBARA_Type::SEL38
__IO uint16_t SEL38
Definition: MIMXRT1021.h:39278
USDHC_Type::CMD_ARG
__IO uint32_t CMD_ARG
Definition: MIMXRT1021.h:37395
KPP_Type::KPCR
__IO uint16_t KPCR
Definition: MIMXRT1021.h:22066
CCM_ANALOG_Type::PLL_SYS
__IO uint32_t PLL_SYS
Definition: MIMXRT1021.h:5773
SEMC_Type::DBICR1
__IO uint32_t DBICR1
Definition: MIMXRT1021.h:29744
I2S_Type::TCR5
__IO uint32_t TCR5
Definition: MIMXRT1021.h:18603
USBPHY_Type::DEBUGr
__IO uint32_t DEBUGr
Definition: MIMXRT1021.h:35844
CCM_ANALOG_Type::MISC1_SET
__IO uint32_t MISC1_SET
Definition: MIMXRT1021.h:5809
OCOTP_Type::MAC1
__IO uint32_t MAC1
Definition: MIMXRT1021.h:24886
SEMC_Type::STS1
uint32_t STS1
Definition: MIMXRT1021.h:29755
DMA_Type::EARS
__IO uint32_t EARS
Definition: MIMXRT1021.h:10663
GPIO_Type::GDIR
__IO uint32_t GDIR
Definition: MIMXRT1021.h:17859
DCP_Type::CH0OPTS_CLR
__IO uint32_t CH0OPTS_CLR
Definition: MIMXRT1021.h:9010
PMU_Type::MISC1
__IO uint32_t MISC1
Definition: MIMXRT1021.h:25999
ENET_Type::RMON_R_OVERSIZE
__I uint32_t RMON_R_OVERSIZE
Definition: MIMXRT1021.h:14411
EWM_Type::CMPH
__IO uint8_t CMPH
Definition: MIMXRT1021.h:15971
CCM_Type::CCGR5
__IO uint32_t CCGR5
Definition: MIMXRT1021.h:3973
USDHC_Type::CMD_RSP0
__I uint32_t CMD_RSP0
Definition: MIMXRT1021.h:37397
LPI2C_Type::SCFGR2
__IO uint32_t SCFGR2
Definition: MIMXRT1021.h:22237
FLEXSPI_Type::IPTXFCR
__IO uint32_t IPTXFCR
Definition: MIMXRT1021.h:16829
LPI2C_Type::SCFGR1
__IO uint32_t SCFGR1
Definition: MIMXRT1021.h:22236
USB_ANALOG_Type::CHRG_DETECT
__IO uint32_t CHRG_DETECT
Definition: MIMXRT1021.h:36943
PGC_Type::MEGA_PDNSCR
__IO uint32_t MEGA_PDNSCR
Definition: MIMXRT1021.h:25686
PMU_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1021.h:25995
LPI2C_Type::SRDR
__I uint32_t SRDR
Definition: MIMXRT1021.h:22246
ENET_Type::RMON_T_P1024TO2047
__I uint32_t RMON_T_P1024TO2047
Definition: MIMXRT1021.h:14390
BEE_Type::CTR_NONCE0_W3
__O uint32_t CTR_NONCE0_W3
Definition: MIMXRT1021.h:2811
LPSPI_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1021.h:23257
ENET_Type::ATPER
__IO uint32_t ATPER
Definition: MIMXRT1021.h:14434
DMA_Type::CDNE
__O uint8_t CDNE
Definition: MIMXRT1021.h:10652
DMA_Type::CITER_ELINKNO
__IO uint16_t CITER_ELINKNO
Definition: MIMXRT1021.h:10711
PWM_Type::DTCNT1
__IO uint16_t DTCNT1
Definition: MIMXRT1021.h:27903
DCP_Type::CH1STAT_SET
__IO uint32_t CH1STAT_SET
Definition: MIMXRT1021.h:9017
USB_ANALOG_Type::MISC_TOG
__IO uint32_t MISC_TOG
Definition: MIMXRT1021.h:36958
CCM_ANALOG_Type::PLL_SYS_DENOM
__IO uint32_t PLL_SYS_DENOM
Definition: MIMXRT1021.h:5781
CCM_ANALOG_Type::PLL_SYS_TOG
__IO uint32_t PLL_SYS_TOG
Definition: MIMXRT1021.h:5776
SEMC_Type::INTEN
__IO uint32_t INTEN
Definition: MIMXRT1021.h:29725
XBARA_Type::SEL44
__IO uint16_t SEL44
Definition: MIMXRT1021.h:39284
XBARA_Type::SEL18
__IO uint16_t SEL18
Definition: MIMXRT1021.h:39258
ADC_ETC_Type::TRIGn_RESULT_5_4
__I uint32_t TRIGn_RESULT_5_4
Definition: MIMXRT1021.h:1436
CCM_ANALOG_Type::PLL_SYS_SET
__IO uint32_t PLL_SYS_SET
Definition: MIMXRT1021.h:5774
XTALOSC24M_Type::OSC_CONFIG1_SET
__IO uint32_t OSC_CONFIG1_SET
Definition: MIMXRT1021.h:40286
TRNG_Type::SCML
__IO uint32_t SCML
Definition: MIMXRT1021.h:33491
CCM_Type::CDCDR
__IO uint32_t CDCDR
Definition: MIMXRT1021.h:3956
XBARA_Type::SEL52
__IO uint16_t SEL52
Definition: MIMXRT1021.h:39292
PMU_Type::REG_3P0
__IO uint32_t REG_3P0
Definition: MIMXRT1021.h:25983
EWM_Type::CMPL
__IO uint8_t CMPL
Definition: MIMXRT1021.h:15970
DMA_Type::SSRT
__O uint8_t SSRT
Definition: MIMXRT1021.h:10653
DCP_Type::CH2STAT_TOG
__IO uint32_t CH2STAT_TOG
Definition: MIMXRT1021.h:9031
CAN_Type::WORD0
__IO uint32_t WORD0
Definition: MIMXRT1021.h:3128
DMA_Type::NBYTES_MLNO
__IO uint32_t NBYTES_MLNO
Definition: MIMXRT1021.h:10703
DCP_Type::CH3OPTS
__IO uint32_t CH3OPTS
Definition: MIMXRT1021.h:9044
IOMUXC_GPR_Type::GPR2
__IO uint32_t GPR2
Definition: MIMXRT1021.h:19587
ENET_Type::IEEE_T_MACERR
__I uint32_t IEEE_T_MACERR
Definition: MIMXRT1021.h:14400
CAN_Type::IFLAG2
__IO uint32_t IFLAG2
Definition: MIMXRT1021.h:3113
USDHC_Type::AUTOCMD12_ERR_STATUS
__IO uint32_t AUTOCMD12_ERR_STATUS
Definition: MIMXRT1021.h:37408
DCP_Type::CH3SEMA
__IO uint32_t CH3SEMA
Definition: MIMXRT1021.h:9038
TRNG_Type::FRQCNT
__I uint32_t FRQCNT
Definition: MIMXRT1021.h:33486
USDHC_Type::VEND_SPEC
__IO uint32_t VEND_SPEC
Definition: MIMXRT1021.h:37421
DCP_Type::CH0STAT_TOG
__IO uint32_t CH0STAT_TOG
Definition: MIMXRT1021.h:9007
DCP_Type::CH1STAT
__IO uint32_t CH1STAT
Definition: MIMXRT1021.h:9016
CAN_Type::ESR1
__IO uint32_t ESR1
Definition: MIMXRT1021.h:3110
LPUART_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1021.h:23883
USDHC_Type::DS_ADDR
__IO uint32_t DS_ADDR
Definition: MIMXRT1021.h:37393
LPI2C_Type::STAR
__IO uint32_t STAR
Definition: MIMXRT1021.h:22242
PMU_Type::MISC2_TOG
__IO uint32_t MISC2_TOG
Definition: MIMXRT1021.h:26006
DCP_Type::CH3STAT_TOG
__IO uint32_t CH3STAT_TOG
Definition: MIMXRT1021.h:9043
GPC_Type::IMR5
__IO uint32_t IMR5
Definition: MIMXRT1021.h:17734
CCM_ANALOG_Type::PLL_SYS_NUM
__IO uint32_t PLL_SYS_NUM
Definition: MIMXRT1021.h:5779
CAN_Type::ID
__IO uint32_t ID
Definition: MIMXRT1021.h:3127
USB_Type::SBUSCFG
__IO uint32_t SBUSCFG
Definition: MIMXRT1021.h:34155
DCP_Type::CH0STAT_CLR
__IO uint32_t CH0STAT_CLR
Definition: MIMXRT1021.h:9006
SNVS_Type::LPSRTCMR
__IO uint32_t LPSRTCMR
Definition: MIMXRT1021.h:30929
USDHC_Type::HOST_CTRL_CAP
__IO uint32_t HOST_CTRL_CAP
Definition: MIMXRT1021.h:37409
ADC_ETC_Type::TRIGn_RESULT_3_2
__I uint32_t TRIGn_RESULT_3_2
Definition: MIMXRT1021.h:1435
PMU_Type::REG_3P0_CLR
__IO uint32_t REG_3P0_CLR
Definition: MIMXRT1021.h:25985
DMA_Type::SADDR
__IO uint32_t SADDR
Definition: MIMXRT1021.h:10699
USDHC_Type::ADMA_ERR_STATUS
__I uint32_t ADMA_ERR_STATUS
Definition: MIMXRT1021.h:37414
OCOTP_Type::MEM2
__IO uint32_t MEM2
Definition: MIMXRT1021.h:24852
SNVS_Type::LPCR
__IO uint32_t LPCR
Definition: MIMXRT1021.h:30923
FLEXSPI_Type::IPCR0
__IO uint32_t IPCR0
Definition: MIMXRT1021.h:16823
TMR_Type::COMP2
__IO uint16_t COMP2
Definition: MIMXRT1021.h:32986
CCM_ANALOG_Type::MISC1
__IO uint32_t MISC1
Definition: MIMXRT1021.h:5808
DMA_Type::SEEI
__O uint8_t SEEI
Definition: MIMXRT1021.h:10649
USDHC_Type::MIX_CTRL
__IO uint32_t MIX_CTRL
Definition: MIMXRT1021.h:37411
ENET_Type::TDAR
__IO uint32_t TDAR
Definition: MIMXRT1021.h:14331
ENC_Type::REVH
__I uint16_t REVH
Definition: MIMXRT1021.h:13824
USDHC_Type::FORCE_EVENT
__O uint32_t FORCE_EVENT
Definition: MIMXRT1021.h:37413
XBARA_Type::SEL59
__IO uint16_t SEL59
Definition: MIMXRT1021.h:39299
LPI2C_Type::SIER
__IO uint32_t SIER
Definition: MIMXRT1021.h:22233
XBARA_Type::SEL40
__IO uint16_t SEL40
Definition: MIMXRT1021.h:39280
OCOTP_Type::CFG6
__IO uint32_t CFG6
Definition: MIMXRT1021.h:24846
OCOTP_Type::MEM1
__IO uint32_t MEM1
Definition: MIMXRT1021.h:24850
IOMUXC_GPR_Type::GPR18
__IO uint32_t GPR18
Definition: MIMXRT1021.h:19603
DMA_Type::SERQ
__O uint8_t SERQ
Definition: MIMXRT1021.h:10651
TRNG_Type::SDCTL
__IO uint32_t SDCTL
Definition: MIMXRT1021.h:33479
PMU_Type::REG_2P5_SET
__IO uint32_t REG_2P5_SET
Definition: MIMXRT1021.h:25988
PMU_Type::MISC2
__IO uint32_t MISC2
Definition: MIMXRT1021.h:26003
PMU_Type::REG_3P0_TOG
__IO uint32_t REG_3P0_TOG
Definition: MIMXRT1021.h:25986
SEMC_Type::STS6
uint32_t STS6
Definition: MIMXRT1021.h:29760
LPSPI_Type::RDR
__I uint32_t RDR
Definition: MIMXRT1021.h:23278
USDHC_Type::CMD_RSP2
__I uint32_t CMD_RSP2
Definition: MIMXRT1021.h:37399
DMA_Type::DCHPRI20
__IO uint8_t DCHPRI20
Definition: MIMXRT1021.h:10688
ADC_Type::HS
__I uint32_t HS
Definition: MIMXRT1021.h:1080
LPUART_Type::MODIR
__IO uint32_t MODIR
Definition: MIMXRT1021.h:23891
ENET_Type::TDSR
__IO uint32_t TDSR
Definition: MIMXRT1021.h:14359
DMA_Type::CERQ
__O uint8_t CERQ
Definition: MIMXRT1021.h:10650
GPIO_Type::ICR2
__IO uint32_t ICR2
Definition: MIMXRT1021.h:17862
DMA_Type::DCHPRI28
__IO uint8_t DCHPRI28
Definition: MIMXRT1021.h:10696
XTALOSC24M_Type::OSC_CONFIG2
__IO uint32_t OSC_CONFIG2
Definition: MIMXRT1021.h:40289
USBPHY_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1021.h:35838
DCP_Type::CH1OPTS
__IO uint32_t CH1OPTS
Definition: MIMXRT1021.h:9020
SEMC_Type::SRAMCR1
__IO uint32_t SRAMCR1
Definition: MIMXRT1021.h:29740
BEE_Type::CTR_NONCE1_W0
__O uint32_t CTR_NONCE1_W0
Definition: MIMXRT1021.h:2812
SPDIF_Type::SRCSL
__I uint32_t SRCSL
Definition: MIMXRT1021.h:32020
USB_ANALOG_Type::MISC
__IO uint32_t MISC
Definition: MIMXRT1021.h:36955
BEE_Type::ADDR_OFFSET1
__IO uint32_t ADDR_OFFSET1
Definition: MIMXRT1021.h:2802
ENET_Type::IEEE_T_1COL
__I uint32_t IEEE_T_1COL
Definition: MIMXRT1021.h:14395
SNVS_Type::HPCR
__IO uint32_t HPCR
Definition: MIMXRT1021.h:30911
PWM_Type::CTRL2
__IO uint16_t CTRL2
Definition: MIMXRT1021.h:27881
USB_Type::CONFIGFLAG
__I uint32_t CONFIGFLAG
Definition: MIMXRT1021.h:34186
ENET_Type::IAUR
__IO uint32_t IAUR
Definition: MIMXRT1021.h:14351
SEMC_Type::IPCR0
__IO uint32_t IPCR0
Definition: MIMXRT1021.h:29746
DMA_Type::SLAST
__IO int32_t SLAST
Definition: MIMXRT1021.h:10707
USB_ANALOG_Type::LOOPBACK_SET
__IO uint32_t LOOPBACK_SET
Definition: MIMXRT1021.h:36952
DCP_Type::CH2CMDPTR
__IO uint32_t CH2CMDPTR
Definition: MIMXRT1021.h:9024
CCM_ANALOG_Type::PLL_ENET_SET
__IO uint32_t PLL_ENET_SET
Definition: MIMXRT1021.h:5792
ENET_Type::RMON_R_BC_PKT
__I uint32_t RMON_R_BC_PKT
Definition: MIMXRT1021.h:14407
OCOTP_Type::MEM0
__IO uint32_t MEM0
Definition: MIMXRT1021.h:24848
TEMPMON_Type::TEMPSENSE2_TOG
__IO uint32_t TEMPSENSE2_TOG
Definition: MIMXRT1021.h:32748
ENET_Type::RMON_T_MC_PKT
__I uint32_t RMON_T_MC_PKT
Definition: MIMXRT1021.h:14378
ENET_Type::RMON_R_P512TO1023
__I uint32_t RMON_R_P512TO1023
Definition: MIMXRT1021.h:14419
DCDC_Type::REG3
__IO uint32_t REG3
Definition: MIMXRT1021.h:8642
OCOTP_Type::SCS
__IO uint32_t SCS
Definition: MIMXRT1021.h:24823
XBARA_Type::SEL20
__IO uint16_t SEL20
Definition: MIMXRT1021.h:39260
XBARA_Type::SEL10
__IO uint16_t SEL10
Definition: MIMXRT1021.h:39250
ENET_Type::RDAR
__IO uint32_t RDAR
Definition: MIMXRT1021.h:14330
TMR_Type::CMPLD1
__IO uint16_t CMPLD1
Definition: MIMXRT1021.h:32993
SNVS_Type::LPGPR0_LEGACY_ALIAS
__IO uint32_t LPGPR0_LEGACY_ALIAS
Definition: MIMXRT1021.h:30935
CAN_Type::IMASK1
__IO uint32_t IMASK1
Definition: MIMXRT1021.h:3112
USB_Type::ENDPTPRIME
__IO uint32_t ENDPTPRIME
Definition: MIMXRT1021.h:34192
ENET_Type::RMON_R_RESVD_0
uint32_t RMON_R_RESVD_0
Definition: MIMXRT1021.h:14414
XBARA_Type::SEL64
__IO uint16_t SEL64
Definition: MIMXRT1021.h:39304
DCP_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1021.h:8966
ENET_Type::RMON_R_P128TO255
__I uint32_t RMON_R_P128TO255
Definition: MIMXRT1021.h:14417
USB_ANALOG_Type::CHRG_DETECT_CLR
__IO uint32_t CHRG_DETECT_CLR
Definition: MIMXRT1021.h:36945
FLEXSPI_Type::IPRXFCR
__IO uint32_t IPRXFCR
Definition: MIMXRT1021.h:16828
DMA_Type::DCHPRI15
__IO uint8_t DCHPRI15
Definition: MIMXRT1021.h:10677
SNVS_Type::LPSRTCLR
__IO uint32_t LPSRTCLR
Definition: MIMXRT1021.h:30930
PWM_Type::CVAL2CYC
__I uint16_t CVAL2CYC
Definition: MIMXRT1021.h:27915
I2S_Type::RMR
__IO uint32_t RMR
Definition: MIMXRT1021.h:18620
CCM_ANALOG_Type::PFD_480_TOG
__IO uint32_t PFD_480_TOG
Definition: MIMXRT1021.h:5798
PWM_Type::FSTS
__IO uint16_t FSTS
Definition: MIMXRT1021.h:27932
USB_Type::GPTIMER1LD
__IO uint32_t GPTIMER1LD
Definition: MIMXRT1021.h:34153
XBARA_Type::SEL8
__IO uint16_t SEL8
Definition: MIMXRT1021.h:39248
XBARA_Type::SEL41
__IO uint16_t SEL41
Definition: MIMXRT1021.h:39281
DCDC_Type::REG1
__IO uint32_t REG1
Definition: MIMXRT1021.h:8640
OCOTP_Type::SRK7
__IO uint32_t SRK7
Definition: MIMXRT1021.h:24878
PGC_Type::MEGA_CTRL
__IO uint32_t MEGA_CTRL
Definition: MIMXRT1021.h:25684
CCM_ANALOG_Type::PFD_480_CLR
__IO uint32_t PFD_480_CLR
Definition: MIMXRT1021.h:5797
ENC_Type::UPOS
__IO uint16_t UPOS
Definition: MIMXRT1021.h:13825
DCP_Type::CH0STAT
__IO uint32_t CH0STAT
Definition: MIMXRT1021.h:9004
SRC_Type::SRSR
__IO uint32_t SRSR
Definition: MIMXRT1021.h:32499
LPI2C_Type::MTDR
__O uint32_t MTDR
Definition: MIMXRT1021.h:22227
PGC_Type::CPU_SR
__IO uint32_t CPU_SR
Definition: MIMXRT1021.h:25692
DMA_Type::CEEI
__O uint8_t CEEI
Definition: MIMXRT1021.h:10648
SPDIF_Type::SRCD
__IO uint32_t SRCD
Definition: MIMXRT1021.h:32010
USBPHY_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1021.h:35854
ENET_Type::RDSR
__IO uint32_t RDSR
Definition: MIMXRT1021.h:14358
USB_ANALOG_Type::LOOPBACK_CLR
__IO uint32_t LOOPBACK_CLR
Definition: MIMXRT1021.h:36953
USBNC_Type::USB_OTGn_CTRL
__IO uint32_t USB_OTGn_CTRL
Definition: MIMXRT1021.h:35695
DMA_Type::ES
__I uint32_t ES
Definition: MIMXRT1021.h:10643
TRNG_Type::PKRMAX
__IO uint32_t PKRMAX
Definition: MIMXRT1021.h:33476
ENET_Type::IEEE_R_MACERR
__I uint32_t IEEE_R_MACERR
Definition: MIMXRT1021.h:14427
PWM_Type::CVAL4CYC
__I uint16_t CVAL4CYC
Definition: MIMXRT1021.h:27919
XBARA_Type::SEL49
__IO uint16_t SEL49
Definition: MIMXRT1021.h:39289
FLEXIO_Type::TIMSTAT
__IO uint32_t TIMSTAT
Definition: MIMXRT1021.h:16094
PMU_Type::REG_CORE_TOG
__IO uint32_t REG_CORE_TOG
Definition: MIMXRT1021.h:25994
DMA_Type::DCHPRI6
__IO uint8_t DCHPRI6
Definition: MIMXRT1021.h:10670
SEMC_Type::NANDCR1
__IO uint32_t NANDCR1
Definition: MIMXRT1021.h:29732
FLEXIO_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1021.h:16088
USDHC_Type::INT_SIGNAL_EN
__IO uint32_t INT_SIGNAL_EN
Definition: MIMXRT1021.h:37407
ADC_Type::GS
__IO uint32_t GS
Definition: MIMXRT1021.h:1084
DMA_Type::DCHPRI1
__IO uint8_t DCHPRI1
Definition: MIMXRT1021.h:10667
AOI_Type::BFCRT23
__IO uint16_t BFCRT23
Definition: MIMXRT1021.h:2597
XBARB_Type::SEL4
__IO uint16_t SEL4
Definition: MIMXRT1021.h:40143
FLEXSPI_Type::INTEN
__IO uint32_t INTEN
Definition: MIMXRT1021.h:16811
OCOTP_Type::MEM4
__IO uint32_t MEM4
Definition: MIMXRT1021.h:24856
USB_Type::ENDPTNAKEN
__IO uint32_t ENDPTNAKEN
Definition: MIMXRT1021.h:34185
ENET_Type::ATCR
__IO uint32_t ATCR
Definition: MIMXRT1021.h:14431
CCM_ANALOG_Type::MISC2_CLR
__IO uint32_t MISC2_CLR
Definition: MIMXRT1021.h:5814
PWM_Type::VAL3
__IO uint16_t VAL3
Definition: MIMXRT1021.h:27890
ENET_Type::RMON_R_MC_PKT
__I uint32_t RMON_R_MC_PKT
Definition: MIMXRT1021.h:14408
PWM_Type::TCTRL
__IO uint16_t TCTRL
Definition: MIMXRT1021.h:27900
DCP_Type::CHANNELCTRL_SET
__IO uint32_t CHANNELCTRL_SET
Definition: MIMXRT1021.h:8973
USB_Type::USBINTR
__IO uint32_t USBINTR
Definition: MIMXRT1021.h:34169
I2S_Type::RCR2
__IO uint32_t RCR2
Definition: MIMXRT1021.h:18612
TRNG_Type::TOTSAM
__I uint32_t TOTSAM
Definition: MIMXRT1021.h:33482
XBARA_Type::SEL21
__IO uint16_t SEL21
Definition: MIMXRT1021.h:39261
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ
__IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ
Definition: MIMXRT1021.h:21460
USB_Type::GPTIMER0LD
__IO uint32_t GPTIMER0LD
Definition: MIMXRT1021.h:34151
ENET_Type::MSCR
__IO uint32_t MSCR
Definition: MIMXRT1021.h:14336
I2S_Type::TCSR
__IO uint32_t TCSR
Definition: MIMXRT1021.h:18598
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ
__IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ
Definition: MIMXRT1021.h:21466
ENC_Type::UINIT
__IO uint16_t UINIT
Definition: MIMXRT1021.h:13829
PIT_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1021.h:25820
DCP_Type::CH1CMDPTR
__IO uint32_t CH1CMDPTR
Definition: MIMXRT1021.h:9012
CCM_Type::CCR
__IO uint32_t CCR
Definition: MIMXRT1021.h:3944
WDOG_Type::WRSR
__I uint16_t WRSR
Definition: MIMXRT1021.h:39044
ENET_Type::RMON_T_CRC_ALIGN
__I uint32_t RMON_T_CRC_ALIGN
Definition: MIMXRT1021.h:14379
TRNG_Type::STATUS
__I uint32_t STATUS
Definition: MIMXRT1021.h:33517
DMA_Type::DOFF
__IO uint16_t DOFF
Definition: MIMXRT1021.h:10709
DCP_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1021.h:8967
PWM_Type::CVAL4
__I uint16_t CVAL4
Definition: MIMXRT1021.h:27918
PWM_Type::DTSRCSEL
__IO uint16_t DTSRCSEL
Definition: MIMXRT1021.h:27928
USDHC_Type::CMD_RSP3
__I uint32_t CMD_RSP3
Definition: MIMXRT1021.h:37400
OCOTP_Type::LOCK
__IO uint32_t LOCK
Definition: MIMXRT1021.h:24832
USB_ANALOG_Type::LOOPBACK_TOG
__IO uint32_t LOOPBACK_TOG
Definition: MIMXRT1021.h:36954
SEMC_Type::SDRAMCR3
__IO uint32_t SDRAMCR3
Definition: MIMXRT1021.h:29730
DMA_Type::DCHPRI13
__IO uint8_t DCHPRI13
Definition: MIMXRT1021.h:10679
ENET_Type::TAFL
__IO uint32_t TAFL
Definition: MIMXRT1021.h:14368
USB_ANALOG_Type::VBUS_DETECT_CLR
__IO uint32_t VBUS_DETECT_CLR
Definition: MIMXRT1021.h:36941
SNVS_Type::LPSVCR
__IO uint32_t LPSVCR
Definition: MIMXRT1021.h:30925
XTALOSC24M_Type::LOWPWR_CTRL_SET
__IO uint32_t LOWPWR_CTRL_SET
Definition: MIMXRT1021.h:40277
SNVS_Type::HPVIDR2
__I uint32_t HPVIDR2
Definition: MIMXRT1021.h:30943
DCP_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1021.h:9055
USDHC_Type::VEND_SPEC2
__IO uint32_t VEND_SPEC2
Definition: MIMXRT1021.h:37423
SRC_Type::SBMR2
__I uint32_t SBMR2
Definition: MIMXRT1021.h:32501
XBARA_Type::SEL30
__IO uint16_t SEL30
Definition: MIMXRT1021.h:39270
USDHC_Type::DLL_CTRL
__IO uint32_t DLL_CTRL
Definition: MIMXRT1021.h:37417
USBPHY_Type::PWD_TOG
__IO uint32_t PWD_TOG
Definition: MIMXRT1021.h:35829
SNVS_Type::HPHACIVR
__IO uint32_t HPHACIVR
Definition: MIMXRT1021.h:30916
SEMC_Type::SDRAMCR2
__IO uint32_t SDRAMCR2
Definition: MIMXRT1021.h:29729
LPSPI_Type::DMR1
__IO uint32_t DMR1
Definition: MIMXRT1021.h:23268
ENET_Type::EIMR
__IO uint32_t EIMR
Definition: MIMXRT1021.h:14328
DCP_Type::PACKET4
__I uint32_t PACKET4
Definition: MIMXRT1021.h:8994
PWM_Type::VAL4
__IO uint16_t VAL4
Definition: MIMXRT1021.h:27892
LPI2C_Type::SASR
__I uint32_t SASR
Definition: MIMXRT1021.h:22241
XBARA_Type::SEL3
__IO uint16_t SEL3
Definition: MIMXRT1021.h:39243
USB_ANALOG_Type::VBUS_DETECT_STAT
__I uint32_t VBUS_DETECT_STAT
Definition: MIMXRT1021.h:36947
SNVS_Type::HPRTCMR
__IO uint32_t HPRTCMR
Definition: MIMXRT1021.h:30918
FLEXSPI_Type::FLSHCR4
__IO uint32_t FLSHCR4
Definition: MIMXRT1021.h:16821
TRNG_Type::PKRCNT98
__I uint32_t PKRCNT98
Definition: MIMXRT1021.h:33523
ENET_Type::TFWR
__IO uint32_t TFWR
Definition: MIMXRT1021.h:14356
TRNG_Type::PKRCNT10
__I uint32_t PKRCNT10
Definition: MIMXRT1021.h:33519
ENET_Type::IEEE_R_FRAME_OK
__I uint32_t IEEE_R_FRAME_OK
Definition: MIMXRT1021.h:14424
OCOTP_Type::SRK2
__IO uint32_t SRK2
Definition: MIMXRT1021.h:24868
ENET_Type::IALR
__IO uint32_t IALR
Definition: MIMXRT1021.h:14352
CCM_Type::CSCDR1
__IO uint32_t CSCDR1
Definition: MIMXRT1021.h:3953
TRNG_Type::SCR6PC
__I uint32_t SCR6PC
Definition: MIMXRT1021.h:33514
USBPHY_Type::DEBUG1_SET
__IO uint32_t DEBUG1_SET
Definition: MIMXRT1021.h:35851
CCM_ANALOG_Type::PLL_AUDIO_DENOM
__IO uint32_t PLL_AUDIO_DENOM
Definition: MIMXRT1021.h:5789
IOMUXC_GPR_Type::GPR7
__IO uint32_t GPR7
Definition: MIMXRT1021.h:19592
DCP_Type::CH2STAT
__IO uint32_t CH2STAT
Definition: MIMXRT1021.h:9028
LPSPI_Type::RSR
__I uint32_t RSR
Definition: MIMXRT1021.h:23277
AIPSTZ_Type::OPACR4
__IO uint32_t OPACR4
Definition: MIMXRT1021.h:1889
PWM_Type::CVAL5CYC
__I uint16_t CVAL5CYC
Definition: MIMXRT1021.h:27921
XBARA_Type::SEL61
__IO uint16_t SEL61
Definition: MIMXRT1021.h:39301
SPDIF_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1021.h:32009
SEMC_Type::NANDCR3
__IO uint32_t NANDCR3
Definition: MIMXRT1021.h:29734
PWM_Type::FCTRL
__IO uint16_t FCTRL
Definition: MIMXRT1021.h:27931
XTALOSC24M_Type::OSC_CONFIG0_CLR
__IO uint32_t OSC_CONFIG0_CLR
Definition: MIMXRT1021.h:40283
DCP_Type::CH0STAT_SET
__IO uint32_t CH0STAT_SET
Definition: MIMXRT1021.h:9005
XBARA_Type::SEL45
__IO uint16_t SEL45
Definition: MIMXRT1021.h:39285
USB_Type::HWDEVICE
__I uint32_t HWDEVICE
Definition: MIMXRT1021.h:34147
FLEXSPI_Type::STS0
__I uint32_t STS0
Definition: MIMXRT1021.h:16832
CCM_ANALOG_Type::PLL_ENET
__IO uint32_t PLL_ENET
Definition: MIMXRT1021.h:5791
USB_Type::BURSTSIZE
__IO uint32_t BURSTSIZE
Definition: MIMXRT1021.h:34181
PWM_Type::CAPTCOMPB
__IO uint16_t CAPTCOMPB
Definition: MIMXRT1021.h:27907
USB_Type::ENDPTFLUSH
__IO uint32_t ENDPTFLUSH
Definition: MIMXRT1021.h:34193
XTALOSC24M_Type::OSC_CONFIG0
__IO uint32_t OSC_CONFIG0
Definition: MIMXRT1021.h:40281
SEMC_Type::STS11
uint32_t STS11
Definition: MIMXRT1021.h:29765
XBARA_Type::SEL43
__IO uint16_t SEL43
Definition: MIMXRT1021.h:39283
CCM_ANALOG_Type::PLL_ENET_CLR
__IO uint32_t PLL_ENET_CLR
Definition: MIMXRT1021.h:5793
DMA_Type::DCHPRI11
__IO uint8_t DCHPRI11
Definition: MIMXRT1021.h:10673
USB_Type::HWHOST
__I uint32_t HWHOST
Definition: MIMXRT1021.h:34146
XBARA_Type::SEL24
__IO uint16_t SEL24
Definition: MIMXRT1021.h:39264
CCM_ANALOG_Type::PLL_USB1_TOG
__IO uint32_t PLL_USB1_TOG
Definition: MIMXRT1021.h:5771
TRNG_Type::INT_CTRL
__IO uint32_t INT_CTRL
Definition: MIMXRT1021.h:33528
USB_Type::ASYNCLISTADDR
__IO uint32_t ASYNCLISTADDR
Definition: MIMXRT1021.h:34177
OCOTP_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1021.h:24828
DCP_Type::CH3STAT_SET
__IO uint32_t CH3STAT_SET
Definition: MIMXRT1021.h:9041
TMR_Type::CMPLD2
__IO uint16_t CMPLD2
Definition: MIMXRT1021.h:32994
GPC_Type::ISR5
__I uint32_t ISR5
Definition: MIMXRT1021.h:17735
DCP_Type::STAT_TOG
__IO uint32_t STAT_TOG
Definition: MIMXRT1021.h:8971
OCOTP_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1021.h:24809
OCOTP_Type::SW_STICKY
__IO uint32_t SW_STICKY
Definition: MIMXRT1021.h:24821
ENET_Type::FTRL
__IO uint32_t FTRL
Definition: MIMXRT1021.h:14370
ENET_Type::IEEE_T_MCOL
__I uint32_t IEEE_T_MCOL
Definition: MIMXRT1021.h:14396
OCOTP_Type::ANA2
__IO uint32_t ANA2
Definition: MIMXRT1021.h:24862
DCP_Type::PACKET2
__I uint32_t PACKET2
Definition: MIMXRT1021.h:8990
USB_Type::DCIVERSION
__I uint16_t DCIVERSION
Definition: MIMXRT1021.h:34163
DMA_Type::EEI
__IO uint32_t EEI
Definition: MIMXRT1021.h:10647
XBARA_Type::SEL58
__IO uint16_t SEL58
Definition: MIMXRT1021.h:39298
USBPHY_Type::TX_SET
__IO uint32_t TX_SET
Definition: MIMXRT1021.h:35831
USB_Type::HWGENERAL
__I uint32_t HWGENERAL
Definition: MIMXRT1021.h:34145
SPDIF_Type::SRU
__I uint32_t SRU
Definition: MIMXRT1021.h:32021
ENC_Type::POSD
__IO uint16_t POSD
Definition: MIMXRT1021.h:13821
FLEXSPI_Type::MCR2
__IO uint32_t MCR2
Definition: MIMXRT1021.h:16809
TRNG_Type::PKRCNT54
__I uint32_t PKRCNT54
Definition: MIMXRT1021.h:33521
USDHC_Type::MMC_BOOT
__IO uint32_t MMC_BOOT
Definition: MIMXRT1021.h:37422
XBARA_Type::SEL6
__IO uint16_t SEL6
Definition: MIMXRT1021.h:39246
PMU_Type::MISC2_CLR
__IO uint32_t MISC2_CLR
Definition: MIMXRT1021.h:26005
TRNG_Type::SCR3C
__I uint32_t SCR3C
Definition: MIMXRT1021.h:33502
TRNG_Type::SCR6PL
__IO uint32_t SCR6PL
Definition: MIMXRT1021.h:33515
SPDIF_Type::STL
__O uint32_t STL
Definition: MIMXRT1021.h:32023
ENET_Type::GALR
__IO uint32_t GALR
Definition: MIMXRT1021.h:14354
ENET_Type::RMON_T_P64
__I uint32_t RMON_T_P64
Definition: MIMXRT1021.h:14385
CAN_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1021.h:3102
ENET_Type::ATINC
__IO uint32_t ATINC
Definition: MIMXRT1021.h:14436
USBPHY_Type::RX
__IO uint32_t RX
Definition: MIMXRT1021.h:35834
LPI2C_Type::STDR
__O uint32_t STDR
Definition: MIMXRT1021.h:22244
ENET_Type::RMON_R_UNDERSIZE
__I uint32_t RMON_R_UNDERSIZE
Definition: MIMXRT1021.h:14410
SPDIF_Type::SRL
__I uint32_t SRL
Definition: MIMXRT1021.h:32017
CMP_Type::CR0
__IO uint8_t CR0
Definition: MIMXRT1021.h:7774
TEMPMON_Type::TEMPSENSE2_CLR
__IO uint32_t TEMPSENSE2_CLR
Definition: MIMXRT1021.h:32747
FLEXIO_Type::TIMIEN
__IO uint32_t TIMIEN
Definition: MIMXRT1021.h:16098
IOMUXC_GPR_Type::GPR10
__IO uint32_t GPR10
Definition: MIMXRT1021.h:19595
SEMC_Type::IOCR
__IO uint32_t IOCR
Definition: MIMXRT1021.h:29720
IOMUXC_GPR_Type::GPR1
__IO uint32_t GPR1
Definition: MIMXRT1021.h:19586
DCP_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1021.h:8965
USB_ANALOG_Type::MISC_CLR
__IO uint32_t MISC_CLR
Definition: MIMXRT1021.h:36957
OCOTP_Type::SW_GP20
__IO uint32_t SW_GP20
Definition: MIMXRT1021.h:24896
TRNG_Type::PKRCNTBA
__I uint32_t PKRCNTBA
Definition: MIMXRT1021.h:33524
LPUART_Type::BAUD
__IO uint32_t BAUD
Definition: MIMXRT1021.h:23886
USBPHY_Type::DEBUG1
__IO uint32_t DEBUG1
Definition: MIMXRT1021.h:35850
SEMC_Type::NANDCR2
__IO uint32_t NANDCR2
Definition: MIMXRT1021.h:29733
ADC_ETC_Type::TRIGn_CTRL
__IO uint32_t TRIGn_CTRL
Definition: MIMXRT1021.h:1428
ENET_Type::TXIC
__IO uint32_t TXIC
Definition: MIMXRT1021.h:14347
USDHC_Type::CMD_RSP1
__I uint32_t CMD_RSP1
Definition: MIMXRT1021.h:37398
PWM_Type::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1021.h:27882
PMU_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1021.h:25998
ENET_Type::RMON_R_PACKETS
__I uint32_t RMON_R_PACKETS
Definition: MIMXRT1021.h:14406
OCOTP_Type::SW_GP23
__IO uint32_t SW_GP23
Definition: MIMXRT1021.h:24902
ENET_Type::IEEE_T_LCOL
__I uint32_t IEEE_T_LCOL
Definition: MIMXRT1021.h:14398
TRNG_Type::SCR3L
__IO uint32_t SCR3L
Definition: MIMXRT1021.h:33503
CCM_Type::CS1CDR
__IO uint32_t CS1CDR
Definition: MIMXRT1021.h:3954
DCP_Type::PACKET5
__I uint32_t PACKET5
Definition: MIMXRT1021.h:8996
CCM_ANALOG_Type::PLL_ENET_TOG
__IO uint32_t PLL_ENET_TOG
Definition: MIMXRT1021.h:5794
ENET_Type::RMON_R_P1024TO2047
__I uint32_t RMON_R_P1024TO2047
Definition: MIMXRT1021.h:14420
DMA_Type::DCHPRI22
__IO uint8_t DCHPRI22
Definition: MIMXRT1021.h:10686
ENET_Type::RMON_T_P512TO1023
__I uint32_t RMON_T_P512TO1023
Definition: MIMXRT1021.h:14389
PWM_Type::CAPTCTRLX
__IO uint16_t CAPTCTRLX
Definition: MIMXRT1021.h:27908
TRNG_Type::FRQMIN
__IO uint32_t FRQMIN
Definition: MIMXRT1021.h:33484
ENC_Type::CTRL2
__IO uint16_t CTRL2
Definition: MIMXRT1021.h:13833
ENET_Type::RMON_T_PACKETS
__I uint32_t RMON_T_PACKETS
Definition: MIMXRT1021.h:14376
DMA_Type::DCHPRI31
__IO uint8_t DCHPRI31
Definition: MIMXRT1021.h:10693
I2S_Type::TCR4
__IO uint32_t TCR4
Definition: MIMXRT1021.h:18602
XBARA_Type::SEL11
__IO uint16_t SEL11
Definition: MIMXRT1021.h:39251
SPDIF_Type::SRCSH
__I uint32_t SRCSH
Definition: MIMXRT1021.h:32019
DCP_Type::STAT_SET
__IO uint32_t STAT_SET
Definition: MIMXRT1021.h:8969
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B
__IO uint32_t SW_PAD_CTL_PAD_POR_B
Definition: MIMXRT1021.h:21462
ENC_Type::LPOS
__IO uint16_t LPOS
Definition: MIMXRT1021.h:13826
DMA_Type::DCHPRI9
__IO uint8_t DCHPRI9
Definition: MIMXRT1021.h:10675
PWM_Type::CVAL0
__I uint16_t CVAL0
Definition: MIMXRT1021.h:27910
CCM_ANALOG_Type::PLL_SYS_SS
__IO uint32_t PLL_SYS_SS
Definition: MIMXRT1021.h:5777
DMA_Type::DCHPRI16
__IO uint8_t DCHPRI16
Definition: MIMXRT1021.h:10684
IOMUXC_GPR_Type::GPR23
__IO uint32_t GPR23
Definition: MIMXRT1021.h:19608
GPC_Type::CNTR
__IO uint32_t CNTR
Definition: MIMXRT1021.h:17729
USB_Type::GPTIMER0CTRL
__IO uint32_t GPTIMER0CTRL
Definition: MIMXRT1021.h:34152
CCM_ANALOG_Type::PFD_528
__IO uint32_t PFD_528
Definition: MIMXRT1021.h:5799
CCM_ANALOG_Type::PLL_SYS_CLR
__IO uint32_t PLL_SYS_CLR
Definition: MIMXRT1021.h:5775
TMR_Type::LOAD
__IO uint16_t LOAD
Definition: MIMXRT1021.h:32988
SEMC_Type::IPTXDAT
__IO uint32_t IPTXDAT
Definition: MIMXRT1021.h:29750
USB_ANALOG_Type::CHRG_DETECT_SET
__IO uint32_t CHRG_DETECT_SET
Definition: MIMXRT1021.h:36944
CSU_Type::HP0
__IO uint32_t HP0
Definition: MIMXRT1021.h:8026
PWM_Type::FRACVAL1
__IO uint16_t FRACVAL1
Definition: MIMXRT1021.h:27885
USB_Type::PERIODICLISTBASE
__IO uint32_t PERIODICLISTBASE
Definition: MIMXRT1021.h:34174
SNVS_Type::LPMKCR
__IO uint32_t LPMKCR
Definition: MIMXRT1021.h:30924
SPDIF_Type::STC
__IO uint32_t STC
Definition: MIMXRT1021.h:32030
DCP_Type::CH1OPTS_CLR
__IO uint32_t CH1OPTS_CLR
Definition: MIMXRT1021.h:9022
SEMC_Type::IPCR2
__IO uint32_t IPCR2
Definition: MIMXRT1021.h:29748
OCOTP_Type::MISC_CONF0
__IO uint32_t MISC_CONF0
Definition: MIMXRT1021.h:24904
PMU_Type::MISC2_SET
__IO uint32_t MISC2_SET
Definition: MIMXRT1021.h:26004
PWM_Type::FRACVAL2
__IO uint16_t FRACVAL2
Definition: MIMXRT1021.h:27887
XBARA_Type::SEL22
__IO uint16_t SEL22
Definition: MIMXRT1021.h:39262
DMA_Type::DCHPRI3
__IO uint8_t DCHPRI3
Definition: MIMXRT1021.h:10665
USBNC_Type::USB_OTGn_PHY_CTRL_0
__IO uint32_t USB_OTGn_PHY_CTRL_0
Definition: MIMXRT1021.h:35697
AIPSTZ_Type::OPACR3
__IO uint32_t OPACR3
Definition: MIMXRT1021.h:1888
TEMPMON_Type::TEMPSENSE2_SET
__IO uint32_t TEMPSENSE2_SET
Definition: MIMXRT1021.h:32746
WDOG_Type::WSR
__IO uint16_t WSR
Definition: MIMXRT1021.h:39043
BEE_Type::AES_KEY0_W2
__O uint32_t AES_KEY0_W2
Definition: MIMXRT1021.h:2805
CAN_Type::RXFGMASK
__IO uint32_t RXFGMASK
Definition: MIMXRT1021.h:3119
CCM_Type::CGPR
__IO uint32_t CGPR
Definition: MIMXRT1021.h:3967
USDHC_Type::ADMA_SYS_ADDR
__IO uint32_t ADMA_SYS_ADDR
Definition: MIMXRT1021.h:37415
ENET_Type::RMON_R_P256TO511
__I uint32_t RMON_R_P256TO511
Definition: MIMXRT1021.h:14418
ENC_Type::LINIT
__IO uint16_t LINIT
Definition: MIMXRT1021.h:13830
USB_Type::USBMODE
__IO uint32_t USBMODE
Definition: MIMXRT1021.h:34190
CCM_ANALOG_Type::PFD_528_TOG
__IO uint32_t PFD_528_TOG
Definition: MIMXRT1021.h:5802
DMA_Type::DCHPRI4
__IO uint8_t DCHPRI4
Definition: MIMXRT1021.h:10672
LPSPI_Type::TCR
__IO uint32_t TCR
Definition: MIMXRT1021.h:23274
LPI2C_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1021.h:22231
ADC_ETC_Type::TRIGn_RESULT_1_0
__I uint32_t TRIGn_RESULT_1_0
Definition: MIMXRT1021.h:1434
CCM_ANALOG_Type::MISC2
__IO uint32_t MISC2
Definition: MIMXRT1021.h:5812
DMA_Type::DADDR
__IO uint32_t DADDR
Definition: MIMXRT1021.h:10708
DCP_Type::PACKET3
__I uint32_t PACKET3
Definition: MIMXRT1021.h:8992
DCP_Type::CH2OPTS_CLR
__IO uint32_t CH2OPTS_CLR
Definition: MIMXRT1021.h:9034
XTALOSC24M_Type::OSC_CONFIG1_CLR
__IO uint32_t OSC_CONFIG1_CLR
Definition: MIMXRT1021.h:40287
PIT_Type::LTMR64H
__I uint32_t LTMR64H
Definition: MIMXRT1021.h:25822
SEMC_Type::BMCR0
__IO uint32_t BMCR0
Definition: MIMXRT1021.h:29721
ENC_Type::LCOMP
__IO uint16_t LCOMP
Definition: MIMXRT1021.h:13837
FLEXIO_Type::SHIFTEIEN
__IO uint32_t SHIFTEIEN
Definition: MIMXRT1021.h:16097
ENET_Type::RMON_T_OCTETS
__I uint32_t RMON_T_OCTETS
Definition: MIMXRT1021.h:14392
DCP_Type::CH1OPTS_TOG
__IO uint32_t CH1OPTS_TOG
Definition: MIMXRT1021.h:9023
CCM_Type::CSCDR3
uint32_t CSCDR3
Definition: MIMXRT1021.h:3959
PMU_Type::REG_1P1_CLR
__IO uint32_t REG_1P1_CLR
Definition: MIMXRT1021.h:25981
CCM_Type::CCGR4
__IO uint32_t CCGR4
Definition: MIMXRT1021.h:3972
CAN_Type::CS
__IO uint32_t CS
Definition: MIMXRT1021.h:3126
PWM_Type::FRCTRL
__IO uint16_t FRCTRL
Definition: MIMXRT1021.h:27895
DCP_Type::CH0OPTS_SET
__IO uint32_t CH0OPTS_SET
Definition: MIMXRT1021.h:9009
USDHC_Type::INT_STATUS_EN
__IO uint32_t INT_STATUS_EN
Definition: MIMXRT1021.h:37406
XBARA_Type::SEL14
__IO uint16_t SEL14
Definition: MIMXRT1021.h:39254
CCM_Type::CLPCR
__IO uint32_t CLPCR
Definition: MIMXRT1021.h:3963
PWM_Type::CAPTCTRLA
__IO uint16_t CAPTCTRLA
Definition: MIMXRT1021.h:27904
USDHC_Type::PROT_CTRL
__IO uint32_t PROT_CTRL
Definition: MIMXRT1021.h:37403
SNVS_Type::LPPGDR
__IO uint32_t LPPGDR
Definition: MIMXRT1021.h:30934
LPUART_Type::STAT
__IO uint32_t STAT
Definition: MIMXRT1021.h:23887
USBPHY_Type::DEBUG0_STATUS
__I uint32_t DEBUG0_STATUS
Definition: MIMXRT1021.h:35848
PWM_Type::PHASEDLY
__IO uint16_t PHASEDLY
Definition: MIMXRT1021.h:27922
USB_ANALOG_Type::MISC_SET
__IO uint32_t MISC_SET
Definition: MIMXRT1021.h:36956
XBARA_Type::SEL51
__IO uint16_t SEL51
Definition: MIMXRT1021.h:39291
PMU_Type::REG_3P0_SET
__IO uint32_t REG_3P0_SET
Definition: MIMXRT1021.h:25984
DCP_Type::CH3CMDPTR
__IO uint32_t CH3CMDPTR
Definition: MIMXRT1021.h:9036
XBARA_Type::SEL23
__IO uint16_t SEL23
Definition: MIMXRT1021.h:39263
TMR_Type::CAPT
__IO uint16_t CAPT
Definition: MIMXRT1021.h:32987
IOMUXC_GPR_Type::GPR25
__IO uint32_t GPR25
Definition: MIMXRT1021.h:19610
DCP_Type::CH3STAT
__IO uint32_t CH3STAT
Definition: MIMXRT1021.h:9040
SEMC_Type::STS2
__I uint32_t STS2
Definition: MIMXRT1021.h:29756
GPIO_Type::DR_TOGGLE
__O uint32_t DR_TOGGLE
Definition: MIMXRT1021.h:17869
LPI2C_Type::MDMR
__IO uint32_t MDMR
Definition: MIMXRT1021.h:22219
DMA_Type::BITER_ELINKNO
__IO uint16_t BITER_ELINKNO
Definition: MIMXRT1021.h:10717
SNVS_Type::LPTDCR
__IO uint32_t LPTDCR
Definition: MIMXRT1021.h:30927
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE
__IO uint32_t SW_PAD_CTL_PAD_TEST_MODE
Definition: MIMXRT1021.h:21461
BEE_Type::CTR_NONCE0_W2
__O uint32_t CTR_NONCE0_W2
Definition: MIMXRT1021.h:2810
USB_ANALOG_Type::VBUS_DETECT_TOG
__IO uint32_t VBUS_DETECT_TOG
Definition: MIMXRT1021.h:36942
CCM_Type::CCGR0
__IO uint32_t CCGR0
Definition: MIMXRT1021.h:3968
FLEXRAM_Type::INT_STAT_EN
__IO uint32_t INT_STAT_EN
Definition: MIMXRT1021.h:16662
CCM_Type::CCGR1
__IO uint32_t CCGR1
Definition: MIMXRT1021.h:3969
ENET_Type::IEEE_T_SQE
__I uint32_t IEEE_T_SQE
Definition: MIMXRT1021.h:14402
CM7_MCM_Type::ISCR
__IO uint32_t ISCR
Definition: MIMXRT1021.h:7621
IOMUXC_SNVS_GPR_Type::GPR0
uint32_t GPR0
Definition: MIMXRT1021.h:21966
DCP_Type::CHANNELCTRL
__IO uint32_t CHANNELCTRL
Definition: MIMXRT1021.h:8972
LPI2C_Type::MCFGR2
__IO uint32_t MCFGR2
Definition: MIMXRT1021.h:22216
CCM_Type::CSCMR2
__IO uint32_t CSCMR2
Definition: MIMXRT1021.h:3952
USB_Type::ENDPTCTRL0
__IO uint32_t ENDPTCTRL0
Definition: MIMXRT1021.h:34196
FLEXSPI_Type::STS1
__I uint32_t STS1
Definition: MIMXRT1021.h:16833
LPI2C_Type::MFCR
__IO uint32_t MFCR
Definition: MIMXRT1021.h:22225
ENET_Type::TIPG
__IO uint32_t TIPG
Definition: MIMXRT1021.h:14369
SEMC_Type::NORCR1
__IO uint32_t NORCR1
Definition: MIMXRT1021.h:29736
XBARB_Type::SEL0
__IO uint16_t SEL0
Definition: MIMXRT1021.h:40139
DCP_Type::STAT
__IO uint32_t STAT
Definition: MIMXRT1021.h:8968
DCP_Type::STAT_CLR
__IO uint32_t STAT_CLR
Definition: MIMXRT1021.h:8970
FLEXSPI_Type::MCR0
__IO uint32_t MCR0
Definition: MIMXRT1021.h:16807
OCOTP_Type::TIMING
__IO uint32_t TIMING
Definition: MIMXRT1021.h:24813
ADC_ETC_Type::TRIGn_COUNTER
__IO uint32_t TRIGn_COUNTER
Definition: MIMXRT1021.h:1429
BEE_Type::REGION1_BOT
__IO uint32_t REGION1_BOT
Definition: MIMXRT1021.h:2817
PIT_Type::TFLG
__IO uint32_t TFLG
Definition: MIMXRT1021.h:25829
USBPHY_Type::RX_CLR
__IO uint32_t RX_CLR
Definition: MIMXRT1021.h:35836
FLEXIO_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1021.h:16090
DMA_Type::DCHPRI29
__IO uint8_t DCHPRI29
Definition: MIMXRT1021.h:10695
PWM_Type::CAPTCOMPA
__IO uint16_t CAPTCOMPA
Definition: MIMXRT1021.h:27905
LPUART_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1021.h:23882
ENC_Type::UPOSH
__I uint16_t UPOSH
Definition: MIMXRT1021.h:13827
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP
__IO uint32_t SW_MUX_CTL_PAD_WAKEUP
Definition: MIMXRT1021.h:21458
I2S_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1021.h:18596
OCOTP_Type::SCS_TOG
__IO uint32_t SCS_TOG
Definition: MIMXRT1021.h:24826
XBARA_Type::SEL47
__IO uint16_t SEL47
Definition: MIMXRT1021.h:39287
XBARA_Type::SEL27
__IO uint16_t SEL27
Definition: MIMXRT1021.h:39267
SNVS_Type::HPHACR
__I uint32_t HPHACR
Definition: MIMXRT1021.h:30917
PIT_Type::CVAL
__I uint32_t CVAL
Definition: MIMXRT1021.h:25827
OCOTP_Type::CFG2
__IO uint32_t CFG2
Definition: MIMXRT1021.h:24838
USB_ANALOG_Type::DIGPROG
__I uint32_t DIGPROG
Definition: MIMXRT1021.h:36961
XBARA_Type::SEL39
__IO uint16_t SEL39
Definition: MIMXRT1021.h:39279
FLEXSPI_Type::IPCMD
__IO uint32_t IPCMD
Definition: MIMXRT1021.h:16826
ADC_Type::CFG
__IO uint32_t CFG
Definition: MIMXRT1021.h:1082
CAN_Type::TIMER
__IO uint32_t TIMER
Definition: MIMXRT1021.h:3104
CCM_ANALOG_Type::PFD_480
__IO uint32_t PFD_480
Definition: MIMXRT1021.h:5795
ENC_Type::UCOMP
__IO uint16_t UCOMP
Definition: MIMXRT1021.h:13836
CAN_Type::GFWR
__IO uint32_t GFWR
Definition: MIMXRT1021.h:3134
PWM_Type::INTEN
__IO uint16_t INTEN
Definition: MIMXRT1021.h:27898
DMA_Type::INT
__IO uint32_t INT
Definition: MIMXRT1021.h:10657
USBPHY_Type::STATUS
__IO uint32_t STATUS
Definition: MIMXRT1021.h:35842
LPI2C_Type::MSR
__IO uint32_t MSR
Definition: MIMXRT1021.h:22211
DMA_Type::ERR
__IO uint32_t ERR
Definition: MIMXRT1021.h:10659
_iomuxc_sw_mux_ctl_pad
_iomuxc_sw_mux_ctl_pad
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Definition: MIMXRT1021.h:395
CAN_Type::IMASK2
__IO uint32_t IMASK2
Definition: MIMXRT1021.h:3111
CCM_ANALOG_Type::MISC1_CLR
__IO uint32_t MISC1_CLR
Definition: MIMXRT1021.h:5810
SEMC_Type::STS7
uint32_t STS7
Definition: MIMXRT1021.h:29761
CCM_ANALOG_Type::PFD_528_SET
__IO uint32_t PFD_528_SET
Definition: MIMXRT1021.h:5800
ADC_ETC_Type::TRIGn_CHAIN_5_4
__IO uint32_t TRIGn_CHAIN_5_4
Definition: MIMXRT1021.h:1432
SEMC_Type::STS9
uint32_t STS9
Definition: MIMXRT1021.h:29763
AIPSTZ_Type::MPR
__IO uint32_t MPR
Definition: MIMXRT1021.h:1883
FLEXSPI_Type::LUTCR
__IO uint32_t LUTCR
Definition: MIMXRT1021.h:16814
XTALOSC24M_Type::LOWPWR_CTRL_CLR
__IO uint32_t LOWPWR_CTRL_CLR
Definition: MIMXRT1021.h:40278
DCP_Type::CH3OPTS_TOG
__IO uint32_t CH3OPTS_TOG
Definition: MIMXRT1021.h:9047
PWM_Type::MASK
__IO uint16_t MASK
Definition: MIMXRT1021.h:27926
TMR_Type::DMA
__IO uint16_t DMA
Definition: MIMXRT1021.h:32997
SRC_Type::SBMR1
__I uint32_t SBMR1
Definition: MIMXRT1021.h:32498
XBARA_Type::SEL55
__IO uint16_t SEL55
Definition: MIMXRT1021.h:39295
TMR_Type::CNTR
__IO uint16_t CNTR
Definition: MIMXRT1021.h:32990
CCM_ANALOG_Type::PLL_USB1
__IO uint32_t PLL_USB1
Definition: MIMXRT1021.h:5768
I2S_Type::RCR5
__IO uint32_t RCR5
Definition: MIMXRT1021.h:18615
kXBARB2_InputAcmp1Out
@ kXBARB2_InputAcmp1Out
Definition: MIMXRT1021.h:824
kXBARA1_InputDmaDone7
@ kXBARA1_InputDmaDone7
Definition: MIMXRT1021.h:801
kXBARA1_InputDmaDone6
@ kXBARA1_InputDmaDone6
Definition: MIMXRT1021.h:800
kXBARA1_InputRESERVED76
@ kXBARA1_InputRESERVED76
Definition: MIMXRT1021.h:806
kXBARB2_InputDmaDone4
@ kXBARB2_InputDmaDone4
Definition: MIMXRT1021.h:872
kXBARA1_InputFlexpwm1Pwm3OutTrig01
@ kXBARA1_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1021.h:772
kXBARB2_InputQtimer1Tmr3
@ kXBARB2_InputQtimer1Tmr3
Definition: MIMXRT1021.h:833
kXBARA1_InputIomuxXbarInout14
@ kXBARA1_InputIomuxXbarInout14
Definition: MIMXRT1021.h:744
kXBARB2_InputAdcEtc0Coco2
@ kXBARB2_InputAdcEtc0Coco2
Definition: MIMXRT1021.h:858
kXBARB2_InputQtimer1Tmr1
@ kXBARB2_InputQtimer1Tmr1
Definition: MIMXRT1021.h:831
kXBARA1_InputAdcEtc0Coco0
@ kXBARA1_InputAdcEtc0Coco0
Definition: MIMXRT1021.h:810
kXBARB2_InputAdcEtc0Coco3
@ kXBARB2_InputAdcEtc0Coco3
Definition: MIMXRT1021.h:859
kXBARB2_InputFlexpwm2Pwm3OutTrig01
@ kXBARB2_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1021.h:844
kXBARB2_InputFlexpwm1Pwm1OutTrig01
@ kXBARB2_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1021.h:838
kXBARA1_InputAdcEtc1Coco2
@ kXBARA1_InputAdcEtc1Coco2
Definition: MIMXRT1021.h:816
kXBARA1_InputIomuxXbarInout05
@ kXBARA1_InputIomuxXbarInout05
Definition: MIMXRT1021.h:735
kXBARA1_InputDmaDone0
@ kXBARA1_InputDmaDone0
Definition: MIMXRT1021.h:794
kXBARB2_InputFlexpwm1Pwm3OutTrig01
@ kXBARB2_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1021.h:840
kXBARA1_InputIomuxXbarInout17
@ kXBARA1_InputIomuxXbarInout17
Definition: MIMXRT1021.h:747
kXBARA1_InputIomuxXbarInout06
@ kXBARA1_InputIomuxXbarInout06
Definition: MIMXRT1021.h:736
kXBARA1_InputQtimer1Tmr0
@ kXBARA1_InputQtimer1Tmr0
Definition: MIMXRT1021.h:762
kXBARA1_InputPitTrigger0
@ kXBARA1_InputPitTrigger0
Definition: MIMXRT1021.h:786
kXBARA1_InputQtimer1Tmr3
@ kXBARA1_InputQtimer1Tmr3
Definition: MIMXRT1021.h:765
kXBARB2_InputQtimer2Tmr3
@ kXBARB2_InputQtimer2Tmr3
Definition: MIMXRT1021.h:837
kXBARB2_InputFlexpwm2Pwm2OutTrig01
@ kXBARB2_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1021.h:843
kXBARA1_InputPitTrigger2
@ kXBARA1_InputPitTrigger2
Definition: MIMXRT1021.h:788
kXBARA1_InputQtimer2Tmr0
@ kXBARA1_InputQtimer2Tmr0
Definition: MIMXRT1021.h:766
kXBARA1_InputAoi1Out0
@ kXBARA1_InputAoi1Out0
Definition: MIMXRT1021.h:802
kXBARA1_InputIomuxXbarInout11
@ kXBARA1_InputIomuxXbarInout11
Definition: MIMXRT1021.h:741
kXBARA1_InputFlexpwm1Pwm2OutTrig01
@ kXBARA1_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1021.h:771
kXBARB2_InputRESERVED11
@ kXBARB2_InputRESERVED11
Definition: MIMXRT1021.h:829
kXBARA1_InputIomuxXbarInout18
@ kXBARA1_InputIomuxXbarInout18
Definition: MIMXRT1021.h:748
kXBARB2_InputAdcEtc0Coco1
@ kXBARB2_InputAdcEtc0Coco1
Definition: MIMXRT1021.h:857
kXBARB2_InputDmaDone3
@ kXBARB2_InputDmaDone3
Definition: MIMXRT1021.h:871
kXBARA1_InputRESERVED50
@ kXBARA1_InputRESERVED50
Definition: MIMXRT1021.h:780
kXBARB2_InputRESERVED33
@ kXBARB2_InputRESERVED33
Definition: MIMXRT1021.h:851
kXBARB2_InputAdcEtc1Coco3
@ kXBARB2_InputAdcEtc1Coco3
Definition: MIMXRT1021.h:863
kXBARA1_InputRESERVED21
@ kXBARA1_InputRESERVED21
Definition: MIMXRT1021.h:751
kXBARB2_InputDmaDone7
@ kXBARB2_InputDmaDone7
Definition: MIMXRT1021.h:875
kXBARB2_InputRESERVED10
@ kXBARB2_InputRESERVED10
Definition: MIMXRT1021.h:828
kXBARA1_InputRESERVED79
@ kXBARA1_InputRESERVED79
Definition: MIMXRT1021.h:809
kXBARB2_InputAcmp2Out
@ kXBARB2_InputAcmp2Out
Definition: MIMXRT1021.h:825
kXBARB2_InputEnc2PosMatch
@ kXBARB2_InputEnc2PosMatch
Definition: MIMXRT1021.h:865
kXBARA1_InputAdcEtc0Coco2
@ kXBARA1_InputAdcEtc0Coco2
Definition: MIMXRT1021.h:812
kXBARB2_InputDmaDone2
@ kXBARB2_InputDmaDone2
Definition: MIMXRT1021.h:870
kXBARB2_InputDmaDone5
@ kXBARB2_InputDmaDone5
Definition: MIMXRT1021.h:873
kXBARA1_InputRESERVED3
@ kXBARA1_InputRESERVED3
Definition: MIMXRT1021.h:733
kXBARA1_InputPitTrigger3
@ kXBARA1_InputPitTrigger3
Definition: MIMXRT1021.h:789
kXBARB2_InputQtimer1Tmr0
@ kXBARB2_InputQtimer1Tmr0
Definition: MIMXRT1021.h:830
kXBARA1_InputRESERVED31
@ kXBARA1_InputRESERVED31
Definition: MIMXRT1021.h:761
kXBARA1_InputLogicLow
@ kXBARA1_InputLogicLow
Definition: MIMXRT1021.h:730
kXBARA1_InputRESERVED78
@ kXBARA1_InputRESERVED78
Definition: MIMXRT1021.h:808
kXBARB2_InputRESERVED2
@ kXBARB2_InputRESERVED2
Definition: MIMXRT1021.h:820
kXBARA1_InputRESERVED52
@ kXBARA1_InputRESERVED52
Definition: MIMXRT1021.h:782
kXBARA1_InputIomuxXbarInout16
@ kXBARA1_InputIomuxXbarInout16
Definition: MIMXRT1021.h:746
kXBARB2_InputRESERVED3
@ kXBARB2_InputRESERVED3
Definition: MIMXRT1021.h:821
kXBARA1_InputAcmp4Out
@ kXBARA1_InputAcmp4Out
Definition: MIMXRT1021.h:759
kXBARA1_InputAdcEtc1Coco3
@ kXBARA1_InputAdcEtc1Coco3
Definition: MIMXRT1021.h:817
kXBARA1_InputIomuxXbarInout07
@ kXBARA1_InputIomuxXbarInout07
Definition: MIMXRT1021.h:737
kXBARB2_InputRESERVED4
@ kXBARB2_InputRESERVED4
Definition: MIMXRT1021.h:822
kXBARB2_InputQtimer2Tmr1
@ kXBARB2_InputQtimer2Tmr1
Definition: MIMXRT1021.h:835
kXBARA1_InputRESERVED48
@ kXBARA1_InputRESERVED48
Definition: MIMXRT1021.h:778
kXBARB2_InputRESERVED31
@ kXBARB2_InputRESERVED31
Definition: MIMXRT1021.h:849
kXBARB2_InputAdcEtc1Coco2
@ kXBARB2_InputAdcEtc1Coco2
Definition: MIMXRT1021.h:862
kXBARA1_InputFlexpwm2Pwm3OutTrig01
@ kXBARA1_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1021.h:776
kXBARA1_InputDmaDone4
@ kXBARA1_InputDmaDone4
Definition: MIMXRT1021.h:798
kXBARB2_InputDmaDone0
@ kXBARB2_InputDmaDone0
Definition: MIMXRT1021.h:868
kXBARA1_InputQtimer1Tmr2
@ kXBARA1_InputQtimer1Tmr2
Definition: MIMXRT1021.h:764
kXBARB2_InputEnc1PosMatch
@ kXBARB2_InputEnc1PosMatch
Definition: MIMXRT1021.h:864
kXBARB2_InputRESERVED5
@ kXBARB2_InputRESERVED5
Definition: MIMXRT1021.h:823
kXBARB2_InputDmaDone6
@ kXBARB2_InputDmaDone6
Definition: MIMXRT1021.h:874
kXBARA1_InputAcmp2Out
@ kXBARA1_InputAcmp2Out
Definition: MIMXRT1021.h:757
kXBARB2_InputRESERVED48
@ kXBARB2_InputRESERVED48
Definition: MIMXRT1021.h:866
kXBARA1_InputRESERVED24
@ kXBARA1_InputRESERVED24
Definition: MIMXRT1021.h:754
kXBARA1_InputRESERVED51
@ kXBARA1_InputRESERVED51
Definition: MIMXRT1021.h:781
kXBARA1_InputAcmp3Out
@ kXBARA1_InputAcmp3Out
Definition: MIMXRT1021.h:758
kXBARB2_InputPitTrigger1
@ kXBARB2_InputPitTrigger1
Definition: MIMXRT1021.h:855
kXBARB2_InputFlexpwm2Pwm1OutTrig01
@ kXBARB2_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1021.h:842
kXBARA1_InputAdcEtc1Coco1
@ kXBARA1_InputAdcEtc1Coco1
Definition: MIMXRT1021.h:815
kXBARA1_InputRESERVED77
@ kXBARA1_InputRESERVED77
Definition: MIMXRT1021.h:807
kXBARA1_InputAoi1Out3
@ kXBARA1_InputAoi1Out3
Definition: MIMXRT1021.h:805
kXBARB2_InputAcmp4Out
@ kXBARB2_InputAcmp4Out
Definition: MIMXRT1021.h:827
kXBARA1_InputAdcEtc0Coco3
@ kXBARA1_InputAdcEtc0Coco3
Definition: MIMXRT1021.h:813
kXBARA1_InputFlexpwm2Pwm4OutTrig01
@ kXBARA1_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1021.h:777
kXBARB2_InputRESERVED32
@ kXBARB2_InputRESERVED32
Definition: MIMXRT1021.h:850
kXBARA1_InputRESERVED54
@ kXBARA1_InputRESERVED54
Definition: MIMXRT1021.h:784
kXBARA1_InputAcmp1Out
@ kXBARA1_InputAcmp1Out
Definition: MIMXRT1021.h:756
kXBARA1_InputIomuxXbarInout10
@ kXBARA1_InputIomuxXbarInout10
Definition: MIMXRT1021.h:740
kXBARA1_InputEnc1PosMatch
@ kXBARA1_InputEnc1PosMatch
Definition: MIMXRT1021.h:790
kXBARA1_InputRESERVED22
@ kXBARA1_InputRESERVED22
Definition: MIMXRT1021.h:752
kXBARA1_InputAdcEtc1Coco0
@ kXBARA1_InputAdcEtc1Coco0
Definition: MIMXRT1021.h:814
kXBARA1_InputQtimer2Tmr2
@ kXBARA1_InputQtimer2Tmr2
Definition: MIMXRT1021.h:768
kXBARB2_InputRESERVED28
@ kXBARB2_InputRESERVED28
Definition: MIMXRT1021.h:846
kXBARB2_InputRESERVED35
@ kXBARB2_InputRESERVED35
Definition: MIMXRT1021.h:853
kXBARA1_InputIomuxXbarInout12
@ kXBARA1_InputIomuxXbarInout12
Definition: MIMXRT1021.h:742
kXBARB2_InputAdcEtc1Coco0
@ kXBARB2_InputAdcEtc1Coco0
Definition: MIMXRT1021.h:860
kXBARB2_InputAdcEtc1Coco1
@ kXBARB2_InputAdcEtc1Coco1
Definition: MIMXRT1021.h:861
kXBARB2_InputRESERVED34
@ kXBARB2_InputRESERVED34
Definition: MIMXRT1021.h:852
kXBARB2_InputAcmp3Out
@ kXBARB2_InputAcmp3Out
Definition: MIMXRT1021.h:826
kXBARA1_InputRESERVED49
@ kXBARA1_InputRESERVED49
Definition: MIMXRT1021.h:779
kXBARA1_InputAdcEtc0Coco1
@ kXBARA1_InputAdcEtc0Coco1
Definition: MIMXRT1021.h:811
kXBARB2_InputFlexpwm2Pwm4OutTrig01
@ kXBARB2_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1021.h:845
kXBARB2_InputRESERVED49
@ kXBARB2_InputRESERVED49
Definition: MIMXRT1021.h:867
kXBARB2_InputPitTrigger0
@ kXBARB2_InputPitTrigger0
Definition: MIMXRT1021.h:854
kXBARA1_InputDmaDone5
@ kXBARA1_InputDmaDone5
Definition: MIMXRT1021.h:799
kXBARB2_InputFlexpwm1Pwm4OutTrig01
@ kXBARB2_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1021.h:841
kXBARB2_InputLogicLow
@ kXBARB2_InputLogicLow
Definition: MIMXRT1021.h:818
kXBARA1_InputFlexpwm2Pwm2OutTrig01
@ kXBARA1_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1021.h:775
kXBARB2_InputFlexpwm1Pwm2OutTrig01
@ kXBARB2_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1021.h:839
kXBARA1_InputAoi1Out1
@ kXBARA1_InputAoi1Out1
Definition: MIMXRT1021.h:803
kXBARA1_InputFlexpwm1Pwm1OutTrig01
@ kXBARA1_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1021.h:770
kXBARA1_InputAoi1Out2
@ kXBARA1_InputAoi1Out2
Definition: MIMXRT1021.h:804
kXBARA1_InputDmaDone3
@ kXBARA1_InputDmaDone3
Definition: MIMXRT1021.h:797
kXBARB2_InputQtimer2Tmr2
@ kXBARB2_InputQtimer2Tmr2
Definition: MIMXRT1021.h:836
kXBARA1_InputIomuxXbarInout08
@ kXBARA1_InputIomuxXbarInout08
Definition: MIMXRT1021.h:738
kXBARA1_InputIomuxXbarInout13
@ kXBARA1_InputIomuxXbarInout13
Definition: MIMXRT1021.h:743
kXBARB2_InputRESERVED30
@ kXBARB2_InputRESERVED30
Definition: MIMXRT1021.h:848
kXBARA1_InputRESERVED30
@ kXBARA1_InputRESERVED30
Definition: MIMXRT1021.h:760
kXBARA1_InputRESERVED20
@ kXBARA1_InputRESERVED20
Definition: MIMXRT1021.h:750
kXBARA1_InputRESERVED23
@ kXBARA1_InputRESERVED23
Definition: MIMXRT1021.h:753
kXBARB2_InputAdcEtc0Coco0
@ kXBARB2_InputAdcEtc0Coco0
Definition: MIMXRT1021.h:856
kXBARA1_InputRESERVED63
@ kXBARA1_InputRESERVED63
Definition: MIMXRT1021.h:793
kXBARA1_InputPitTrigger1
@ kXBARA1_InputPitTrigger1
Definition: MIMXRT1021.h:787
kXBARB2_InputQtimer2Tmr0
@ kXBARB2_InputQtimer2Tmr0
Definition: MIMXRT1021.h:834
kXBARA1_InputRESERVED55
@ kXBARA1_InputRESERVED55
Definition: MIMXRT1021.h:785
kXBARA1_InputFlexpwm2Pwm1OutTrig01
@ kXBARA1_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1021.h:774
kXBARA1_InputLogicHigh
@ kXBARA1_InputLogicHigh
Definition: MIMXRT1021.h:731
kXBARA1_InputQtimer2Tmr3
@ kXBARA1_InputQtimer2Tmr3
Definition: MIMXRT1021.h:769
kXBARA1_InputIomuxXbarInout04
@ kXBARA1_InputIomuxXbarInout04
Definition: MIMXRT1021.h:734
kXBARB2_InputLogicHigh
@ kXBARB2_InputLogicHigh
Definition: MIMXRT1021.h:819
kXBARA1_InputFlexpwm1Pwm4OutTrig01
@ kXBARA1_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1021.h:773
kXBARA1_InputEnc2PosMatch
@ kXBARA1_InputEnc2PosMatch
Definition: MIMXRT1021.h:791
kXBARA1_InputRESERVED62
@ kXBARA1_InputRESERVED62
Definition: MIMXRT1021.h:792
kXBARA1_InputIomuxXbarInout19
@ kXBARA1_InputIomuxXbarInout19
Definition: MIMXRT1021.h:749
kXBARA1_InputRESERVED25
@ kXBARA1_InputRESERVED25
Definition: MIMXRT1021.h:755
kXBARB2_InputRESERVED29
@ kXBARB2_InputRESERVED29
Definition: MIMXRT1021.h:847
kXBARA1_InputQtimer1Tmr1
@ kXBARA1_InputQtimer1Tmr1
Definition: MIMXRT1021.h:763
kXBARA1_InputQtimer2Tmr1
@ kXBARA1_InputQtimer2Tmr1
Definition: MIMXRT1021.h:767
kXBARA1_InputDmaDone2
@ kXBARA1_InputDmaDone2
Definition: MIMXRT1021.h:796
kXBARA1_InputIomuxXbarInout09
@ kXBARA1_InputIomuxXbarInout09
Definition: MIMXRT1021.h:739
kXBARB2_InputQtimer1Tmr2
@ kXBARB2_InputQtimer1Tmr2
Definition: MIMXRT1021.h:832
kXBARA1_InputRESERVED53
@ kXBARA1_InputRESERVED53
Definition: MIMXRT1021.h:783
kXBARA1_InputIomuxXbarInout15
@ kXBARA1_InputIomuxXbarInout15
Definition: MIMXRT1021.h:745
kXBARA1_InputRESERVED2
@ kXBARA1_InputRESERVED2
Definition: MIMXRT1021.h:732
kXBARB2_InputDmaDone1
@ kXBARB2_InputDmaDone1
Definition: MIMXRT1021.h:869
kXBARA1_InputDmaDone1
@ kXBARA1_InputDmaDone1
Definition: MIMXRT1021.h:795
kXBARA1_OutputFlexpwm1ExtForce
@ kXBARA1_OutputFlexpwm1ExtForce
Definition: MIMXRT1021.h:919
kXBARA1_OutputRESERVED55
@ kXBARA1_OutputRESERVED55
Definition: MIMXRT1021.h:935
kXBARA1_OutputLpuart7TrgInput
@ kXBARA1_OutputLpuart7TrgInput
Definition: MIMXRT1021.h:1005
kXBARA1_OutputEnc2Home
@ kXBARA1_OutputEnc2Home
Definition: MIMXRT1021.h:954
kXBARA1_OutputRESERVED131
@ kXBARA1_OutputRESERVED131
Definition: MIMXRT1021.h:1011
kXBARA1_OutputEnc1PhaseAInput
@ kXBARA1_OutputEnc1PhaseAInput
Definition: MIMXRT1021.h:946
kXBARA1_OutputFlexpwm1Exta0
@ kXBARA1_OutputFlexpwm1Exta0
Definition: MIMXRT1021.h:906
kXBARA1_OutputRESERVED82
@ kXBARA1_OutputRESERVED82
Definition: MIMXRT1021.h:962
kXBARA1_OutputIomuxXbarInout13
@ kXBARA1_OutputIomuxXbarInout13
Definition: MIMXRT1021.h:893
kXBARA1_OutputEnc1Index
@ kXBARA1_OutputEnc1Index
Definition: MIMXRT1021.h:948
kXBARA1_OutputEnc2PhaseAInput
@ kXBARA1_OutputEnc2PhaseAInput
Definition: MIMXRT1021.h:951
kXBARA1_OutputRESERVED63
@ kXBARA1_OutputRESERVED63
Definition: MIMXRT1021.h:943
kXBARA1_OutputRESERVED65
@ kXBARA1_OutputRESERVED65
Definition: MIMXRT1021.h:945
kXBARA1_OutputEnc1PhaseBInput
@ kXBARA1_OutputEnc1PhaseBInput
Definition: MIMXRT1021.h:947
kXBARA1_OutputAdcEtcTrig02
@ kXBARA1_OutputAdcEtcTrig02
Definition: MIMXRT1021.h:985
kXBARA1_OutputFlexpwm2Exta0
@ kXBARA1_OutputFlexpwm2Exta0
Definition: MIMXRT1021.h:920
kXBARA1_OutputFlexpwm2ExtForce
@ kXBARA1_OutputFlexpwm2ExtForce
Definition: MIMXRT1021.h:931
kXBARA1_OutputIomuxXbarInout04
@ kXBARA1_OutputIomuxXbarInout04
Definition: MIMXRT1021.h:884
kXBARA1_OutputRESERVED80
@ kXBARA1_OutputRESERVED80
Definition: MIMXRT1021.h:960
kXBARA1_OutputIomuxXbarInout16
@ kXBARA1_OutputIomuxXbarInout16
Definition: MIMXRT1021.h:896
kXBARA1_OutputRESERVED64
@ kXBARA1_OutputRESERVED64
Definition: MIMXRT1021.h:944
kXBARB2_OutputAoi1In09
@ kXBARB2_OutputAoi1In09
Definition: MIMXRT1021.h:1021
kXBARA1_OutputRESERVED25
@ kXBARA1_OutputRESERVED25
Definition: MIMXRT1021.h:905
kXBARA1_OutputLpuart4TrgInput
@ kXBARA1_OutputLpuart4TrgInput
Definition: MIMXRT1021.h:1002
kXBARA1_OutputAcmp1Sample
@ kXBARA1_OutputAcmp1Sample
Definition: MIMXRT1021.h:900
kXBARA1_OutputAdcEtcTrig13
@ kXBARA1_OutputAdcEtcTrig13
Definition: MIMXRT1021.h:990
kXBARA1_OutputLpi2c2TrgInput
@ kXBARA1_OutputLpi2c2TrgInput
Definition: MIMXRT1021.h:992
kXBARA1_OutputFlexpwm1ExtSync2
@ kXBARA1_OutputFlexpwm1ExtSync2
Definition: MIMXRT1021.h:912
kXBARA1_OutputRESERVED54
@ kXBARA1_OutputRESERVED54
Definition: MIMXRT1021.h:934
kXBARA1_OutputIomuxXbarInout15
@ kXBARA1_OutputIomuxXbarInout15
Definition: MIMXRT1021.h:895
kXBARA1_OutputFlexpwm2ExtSync0
@ kXBARA1_OutputFlexpwm2ExtSync0
Definition: MIMXRT1021.h:924
kXBARA1_OutputFlexpwm1ExtClk
@ kXBARA1_OutputFlexpwm1ExtClk
Definition: MIMXRT1021.h:914
kXBARB2_OutputAoi1In13
@ kXBARB2_OutputAoi1In13
Definition: MIMXRT1021.h:1025
kXBARA1_OutputRESERVED130
@ kXBARA1_OutputRESERVED130
Definition: MIMXRT1021.h:1010
kXBARA1_OutputIomuxXbarInout10
@ kXBARA1_OutputIomuxXbarInout10
Definition: MIMXRT1021.h:890
kXBARA1_OutputAdcEtcTrig10
@ kXBARA1_OutputAdcEtcTrig10
Definition: MIMXRT1021.h:987
kXBARA1_OutputRESERVED62
@ kXBARA1_OutputRESERVED62
Definition: MIMXRT1021.h:942
kXBARA1_OutputIomuxXbarInout17
@ kXBARA1_OutputIomuxXbarInout17
Definition: MIMXRT1021.h:897
kXBARA1_OutputIomuxXbarInout19
@ kXBARA1_OutputIomuxXbarInout19
Definition: MIMXRT1021.h:899
kXBARA1_OutputLpi2c1TrgInput
@ kXBARA1_OutputLpi2c1TrgInput
Definition: MIMXRT1021.h:991
kXBARA1_OutputRESERVED83
@ kXBARA1_OutputRESERVED83
Definition: MIMXRT1021.h:963
kXBARA1_OutputLpuart8TrgInput
@ kXBARA1_OutputLpuart8TrgInput
Definition: MIMXRT1021.h:1006
kXBARA1_OutputRESERVED57
@ kXBARA1_OutputRESERVED57
Definition: MIMXRT1021.h:937
kXBARA1_OutputFlexpwm1Exta3
@ kXBARA1_OutputFlexpwm1Exta3
Definition: MIMXRT1021.h:909
kXBARA1_OutputQtimer2Tmr2
@ kXBARA1_OutputQtimer2Tmr2
Definition: MIMXRT1021.h:972
kXBARB2_OutputAoi1In08
@ kXBARB2_OutputAoi1In08
Definition: MIMXRT1021.h:1020
kXBARA1_OutputQtimer1Tmr0
@ kXBARA1_OutputQtimer1Tmr0
Definition: MIMXRT1021.h:966
kXBARA1_OutputEnc2PhaseBInput
@ kXBARA1_OutputEnc2PhaseBInput
Definition: MIMXRT1021.h:952
kXBARA1_OutputRESERVED61
@ kXBARA1_OutputRESERVED61
Definition: MIMXRT1021.h:941
kXBARA1_OutputFlexpwm2ExtSync2
@ kXBARA1_OutputFlexpwm2ExtSync2
Definition: MIMXRT1021.h:926
kXBARA1_OutputRESERVED53
@ kXBARA1_OutputRESERVED53
Definition: MIMXRT1021.h:933
kXBARA1_OutputRESERVED79
@ kXBARA1_OutputRESERVED79
Definition: MIMXRT1021.h:959
kXBARB2_OutputAoi1In04
@ kXBARB2_OutputAoi1In04
Definition: MIMXRT1021.h:1016
kXBARA1_OutputEwmEwmIn
@ kXBARA1_OutputEwmEwmIn
Definition: MIMXRT1021.h:982
kXBARA1_OutputFlexpwm1Exta2
@ kXBARA1_OutputFlexpwm1Exta2
Definition: MIMXRT1021.h:908
kXBARB2_OutputAoi1In12
@ kXBARB2_OutputAoi1In12
Definition: MIMXRT1021.h:1024
kXBARA1_OutputIomuxXbarInout08
@ kXBARA1_OutputIomuxXbarInout08
Definition: MIMXRT1021.h:888
kXBARA1_OutputIomuxXbarInout06
@ kXBARA1_OutputIomuxXbarInout06
Definition: MIMXRT1021.h:886
kXBARA1_OutputRESERVED24
@ kXBARA1_OutputRESERVED24
Definition: MIMXRT1021.h:904
kXBARA1_OutputAdcEtcTrig12
@ kXBARA1_OutputAdcEtcTrig12
Definition: MIMXRT1021.h:989
kXBARA1_OutputFlexpwm1Fault0
@ kXBARA1_OutputFlexpwm1Fault0
Definition: MIMXRT1021.h:915
kXBARA1_OutputFlexpwm1ExtSync1
@ kXBARA1_OutputFlexpwm1ExtSync1
Definition: MIMXRT1021.h:911
kXBARA1_OutputIomuxXbarInout05
@ kXBARA1_OutputIomuxXbarInout05
Definition: MIMXRT1021.h:885
kXBARB2_OutputAoi1In07
@ kXBARB2_OutputAoi1In07
Definition: MIMXRT1021.h:1019
kXBARA1_OutputIomuxXbarInout07
@ kXBARA1_OutputIomuxXbarInout07
Definition: MIMXRT1021.h:887
kXBARA1_OutputAdcEtcTrig11
@ kXBARA1_OutputAdcEtcTrig11
Definition: MIMXRT1021.h:988
kXBARA1_OutputLpuart6TrgInput
@ kXBARA1_OutputLpuart6TrgInput
Definition: MIMXRT1021.h:1004
kXBARA1_OutputRESERVED101
@ kXBARA1_OutputRESERVED101
Definition: MIMXRT1021.h:981
kXBARA1_OutputFlexpwm2Exta1
@ kXBARA1_OutputFlexpwm2Exta1
Definition: MIMXRT1021.h:921
kXBARB2_OutputAoi1In00
@ kXBARB2_OutputAoi1In00
Definition: MIMXRT1021.h:1012
kXBARA1_OutputRESERVED84
@ kXBARA1_OutputRESERVED84
Definition: MIMXRT1021.h:964
kXBARA1_OutputFlexpwm2ExtSync1
@ kXBARA1_OutputFlexpwm2ExtSync1
Definition: MIMXRT1021.h:925
kXBARA1_OutputLpi2c4TrgInput
@ kXBARA1_OutputLpi2c4TrgInput
Definition: MIMXRT1021.h:994
kXBARA1_OutputAcmp2Sample
@ kXBARA1_OutputAcmp2Sample
Definition: MIMXRT1021.h:901
kXBARA1_OutputLpi2c3TrgInput
@ kXBARA1_OutputLpi2c3TrgInput
Definition: MIMXRT1021.h:993
kXBARA1_OutputIomuxXbarInout12
@ kXBARA1_OutputIomuxXbarInout12
Definition: MIMXRT1021.h:892
kXBARB2_OutputAoi1In15
@ kXBARB2_OutputAoi1In15
Definition: MIMXRT1021.h:1027
kXBARA1_OutputFlexpwm1ExtSync0
@ kXBARA1_OutputFlexpwm1ExtSync0
Definition: MIMXRT1021.h:910
kXBARA1_OutputFlexpwm2ExtSync3
@ kXBARA1_OutputFlexpwm2ExtSync3
Definition: MIMXRT1021.h:927
kXBARA1_OutputFlexpwm2Fault1
@ kXBARA1_OutputFlexpwm2Fault1
Definition: MIMXRT1021.h:930
kXBARA1_OutputFlexpwm2Fault0
@ kXBARA1_OutputFlexpwm2Fault0
Definition: MIMXRT1021.h:929
kXBARB2_OutputAoi1In14
@ kXBARB2_OutputAoi1In14
Definition: MIMXRT1021.h:1026
kXBARA1_OutputFlexpwm1Fault1
@ kXBARA1_OutputFlexpwm1Fault1
Definition: MIMXRT1021.h:916
kXBARA1_OutputEnc2Trigger
@ kXBARA1_OutputEnc2Trigger
Definition: MIMXRT1021.h:955
kXBARA1_OutputLpuart3TrgInput
@ kXBARA1_OutputLpuart3TrgInput
Definition: MIMXRT1021.h:1001
kXBARA1_OutputRESERVED94
@ kXBARA1_OutputRESERVED94
Definition: MIMXRT1021.h:974
kXBARB2_OutputAoi1In10
@ kXBARB2_OutputAoi1In10
Definition: MIMXRT1021.h:1022
kXBARA1_OutputQtimer1Tmr1
@ kXBARA1_OutputQtimer1Tmr1
Definition: MIMXRT1021.h:967
kXBARA1_OutputEnc1Home
@ kXBARA1_OutputEnc1Home
Definition: MIMXRT1021.h:949
kXBARA1_OutputDmaChMuxReq31
@ kXBARA1_OutputDmaChMuxReq31
Definition: MIMXRT1021.h:881
kXBARA1_OutputFlexpwm2ExtClk
@ kXBARA1_OutputFlexpwm2ExtClk
Definition: MIMXRT1021.h:928
kXBARA1_OutputEnc1Trigger
@ kXBARA1_OutputEnc1Trigger
Definition: MIMXRT1021.h:950
kXBARA1_OutputIomuxXbarInout14
@ kXBARA1_OutputIomuxXbarInout14
Definition: MIMXRT1021.h:894
kXBARA1_OutputQtimer1Tmr3
@ kXBARA1_OutputQtimer1Tmr3
Definition: MIMXRT1021.h:969
kXBARA1_OutputQtimer2Tmr0
@ kXBARA1_OutputQtimer2Tmr0
Definition: MIMXRT1021.h:970
kXBARA1_OutputDmaChMuxReq30
@ kXBARA1_OutputDmaChMuxReq30
Definition: MIMXRT1021.h:880
kXBARA1_OutputRESERVED56
@ kXBARA1_OutputRESERVED56
Definition: MIMXRT1021.h:936
kXBARA1_OutputRESERVED95
@ kXBARA1_OutputRESERVED95
Definition: MIMXRT1021.h:975
kXBARA1_OutputRESERVED76
@ kXBARA1_OutputRESERVED76
Definition: MIMXRT1021.h:956
kXBARA1_OutputIomuxXbarInout09
@ kXBARA1_OutputIomuxXbarInout09
Definition: MIMXRT1021.h:889
kXBARA1_OutputLpspi1TrgInput
@ kXBARA1_OutputLpspi1TrgInput
Definition: MIMXRT1021.h:995
kXBARA1_OutputAdcEtcTrig01
@ kXBARA1_OutputAdcEtcTrig01
Definition: MIMXRT1021.h:984
kXBARB2_OutputAoi1In06
@ kXBARB2_OutputAoi1In06
Definition: MIMXRT1021.h:1018
kXBARB2_OutputAoi1In03
@ kXBARB2_OutputAoi1In03
Definition: MIMXRT1021.h:1015
kXBARA1_OutputRESERVED52
@ kXBARA1_OutputRESERVED52
Definition: MIMXRT1021.h:932
kXBARA1_OutputLpuart5TrgInput
@ kXBARA1_OutputLpuart5TrgInput
Definition: MIMXRT1021.h:1003
kXBARA1_OutputIomuxXbarInout18
@ kXBARA1_OutputIomuxXbarInout18
Definition: MIMXRT1021.h:898
kXBARA1_OutputLpspi4TrgInput
@ kXBARA1_OutputLpspi4TrgInput
Definition: MIMXRT1021.h:998
kXBARA1_OutputDmaChMuxReq95
@ kXBARA1_OutputDmaChMuxReq95
Definition: MIMXRT1021.h:883
kXBARA1_OutputRESERVED58
@ kXBARA1_OutputRESERVED58
Definition: MIMXRT1021.h:938
kXBARA1_OutputRESERVED81
@ kXBARA1_OutputRESERVED81
Definition: MIMXRT1021.h:961
kXBARB2_OutputAoi1In05
@ kXBARB2_OutputAoi1In05
Definition: MIMXRT1021.h:1017
kXBARA1_OutputRESERVED60
@ kXBARA1_OutputRESERVED60
Definition: MIMXRT1021.h:940
kXBARA1_OutputFlexpwm12Fault3
@ kXBARA1_OutputFlexpwm12Fault3
Definition: MIMXRT1021.h:918
kXBARA1_OutputDmaChMuxReq94
@ kXBARA1_OutputDmaChMuxReq94
Definition: MIMXRT1021.h:882
kXBARA1_OutputLpuart2TrgInput
@ kXBARA1_OutputLpuart2TrgInput
Definition: MIMXRT1021.h:1000
kXBARA1_OutputFlexpwm1ExtSync3
@ kXBARA1_OutputFlexpwm1ExtSync3
Definition: MIMXRT1021.h:913
kXBARA1_OutputRESERVED77
@ kXBARA1_OutputRESERVED77
Definition: MIMXRT1021.h:957
kXBARA1_OutputRESERVED97
@ kXBARA1_OutputRESERVED97
Definition: MIMXRT1021.h:977
kXBARA1_OutputLpspi2TrgInput
@ kXBARA1_OutputLpspi2TrgInput
Definition: MIMXRT1021.h:996
kXBARA1_OutputAcmp3Sample
@ kXBARA1_OutputAcmp3Sample
Definition: MIMXRT1021.h:902
kXBARA1_OutputLpspi3TrgInput
@ kXBARA1_OutputLpspi3TrgInput
Definition: MIMXRT1021.h:997
kXBARA1_OutputAdcEtcTrig03
@ kXBARA1_OutputAdcEtcTrig03
Definition: MIMXRT1021.h:986
kXBARA1_OutputEnc2Index
@ kXBARA1_OutputEnc2Index
Definition: MIMXRT1021.h:953
kXBARA1_OutputFlexpwm2Exta2
@ kXBARA1_OutputFlexpwm2Exta2
Definition: MIMXRT1021.h:922
kXBARA1_OutputFlexpwm12Fault2
@ kXBARA1_OutputFlexpwm12Fault2
Definition: MIMXRT1021.h:917
kXBARA1_OutputFlexpwm1Exta1
@ kXBARA1_OutputFlexpwm1Exta1
Definition: MIMXRT1021.h:907
kXBARA1_OutputRESERVED99
@ kXBARA1_OutputRESERVED99
Definition: MIMXRT1021.h:979
kXBARA1_OutputIomuxXbarInout11
@ kXBARA1_OutputIomuxXbarInout11
Definition: MIMXRT1021.h:891
kXBARA1_OutputRESERVED78
@ kXBARA1_OutputRESERVED78
Definition: MIMXRT1021.h:958
kXBARB2_OutputAoi1In02
@ kXBARB2_OutputAoi1In02
Definition: MIMXRT1021.h:1014
kXBARA1_OutputRESERVED129
@ kXBARA1_OutputRESERVED129
Definition: MIMXRT1021.h:1009
kXBARB2_OutputAoi1In01
@ kXBARB2_OutputAoi1In01
Definition: MIMXRT1021.h:1013
kXBARA1_OutputLpuart1TrgInput
@ kXBARA1_OutputLpuart1TrgInput
Definition: MIMXRT1021.h:999
kXBARA1_OutputFlexpwm2Exta3
@ kXBARA1_OutputFlexpwm2Exta3
Definition: MIMXRT1021.h:923
kXBARA1_OutputFlexio1TriggerIn0
@ kXBARA1_OutputFlexio1TriggerIn0
Definition: MIMXRT1021.h:1007
kXBARA1_OutputQtimer1Tmr2
@ kXBARA1_OutputQtimer1Tmr2
Definition: MIMXRT1021.h:968
kXBARA1_OutputRESERVED85
@ kXBARA1_OutputRESERVED85
Definition: MIMXRT1021.h:965
kXBARA1_OutputRESERVED100
@ kXBARA1_OutputRESERVED100
Definition: MIMXRT1021.h:980
kXBARA1_OutputQtimer2Tmr3
@ kXBARA1_OutputQtimer2Tmr3
Definition: MIMXRT1021.h:973
kXBARA1_OutputRESERVED96
@ kXBARA1_OutputRESERVED96
Definition: MIMXRT1021.h:976
kXBARA1_OutputAcmp4Sample
@ kXBARA1_OutputAcmp4Sample
Definition: MIMXRT1021.h:903
kXBARA1_OutputRESERVED98
@ kXBARA1_OutputRESERVED98
Definition: MIMXRT1021.h:978
kXBARA1_OutputQtimer2Tmr1
@ kXBARA1_OutputQtimer2Tmr1
Definition: MIMXRT1021.h:971
kXBARB2_OutputAoi1In11
@ kXBARB2_OutputAoi1In11
Definition: MIMXRT1021.h:1023
kXBARA1_OutputFlexio1TriggerIn1
@ kXBARA1_OutputFlexio1TriggerIn1
Definition: MIMXRT1021.h:1008
kXBARA1_OutputAdcEtcTrig00
@ kXBARA1_OutputAdcEtcTrig00
Definition: MIMXRT1021.h:983
kXBARA1_OutputRESERVED59
@ kXBARA1_OutputRESERVED59
Definition: MIMXRT1021.h:939
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14
Definition: MIMXRT1021.h:564
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01
Definition: MIMXRT1021.h:551
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
Definition: MIMXRT1021.h:512
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13
Definition: MIMXRT1021.h:521
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
Definition: MIMXRT1021.h:585
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06
Definition: MIMXRT1021.h:556
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03
Definition: MIMXRT1021.h:511
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
Definition: MIMXRT1021.h:583
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09
Definition: MIMXRT1021.h:598
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15
Definition: MIMXRT1021.h:523
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34
Definition: MIMXRT1021.h:542
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15
Definition: MIMXRT1021.h:565
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06
Definition: MIMXRT1021.h:595
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11
Definition: MIMXRT1021.h:519
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
Definition: MIMXRT1021.h:584
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10
Definition: MIMXRT1021.h:560
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
Definition: MIMXRT1021.h:515
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30
Definition: MIMXRT1021.h:538
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
Definition: MIMXRT1021.h:580
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21
Definition: MIMXRT1021.h:529
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
Definition: MIMXRT1021.h:568
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04
Definition: MIMXRT1021.h:554
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
Definition: MIMXRT1021.h:570
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10
Definition: MIMXRT1021.h:518
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08
Definition: MIMXRT1021.h:558
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18
Definition: MIMXRT1021.h:526
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
Definition: MIMXRT1021.h:581
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16
Definition: MIMXRT1021.h:524
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
Definition: MIMXRT1021.h:573
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09
Definition: MIMXRT1021.h:517
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07
Definition: MIMXRT1021.h:557
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35
Definition: MIMXRT1021.h:543
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
Definition: MIMXRT1021.h:587
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
Definition: MIMXRT1021.h:577
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
Definition: MIMXRT1021.h:531
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1021.h:593
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
Definition: MIMXRT1021.h:552
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38
Definition: MIMXRT1021.h:546
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
Definition: MIMXRT1021.h:534
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00
Definition: MIMXRT1021.h:550
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
Definition: MIMXRT1021.h:530
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1021.h:589
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1021.h:594
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05
Definition: MIMXRT1021.h:555
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
Definition: MIMXRT1021.h:514
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33
Definition: MIMXRT1021.h:541
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39
Definition: MIMXRT1021.h:547
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
Definition: MIMXRT1021.h:579
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
Definition: MIMXRT1021.h:536
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14
Definition: MIMXRT1021.h:522
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
Definition: MIMXRT1021.h:586
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
Definition: MIMXRT1021.h:574
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10
Definition: MIMXRT1021.h:599
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
Definition: MIMXRT1021.h:544
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
Definition: MIMXRT1021.h:569
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41
Definition: MIMXRT1021.h:549
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
Definition: MIMXRT1021.h:545
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11
Definition: MIMXRT1021.h:600
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
Definition: MIMXRT1021.h:533
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
Definition: MIMXRT1021.h:535
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1021.h:590
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
Definition: MIMXRT1021.h:567
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
Definition: MIMXRT1021.h:572
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02
Definition: MIMXRT1021.h:510
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
Definition: MIMXRT1021.h:537
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
Definition: MIMXRT1021.h:516
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
Definition: MIMXRT1021.h:563
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08
Definition: MIMXRT1021.h:597
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1021.h:591
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
Definition: MIMXRT1021.h:571
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
Definition: MIMXRT1021.h:576
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01
Definition: MIMXRT1021.h:509
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00
Definition: MIMXRT1021.h:508
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12
Definition: MIMXRT1021.h:520
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_06
Definition: MIMXRT1021.h:588
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
Definition: MIMXRT1021.h:513
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19
Definition: MIMXRT1021.h:527
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
Definition: MIMXRT1021.h:540
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
Definition: MIMXRT1021.h:566
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17
Definition: MIMXRT1021.h:525
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07
Definition: MIMXRT1021.h:596
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20
Definition: MIMXRT1021.h:528
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
Definition: MIMXRT1021.h:578
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
Definition: MIMXRT1021.h:562
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
Definition: MIMXRT1021.h:553
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
Definition: MIMXRT1021.h:575
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11
Definition: MIMXRT1021.h:561
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1021.h:592
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
Definition: MIMXRT1021.h:539
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40
Definition: MIMXRT1021.h:548
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
Definition: MIMXRT1021.h:582
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09
Definition: MIMXRT1021.h:559
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
Definition: MIMXRT1021.h:532
kIOMUXC_QTIMER2_TIMER0_INPUT_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER0_INPUT_SELECT_INPUT
Definition: MIMXRT1021.h:685
kIOMUXC_XBAR1_IN16_SELECT_INPUT
@ kIOMUXC_XBAR1_IN16_SELECT_INPUT
Definition: MIMXRT1021.h:719
kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT
Definition: MIMXRT1021.h:643
kIOMUXC_SAI3_MCLK_SELECT_INPUT
@ kIOMUXC_SAI3_MCLK_SELECT_INPUT
Definition: MIMXRT1021.h:704
kIOMUXC_NMI_SELECT_INPUT
@ kIOMUXC_NMI_SELECT_INPUT
Definition: MIMXRT1021.h:680
kIOMUXC_LPSPI1_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI1_SDI_SELECT_INPUT
Definition: MIMXRT1021.h:654
kIOMUXC_XBAR1_IN13_SELECT_INPUT
@ kIOMUXC_XBAR1_IN13_SELECT_INPUT
Definition: MIMXRT1021.h:723
kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT
Definition: MIMXRT1021.h:634
kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1021.h:707
kIOMUXC_QTIMER1_TIMER1_INPUT_SELECT_INPUT
@ kIOMUXC_QTIMER1_TIMER1_INPUT_SELECT_INPUT
Definition: MIMXRT1021.h:682
kIOMUXC_LPI2C4_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C4_SCL_SELECT_INPUT
Definition: MIMXRT1021.h:650
kIOMUXC_USDHC1_WP_SELECT_INPUT
@ kIOMUXC_USDHC1_WP_SELECT_INPUT
Definition: MIMXRT1021.h:714
kIOMUXC_LPUART8_RX_SELECT_INPUT
@ kIOMUXC_LPUART8_RX_SELECT_INPUT
Definition: MIMXRT1021.h:678
kIOMUXC_XBAR1_IN17_SELECT_INPUT
@ kIOMUXC_XBAR1_IN17_SELECT_INPUT
Definition: MIMXRT1021.h:720
kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT
Definition: MIMXRT1021.h:632
kIOMUXC_XBAR1_IN15_SELECT_INPUT
@ kIOMUXC_XBAR1_IN15_SELECT_INPUT
Definition: MIMXRT1021.h:718
kIOMUXC_LPI2C2_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C2_SDA_SELECT_INPUT
Definition: MIMXRT1021.h:647
kIOMUXC_LPUART4_RX_SELECT_INPUT
@ kIOMUXC_LPUART4_RX_SELECT_INPUT
Definition: MIMXRT1021.h:670
kIOMUXC_QTIMER1_TIMER2_INPUT_SELECT_INPUT
@ kIOMUXC_QTIMER1_TIMER2_INPUT_SELECT_INPUT
Definition: MIMXRT1021.h:683
kIOMUXC_QTIMER1_TIMER0_INPUT_SELECT_INPUT
@ kIOMUXC_QTIMER1_TIMER0_INPUT_SELECT_INPUT
Definition: MIMXRT1021.h:681
kIOMUXC_LPSPI2_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI2_SDO_SELECT_INPUT
Definition: MIMXRT1021.h:659
kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT
Definition: MIMXRT1021.h:641
kIOMUXC_FLEXCAN2_RX_SELECT_INPUT
@ kIOMUXC_FLEXCAN2_RX_SELECT_INPUT
Definition: MIMXRT1021.h:622
kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT
Definition: MIMXRT1021.h:625
kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1021.h:690
kIOMUXC_SEMC_READY_SELECT_INPUT
@ kIOMUXC_SEMC_READY_SELECT_INPUT
Definition: MIMXRT1021.h:710
kIOMUXC_XBAR1_IN14_SELECT_INPUT
@ kIOMUXC_XBAR1_IN14_SELECT_INPUT
Definition: MIMXRT1021.h:717
kIOMUXC_LPUART8_TX_SELECT_INPUT
@ kIOMUXC_LPUART8_TX_SELECT_INPUT
Definition: MIMXRT1021.h:679
kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT
Definition: MIMXRT1021.h:628
kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT
Definition: MIMXRT1021.h:639
kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1021.h:708
kIOMUXC_LPSPI2_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI2_SDI_SELECT_INPUT
Definition: MIMXRT1021.h:658
kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1021.h:702
kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT
Definition: MIMXRT1021.h:627
kIOMUXC_LPUART6_RX_SELECT_INPUT
@ kIOMUXC_LPUART6_RX_SELECT_INPUT
Definition: MIMXRT1021.h:674
kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT
Definition: MIMXRT1021.h:623
kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT
Definition: MIMXRT1021.h:626
kIOMUXC_XBAR1_IN18_SELECT_INPUT
@ kIOMUXC_XBAR1_IN18_SELECT_INPUT
Definition: MIMXRT1021.h:724
kIOMUXC_USDHC2_WP_SELECT_INPUT
@ kIOMUXC_USDHC2_WP_SELECT_INPUT
Definition: MIMXRT1021.h:716
kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT
@ kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1021.h:700
kIOMUXC_LPSPI4_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI4_SDO_SELECT_INPUT
Definition: MIMXRT1021.h:663
kIOMUXC_ENET_RX_ERR_SELECT_INPUT
@ kIOMUXC_ENET_RX_ERR_SELECT_INPUT
Definition: MIMXRT1021.h:619
kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1021.h:701
kIOMUXC_FLEXCAN1_RX_SELECT_INPUT
@ kIOMUXC_FLEXCAN1_RX_SELECT_INPUT
Definition: MIMXRT1021.h:621
kIOMUXC_QTIMER2_TIMER1_INPUT_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER1_INPUT_SELECT_INPUT
Definition: MIMXRT1021.h:686
kIOMUXC_USB_OTG_OC_SELECT_INPUT
@ kIOMUXC_USB_OTG_OC_SELECT_INPUT
Definition: MIMXRT1021.h:712
kIOMUXC_XBAR1_IN10_SELECT_INPUT
@ kIOMUXC_XBAR1_IN10_SELECT_INPUT
Definition: MIMXRT1021.h:721
kIOMUXC_LPSPI2_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI2_SCK_SELECT_INPUT
Definition: MIMXRT1021.h:657
kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT
Definition: MIMXRT1021.h:633
kIOMUXC_SAI2_MCLK_SELECT_INPUT
@ kIOMUXC_SAI2_MCLK_SELECT_INPUT
Definition: MIMXRT1021.h:698
kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT
Definition: MIMXRT1021.h:636
kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT
Definition: MIMXRT1021.h:635
kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1021.h:697
kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT
Definition: MIMXRT1021.h:630
kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT
Definition: MIMXRT1021.h:637
kIOMUXC_ENET_RX_EN_SELECT_INPUT
@ kIOMUXC_ENET_RX_EN_SELECT_INPUT
Definition: MIMXRT1021.h:618
kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT
Definition: MIMXRT1021.h:629
kIOMUXC_LPI2C3_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C3_SDA_SELECT_INPUT
Definition: MIMXRT1021.h:649
kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1021.h:699
kIOMUXC_QTIMER1_TIMER3_INPUT_SELECT_INPUT
@ kIOMUXC_QTIMER1_TIMER3_INPUT_SELECT_INPUT
Definition: MIMXRT1021.h:684
kIOMUXC_XBAR1_IN12_SELECT_INPUT
@ kIOMUXC_XBAR1_IN12_SELECT_INPUT
Definition: MIMXRT1021.h:722
kIOMUXC_QTIMER2_TIMER2_INPUT_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER2_INPUT_SELECT_INPUT
Definition: MIMXRT1021.h:687
kIOMUXC_LPUART7_RX_SELECT_INPUT
@ kIOMUXC_LPUART7_RX_SELECT_INPUT
Definition: MIMXRT1021.h:676
kIOMUXC_XBAR1_IN19_SELECT_INPUT
@ kIOMUXC_XBAR1_IN19_SELECT_INPUT
Definition: MIMXRT1021.h:725
kIOMUXC_CCM_PMIC_READY_SELECT_INPUT
@ kIOMUXC_CCM_PMIC_READY_SELECT_INPUT
Definition: MIMXRT1021.h:613
kIOMUXC_ENET_RMII_SELECT_INPUT
@ kIOMUXC_ENET_RMII_SELECT_INPUT
Definition: MIMXRT1021.h:614
kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT
Definition: MIMXRT1021.h:624
kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT
Definition: MIMXRT1021.h:692
kIOMUXC_LPSPI4_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI4_SCK_SELECT_INPUT
Definition: MIMXRT1021.h:661
kIOMUXC_LPSPI1_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI1_SDO_SELECT_INPUT
Definition: MIMXRT1021.h:655
kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1021.h:709
kIOMUXC_ENET_RX_DATA1_SELECT_INPUT
@ kIOMUXC_ENET_RX_DATA1_SELECT_INPUT
Definition: MIMXRT1021.h:617
kIOMUXC_LPSPI1_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI1_PCS0_SELECT_INPUT
Definition: MIMXRT1021.h:652
kIOMUXC_SAI3_RX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI3_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1021.h:705
kIOMUXC_LPUART6_TX_SELECT_INPUT
@ kIOMUXC_LPUART6_TX_SELECT_INPUT
Definition: MIMXRT1021.h:675
kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT
Definition: MIMXRT1021.h:640
kIOMUXC_LPI2C1_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C1_SDA_SELECT_INPUT
Definition: MIMXRT1021.h:645
kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1021.h:691
kIOMUXC_USDHC2_CD_B_SELECT_INPUT
@ kIOMUXC_USDHC2_CD_B_SELECT_INPUT
Definition: MIMXRT1021.h:715
kIOMUXC_LPUART4_CTS_B_SELECT_INPUT
@ kIOMUXC_LPUART4_CTS_B_SELECT_INPUT
Definition: MIMXRT1021.h:669
kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1021.h:695
kIOMUXC_LPSPI1_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI1_SCK_SELECT_INPUT
Definition: MIMXRT1021.h:653
kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT
@ kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1021.h:706
kIOMUXC_LPUART2_CTS_B_SELECT_INPUT
@ kIOMUXC_LPUART2_CTS_B_SELECT_INPUT
Definition: MIMXRT1021.h:664
kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT
Definition: MIMXRT1021.h:693
kIOMUXC_LPI2C2_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C2_SCL_SELECT_INPUT
Definition: MIMXRT1021.h:646
kIOMUXC_LPSPI4_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI4_PCS0_SELECT_INPUT
Definition: MIMXRT1021.h:660
kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1021.h:696
kIOMUXC_QTIMER2_TIMER3_INPUT_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER3_INPUT_SELECT_INPUT
Definition: MIMXRT1021.h:688
kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT
@ kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT
Definition: MIMXRT1021.h:612
kIOMUXC_LPUART3_RX_SELECT_INPUT
@ kIOMUXC_LPUART3_RX_SELECT_INPUT
Definition: MIMXRT1021.h:667
kIOMUXC_LPI2C1_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C1_SCL_SELECT_INPUT
Definition: MIMXRT1021.h:644
kIOMUXC_LPUART2_RX_SELECT_INPUT
@ kIOMUXC_LPUART2_RX_SELECT_INPUT
Definition: MIMXRT1021.h:665
kIOMUXC_SAI1_MCLK_SELECT_INPUT
@ kIOMUXC_SAI1_MCLK_SELECT_INPUT
Definition: MIMXRT1021.h:689
kIOMUXC_LPI2C3_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C3_SCL_SELECT_INPUT
Definition: MIMXRT1021.h:648
kIOMUXC_LPUART2_TX_SELECT_INPUT
@ kIOMUXC_LPUART2_TX_SELECT_INPUT
Definition: MIMXRT1021.h:666
kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT
Definition: MIMXRT1021.h:694
kIOMUXC_LPUART5_TX_SELECT_INPUT
@ kIOMUXC_LPUART5_TX_SELECT_INPUT
Definition: MIMXRT1021.h:673
kIOMUXC_ENET_RX_DATA0_SELECT_INPUT
@ kIOMUXC_ENET_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1021.h:616
kIOMUXC_LPSPI2_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI2_PCS0_SELECT_INPUT
Definition: MIMXRT1021.h:656
kIOMUXC_ENET_TX_CLK_SELECT_INPUT
@ kIOMUXC_ENET_TX_CLK_SELECT_INPUT
Definition: MIMXRT1021.h:620
kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT
Definition: MIMXRT1021.h:642
kIOMUXC_SPDIF_IN_SELECT_INPUT
@ kIOMUXC_SPDIF_IN_SELECT_INPUT
Definition: MIMXRT1021.h:711
kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1021.h:703
kIOMUXC_LPUART7_TX_SELECT_INPUT
@ kIOMUXC_LPUART7_TX_SELECT_INPUT
Definition: MIMXRT1021.h:677
kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT
Definition: MIMXRT1021.h:638
kIOMUXC_LPUART5_RX_SELECT_INPUT
@ kIOMUXC_LPUART5_RX_SELECT_INPUT
Definition: MIMXRT1021.h:672
kIOMUXC_LPUART4_TX_SELECT_INPUT
@ kIOMUXC_LPUART4_TX_SELECT_INPUT
Definition: MIMXRT1021.h:671
kIOMUXC_LPUART3_TX_SELECT_INPUT
@ kIOMUXC_LPUART3_TX_SELECT_INPUT
Definition: MIMXRT1021.h:668
kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT
Definition: MIMXRT1021.h:631
kIOMUXC_LPSPI4_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI4_SDI_SELECT_INPUT
Definition: MIMXRT1021.h:662
kIOMUXC_USDHC1_CD_B_SELECT_INPUT
@ kIOMUXC_USDHC1_CD_B_SELECT_INPUT
Definition: MIMXRT1021.h:713
kIOMUXC_LPI2C4_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C4_SDA_SELECT_INPUT
Definition: MIMXRT1021.h:651
kIOMUXC_ENET_MDIO_SELECT_INPUT
@ kIOMUXC_ENET_MDIO_SELECT_INPUT
Definition: MIMXRT1021.h:615
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
Definition: MIMXRT1021.h:463
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21
Definition: MIMXRT1021.h:417
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05
Definition: MIMXRT1021.h:443
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10
Definition: MIMXRT1021.h:406
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
Definition: MIMXRT1021.h:433
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
Definition: MIMXRT1021.h:461
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09
Definition: MIMXRT1021.h:405
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18
Definition: MIMXRT1021.h:414
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35
Definition: MIMXRT1021.h:431
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
Definition: MIMXRT1021.h:467
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00
Definition: MIMXRT1021.h:396
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
Definition: MIMXRT1021.h:475
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15
Definition: MIMXRT1021.h:453
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11
Definition: MIMXRT1021.h:449
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
Definition: MIMXRT1021.h:462
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
Definition: MIMXRT1021.h:400
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
Definition: MIMXRT1021.h:441
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
Definition: MIMXRT1021.h:402
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
Definition: MIMXRT1021.h:455
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04
Definition: MIMXRT1021.h:442
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
Definition: MIMXRT1021.h:440
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15
Definition: MIMXRT1021.h:411
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
Definition: MIMXRT1021.h:473
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12
Definition: MIMXRT1021.h:408
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
Definition: MIMXRT1021.h:428
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40
Definition: MIMXRT1021.h:436
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
Definition: MIMXRT1021.h:457
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
Definition: MIMXRT1021.h:458
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08
Definition: MIMXRT1021.h:485
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09
Definition: MIMXRT1021.h:486
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
Definition: MIMXRT1021.h:419
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1021.h:480
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07
Definition: MIMXRT1021.h:484
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38
Definition: MIMXRT1021.h:434
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
Definition: MIMXRT1021.h:450
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34
Definition: MIMXRT1021.h:430
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10
Definition: MIMXRT1021.h:487
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02
Definition: MIMXRT1021.h:398
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06
Definition: MIMXRT1021.h:483
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30
Definition: MIMXRT1021.h:426
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
Definition: MIMXRT1021.h:459
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
Definition: MIMXRT1021.h:464
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
Definition: MIMXRT1021.h:403
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
Definition: MIMXRT1021.h:424
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
Definition: MIMXRT1021.h:454
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14
Definition: MIMXRT1021.h:452
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11
Definition: MIMXRT1021.h:407
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1021.h:477
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39
Definition: MIMXRT1021.h:435
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11
Definition: MIMXRT1021.h:488
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01
Definition: MIMXRT1021.h:397
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01
Definition: MIMXRT1021.h:439
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14
Definition: MIMXRT1021.h:410
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
Definition: MIMXRT1021.h:469
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09
Definition: MIMXRT1021.h:447
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
Definition: MIMXRT1021.h:422
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
Definition: MIMXRT1021.h:427
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33
Definition: MIMXRT1021.h:429
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
Definition: MIMXRT1021.h:471
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1021.h:481
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
Definition: MIMXRT1021.h:421
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
Definition: MIMXRT1021.h:423
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07
Definition: MIMXRT1021.h:445
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16
Definition: MIMXRT1021.h:412
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
Definition: MIMXRT1021.h:432
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03
Definition: MIMXRT1021.h:399
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
Definition: MIMXRT1021.h:465
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20
Definition: MIMXRT1021.h:416
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19
Definition: MIMXRT1021.h:415
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
Definition: MIMXRT1021.h:451
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06
Definition: MIMXRT1021.h:444
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10
Definition: MIMXRT1021.h:448
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
Definition: MIMXRT1021.h:456
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41
Definition: MIMXRT1021.h:437
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_06
Definition: MIMXRT1021.h:476
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
Definition: MIMXRT1021.h:474
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00
Definition: MIMXRT1021.h:438
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1021.h:478
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
Definition: MIMXRT1021.h:466
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
Definition: MIMXRT1021.h:420
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
Definition: MIMXRT1021.h:468
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
Definition: MIMXRT1021.h:470
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
Definition: MIMXRT1021.h:472
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1021.h:482
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1021.h:479
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
Definition: MIMXRT1021.h:401
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13
Definition: MIMXRT1021.h:409
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
Definition: MIMXRT1021.h:460
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
Definition: MIMXRT1021.h:425
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
Definition: MIMXRT1021.h:418
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
Definition: MIMXRT1021.h:404
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08
Definition: MIMXRT1021.h:446
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17
Definition: MIMXRT1021.h:413
ADC_ETC_Type
Definition: MIMXRT1021.h:1422
ADC_Type
Definition: MIMXRT1021.h:1078
AIPSTZ_Type
Definition: MIMXRT1021.h:1882
AOI_Type
Definition: MIMXRT1021.h:2594
BEE_Type
Definition: MIMXRT1021.h:2799
CAN_Type
Definition: MIMXRT1021.h:3101
CCM_ANALOG_Type
Definition: MIMXRT1021.h:5766
CCM_Type
Definition: MIMXRT1021.h:3943
CM7_MCM_Type
Definition: MIMXRT1021.h:7619
CMP_Type
Definition: MIMXRT1021.h:7773
CSU_Type
Definition: MIMXRT1021.h:8023
DCDC_Type
Definition: MIMXRT1021.h:8638
DCP_Type
Definition: MIMXRT1021.h:8963
DMAMUX_Type
Definition: MIMXRT1021.h:13739
DMA_Type
Definition: MIMXRT1021.h:10641
ENC_Type
Definition: MIMXRT1021.h:13817
ENET_Type
Definition: MIMXRT1021.h:14325
EWM_Type
Definition: MIMXRT1021.h:15967
FLEXIO_Type
Definition: MIMXRT1021.h:16087
FLEXRAM_Type
Definition: MIMXRT1021.h:16658
FLEXSPI_Type
Definition: MIMXRT1021.h:16806
GPC_Type
Definition: MIMXRT1021.h:17728
GPIO_Type
Definition: MIMXRT1021.h:17857
GPT_Type
Definition: MIMXRT1021.h:18305
I2S_Type
Definition: MIMXRT1021.h:18595
IOMUXC_GPR_Type
Definition: MIMXRT1021.h:19584
IOMUXC_SNVS_GPR_Type
Definition: MIMXRT1021.h:21965
IOMUXC_SNVS_Type
Definition: MIMXRT1021.h:21457
IOMUXC_Type
Definition: MIMXRT1021.h:19422
KPP_Type
Definition: MIMXRT1021.h:22065
LPI2C_Type
Definition: MIMXRT1021.h:22206
LPSPI_Type
Definition: MIMXRT1021.h:23256
LPUART_Type
Definition: MIMXRT1021.h:23881
OCOTP_Type
Definition: MIMXRT1021.h:24808
PGC_Type
Definition: MIMXRT1021.h:25682
PIT_Type
Definition: MIMXRT1021.h:25819
PMU_Type
Definition: MIMXRT1021.h:25977
PWM_Type
Definition: MIMXRT1021.h:27877
RTWDOG_Type
Definition: MIMXRT1021.h:29520
SEMC_Type
Definition: MIMXRT1021.h:29718
SNVS_Type
Definition: MIMXRT1021.h:30908
SPDIF_Type
Definition: MIMXRT1021.h:32008
SRC_Type
Definition: MIMXRT1021.h:32496
TEMPMON_Type
Definition: MIMXRT1021.h:32734
TMR_Type
Definition: MIMXRT1021.h:32983
TRNG_Type
Definition: MIMXRT1021.h:33471
USBNC_Type
Definition: MIMXRT1021.h:35693
USBPHY_Type
Definition: MIMXRT1021.h:35825
USB_ANALOG_Type
Definition: MIMXRT1021.h:36936
USB_Type
Definition: MIMXRT1021.h:34143
USDHC_Type
Definition: MIMXRT1021.h:37392
WDOG_Type
Definition: MIMXRT1021.h:39041
XBARA_Type
Definition: MIMXRT1021.h:39239
XBARB_Type
Definition: MIMXRT1021.h:40138
XTALOSC24M_Type
Definition: MIMXRT1021.h:40269
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